JPH06333816A - Pattern formation - Google Patents

Abstract

PURPOSE:To make possible the formation of an inversion pattern of resist in one selective electron beam irradiation to the resist by forming resists of different sensitivity characteristics to an electron beam in layers. CONSTITUTION:After electron beam is selectively cast on a positive type resist 12 on a silicon substrate 11 and a latent image 14 of a pattern is formed, an opening part 15 is formed and phosphorus ions 16 are implanted. After the opening part 15 is covered with a negative type resist 17 successively, a surface of the negative type resist 17 is removed. An electron beam 18 is cast all over. After reformation is performed to improve solubility to developer in a part of the positive type resist 12 and to lower that in a part of the negative type resist 17, the originally formed opening part 1 remains, an inversion resist pattern constituted of the negative type resist 17 is formed and BF2 ions 19 are implanted. Thereby, it is possible to form resist patterns which are inverse mutually in one selective electron beam irradiation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method for forming resist patterns in an inverted relationship on a semiconductor substrate.

[0002]

2. Description of the Related Art The progress of semiconductor integration technology is remarkable,
Microfabrication technology is one of the basic technologies that support it. For example, 1990 Symposium on VISI Technology Digest of Technical Papers, pages 13-14 (1990 Symposium on
64 megabit dynamic as described in VLSI Technology Dig. Of Tech. Papers 13-14).
In order to form a random access memory, processing with a minimum dimension of 0.3 μm is required.

As a device structure, a complementary metal oxide semiconductor field effect transistor (Complementary metal oxide semiconductor f)
A field effect transistor (hereinafter referred to as CMOS) structure is adopted.

FIG. 4 shows a sectional shape of a basic structure of a CMOS structure transistor formed on a p-type semiconductor substrate 31. In this way, p (positive) type (left side) and n
(Negative) type (right side) transistor (hereinafter pMOS and n
It is a characteristic of the CMOS structure that the (MOS) is formed as a pair structure on the same substrate.

The pMOS is formed on the n-well region 32, and has an n-type impurity layer 33 for element isolation, a p-type low-concentration diffusion layer 34 and a p-type high-concentration diffusion layer 3 which are source and drain portions.
5, a gate oxide film 36, a gate electrode 37 mainly made of polycrystalline silicon, and a sidewall oxide film 38. on the other hand,
The nMOS is formed on the p-well region 39, and has a p-type impurity layer 40 for element isolation, an n-type low-concentration diffusion layer 41 and a p-type high-concentration diffusion layer 42 that are source and drain portions, a gate oxide film 43, and mainly a multi-layer. A gate electrode 44 made of crystalline silicon,
The sidewall oxide film 45 is formed. The elements are separated from each other by the element isolation selective oxide film 46, and each electrode is in contact with the wiring metal 49 by the metal 48 filling the contact hole formed in the interlayer insulating film 47.

The p-type and n-type regions are mainly formed by implanting ions. In order to form the p-type region, ions of boron (B) or boron difluoride (BF ₂ ) are accelerated and implanted into the opening mainly using the resist as a mask. In order to form the n-type region, phosphorus (P) or arsenic (As) ions are accelerated and implanted at high energy. After the ion implantation, heat treatment is performed to diffuse the ions and form a region.

As can be seen from FIG. 4, pMOS and nMO
In S, the structure is symmetric, and the ion species in each region are different. Conventionally, each region is formed as follows. Here, the formation of the element isolation impurity layer will be described as an example.

FIG. 5A shows a state in which the element isolation selective oxide film 52 is formed on the p-type semiconductor substrate 51 by a known method. An n well region 53 and ap well region 54 are formed on the p type semiconductor substrate 51. The step is present on the p-type semiconductor substrate 51 here because a well-known selective oxidation method is used when forming the well.

Then, as shown in FIG. 5B, after applying the positive resist 55, the positive resist 55 is selectively irradiated with an energy beam 56 such as an electron beam or an ultraviolet ray to develop the positive resist 55.
An opening is formed in 5. As a result, the p-well region 54 is covered here. Therefore, by implanting divalent phosphorus ions accelerated with an acceleration voltage of 200 kV, a phosphorus impurity layer 57 is formed as shown in FIG. 5C. Here, since the p-well region 54 is covered with the positive type resist 55 having a sufficient thickness to prevent the ion implantation into the substrate, no ions are implanted therein. The implantation amount is 10 ¹³ / cm ² .

Next, as shown in FIG. 5D, after the resist is once removed, a positive resist 58 is applied again as described above, and then an energy beam 59 such as an electron beam or an ultraviolet ray 59 is applied.
Are selectively irradiated and developed to form an opening in the positive resist 58. As a result, here, the n-well region 53
To cover. And it was accelerated by the acceleration voltage of 150 kV 1
By implanting valence boron ions, a boron impurity layer 60 is formed as shown in FIG. Again n
Since the well region 53 is covered with the positive type resist 58 having a sufficient thickness to prevent the implantation of ions into the substrate, no ions are implanted therein. The driving amount is 10 ¹³ /
It is cm ² .

After that, the device as shown in FIG. 4 can be formed by going through the steps of forming a gate electrode, forming a diffusion layer to be source and drain portions, forming a contact hole, forming a wiring metal, and the like. .

The pattern forming method using the above-mentioned resist, which is the center of the present invention, will be briefly described below. At present, the method generally used in the formation of semiconductor devices follows the procedure shown in FIG.

First, after cleaning the semiconductor substrate 61 to be processed, it is subjected to a hydrophobizing treatment to increase the adhesion of a thin film mainly made of an organic polymer called a resist to the substrate 61. Resist 6 as shown in FIG.
The two solutions are dropped on the substrate 61, and the resist 62 is applied to the substrate 61 mainly by a method such as spin coating. Then, in order to scatter the solvent in the resist solution, heat treatment (hereinafter referred to as baking) is generally performed. This baking is performed by allowing the substrate to stand for a certain period of time on a hot plate set to a constant temperature.

Then, as shown in FIG. 6B, energy rays 63 such as ultraviolet rays and electron rays are selectively irradiated in accordance with a desired pattern to form a latent image 64 of the pattern. Then, the substrate 61 is immersed in the developing solution. Here, a chemical change occurs in the resist 62 due to the irradiation of the energy rays 63, and in this development processing, a difference occurs in the dissolution rate in the developing solution between the latent image 64 part which is the pattern irradiation part and the pattern non-irradiation part.
A desired pattern can be formed.

When the dissolution speed of the latent image 64 is reduced and this portion remains, a negative resist pattern is obtained as shown in FIG. 6 (c). On the other hand, when the dissolution speed of the latent image 64 part increases and this part melts,
As shown in (d), a positive resist pattern is obtained.

As described above, many steps are required to form one resist pattern. Further, after the step of ion implantation and the like, the resist pattern becomes unnecessary and therefore must be removed, and a step of removing using oxygen plasma or the like is required. In addition, it becomes necessary to perform pattern superposition processing for each of a number of steps, and the working time becomes long. In addition, in order to perform each superposition process, it is necessary to have a margin in design dimensions for superposition, which causes a problem of hindering the improvement of the degree of integration.

[0017]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above,
In forming a CMOS structure, it is necessary to form semiconductors having different conductivity on the same substrate, so it is necessary to cover one semiconductor with a resist in each step of introducing impurities. As can be seen from FIG. 5, the openings of the resist used at the time of ion implantation in the pMOS and the nMOS have an inversion relation to each other. Similarly, when forming the source and drain portions, resist patterns having an inversion relation to each other are used as a mask for ion implantation.
As described above, in forming the CMOS structure, the ion-implanted layers having different conductivity are formed, and the reverse resist pattern is required at that time. Then, it is necessary to selectively irradiate energy rays each time each resist pattern is formed. Here, irradiation of energy rays is performed using an expensive electron beam drawing apparatus or exposure apparatus, and it is necessary to perform the process without using these apparatuses as much as possible and to operate these apparatuses efficiently to improve productivity. Desirable for. Further, as described above, in forming the resist pattern, it is necessary to wash the substrate, apply resist, irradiate energy rays, develop, and remove each time, and an increase in the number of steps cannot be avoided. Moreover, the design area is increased in order to secure the overlapping margin, which hinders the improvement of the degree of integration.

That is, in forming a CMOS structure, the number of steps is inevitably large, and how to reduce the number of steps for improving productivity and how to increase the degree of integration are major problems.

In order to solve these problems, the present invention enables a resist inversion pattern, which is often used in forming a CMOS structure, to selectively irradiate a resist with an energy beam only once. It was made for the purpose of providing a method.

[0020]

Means for solving the problems: Resists having different sensitivity characteristics to energy rays are formed in layers, or a region having resistance to plasma is introduced on the resist surface.

[0021]

According to the present invention, the resist having a certain sensitivity to the energy rays is selectively irradiated with the energy rays to form the openings, and then the steps such as ion implantation are performed. After that, another resist is formed on top of this without removing the resist. Here, the resist surface is ground with oxygen plasma or the like to expose a different type of resist. After that,
A process is performed in which only the resist that remains first is removed.
As a result, only the resist formed later remains. As described above, it is possible to form a pattern having an inversion relationship with the pattern formed first by one selective irradiation of energy rays. Further, since the second resist pattern always has an inversion relationship with respect to the first resist pattern, when the second resist pattern is formed, it is not necessary to perform the alignment process required in the normal semiconductor forming process. . Therefore, the processing time is shortened and the degree of integration is increased.

[0022]

EXAMPLE 1 In this example, it is premised that ions having different conductivity are implanted, and in forming a resist pattern serving as a mask, forming resist patterns having an inversion relationship to each other will be described with reference to FIG. It demonstrates using. The structure of the substrate will be described in the simplest case using a silicon substrate having no element isolation region, but is not limited to this, and a structure including the element isolation region or a laminated structure with another material,
The substrate material may be other than silicon such as GaAs.

For example, a p-type 10 Ω · cm silicon substrate 1
1 is subjected to a known surface treatment. This is a process generally performed in order to adhere a silane coupling agent such as hexamethyldisilazane to the substrate to enhance the adhesiveness of the resist to the substrate. A positive resist 12 (for example, RE-5
000P (registered trademark of Hitachi Chemical Co., Ltd.) is formed to a thickness of 1.5 μm by a known spin coating method.

As shown in FIG. 1 (a), an electron beam 13 having an accelerating voltage of 30 kV is applied to the electron beam drawing apparatus in an amount of 10 μm.
Latent image of the pattern by selectively irradiating with a dose of C / cm ²
4 is formed. After the electron beam irradiation, the positive resist 12 and the silicon substrate 11 are placed in a 2.38% tetramethylammonium hydroxide aqueous solution at room temperature for 3 hours.
Soak for 0 seconds. As a result, as shown in FIG. 1B, the opening 15 with the electron beam 13 irradiation portion selectively removed.
Is formed. After this, monovalent phosphorus ions 16 accelerated at an acceleration voltage of 60 kV were implanted at a dose of 5 × 10 ¹² / cm 3.
Type in ² .

Continuing from this, as shown in FIG.
A negative resist 17 (for example, RD-2000N (registered trademark of Hitachi Chemical Co., Ltd.)) is formed to a thickness of 3.0 μm by a known spin coating method, and the opening 15 is covered with the negative resist 17. Then, the surface of the negative resist 17 is removed by leaving it in oxygen plasma. Here, instead of standing still in oxygen plasma, it may be immersed in a solvent such as acetone that dissolves the resist. As a result, as shown in FIG. 1D, the surface of the positive resist 12 is exposed so that the positive resist 12 coexists with the negative resist 17.

Next, as shown in FIG. 1E, the entire surface is irradiated with an electron beam 18 with an acceleration voltage of 10 kV at a dose of 10 μC / cm ² . An expensive electron beam drawing apparatus is not necessary here because selective irradiation of energy rays is unnecessary, and an inexpensive apparatus having a function of uniformly irradiating an electron beam may be used. As a result, the portion of the positive resist 12 is modified so that the solubility in the developing solution is improved, while the portion of the negative resist 17 is modified so that the solubility in the developing solution is reduced.

Then, the positive resist 1 after electron beam irradiation
2. The negative resist 17 and the silicon substrate 11 are made of tetramethylammonium hydroxide 2.38%.
Immerse in aqueous solution for 30 seconds at room temperature. As a result,
As shown in (f), the opening 15 formed at the beginning remains, and an inverted resist pattern composed of the negative resist 17 is formed. Then, after this, the acceleration voltage 60
BF ₂ ion 19 accelerated by kV, implantation amount 5 ×
Drive at 10 ¹² / cm ² . Next, the negative resist 17 is removed by a known oxygen plasma treatment, and heat treatment is performed at 1100 ° C. to thermally diffuse the implanted ions, whereby regions having different conductivity can be formed.

As described above, in forming the resist patterns which are opposite to each other, it is possible to selectively irradiate the energy rays at one time. Here, the case where the electron beam is used as the energy ray has been described, but the invention is not limited to this.
A particle beam such as an ion beam may be used. Further, the energy rays that are collectively irradiated need not necessarily be the same as the energy rays that are selectively irradiated, and can be selected according to the sensitivity of the resist. An electron beam may be used for selective energy ray irradiation, and an ultraviolet ray may be used for collective energy ray irradiation.

Further, as is apparent from the above description, according to the present invention, the second resist pattern always has an inverted shape with respect to the first resist pattern. Therefore, in forming the second resist pattern, the alignment process required in the normal semiconductor forming process is not necessary, and the so-called "self-alignment process" is performed.
That is, the processing time can be shortened and the degree of integration can be improved.

By the above method, the number of steps can be reduced, and an expensive electron beam drawing apparatus or exposure apparatus can be used more efficiently, so that the processing time can be shortened and high integration can be realized. Therefore, the productivity can be greatly improved.

(Embodiment 2) In the above embodiment, after the second resist is formed, the energy rays are collectively radiated to improve the solubility of the first remaining resist in the developing solution. . Here, the property that the solubility of the resist in the developing solution is changed by the ions is used.
Ions have a very large mass as compared with electrons, so that the range of passage through the resist is small. Therefore, it is necessary to reduce the film thickness of the resist applied by spin coating.

Similar to the first embodiment, for example, p-type 10 Ω.
A known surface treatment is performed on the silicon substrate 11 of cm. A positive resist 12 (RE-5000P (registered trademark of Hitachi Chemical Co., Ltd.)) is formed on this to a thickness of 0.1 μm by a known spin coating method.

As shown in FIG. 2 (a), an electron beam 13 with an accelerating voltage of 30 kV is applied to the inside of the electron beam drawing apparatus.
A latent image 14 of the pattern is formed by selectively irradiating with a dose of 0 μC / cm ² . Then, the positive resist 12 and the silicon substrate 11 after the electron beam irradiation are immersed in a 2.38% tetramethylammonium hydroxide aqueous solution at room temperature for 15 seconds.

As a result, as shown in FIG. 2B, an opening 15 is formed in which the electron beam 13 irradiation portion is selectively removed. After this, monovalent phosphorus ions 16 accelerated at an acceleration voltage of 60 kV are implanted at a dose of 5 × 10 ¹² / cm ² . Here, the positive type resist 12 irradiated with the phosphorus ions 16 has increased solubility in the developing solution as in the case of being irradiated with the electron beam.

Following this, the negative resist 17 (RD
-2000N (registered trademark of Hitachi Chemical Co., Ltd.), thickness of 0.2μ
m is formed by a known spin coating method. As a result, FIG.
As shown in (c), the opening 15 is covered with the negative resist 17. Then, the surface of the negative resist 17 is removed by leaving it in a known oxygen plasma. As a result, as shown in FIG. 2D, the surface of the positive resist 12 is exposed, and a form coexisting with the negative resist 17 can be obtained. Here, as described above, the portion of the positive resist 12 is modified so that the solubility in the developing solution is improved. Therefore, the positive resist 12, the negative resist 17, and the silicon substrate 11 are immersed in a 2.38% tetramethylammonium hydroxide aqueous solution at room temperature for 15 seconds. As a result, as shown in FIG. 2E, the opening 15 formed at the beginning remains, and an inverted resist pattern composed of the negative resist 17 is formed. Then, after this, BF ₂ ions 19 accelerated at an acceleration voltage of 60 kV are implanted with an implantation amount of 5 × 10 ¹² / cm ² . Next, the negative resist 17 is removed by a known oxygen plasma treatment, and heat treatment is performed at 1100 ° C. to thermally diffuse the implanted ions, whereby regions having different conductivity can be formed.

Although the second resist is described here as a negative type, it is not limited to this and a positive type resist may be used. Even when the resist is not completely dissolved by the development, a step formed on the resist surface is used, and the resist pattern is obtained by removing it in a known oxygen plasma and removing the thin resist film thickness. You can
Further, as described above, this embodiment is basically applicable to the case where the film thickness is thin. The appropriate value of the film thickness can be selected depending on the type of ions and the acceleration voltage. In the case of Example 1 in which the film thickness is large, there is no problem because the dissolution of the resist is limited to the surface portion.

(Embodiment 3) In the above embodiment, the method of selectively irradiating energy rays once by forming resists having different sensitivities to energy rays is described. Here, a method in which sensitivity to energy rays may be the same will be described. As the method used here, the technology disclosed in the proceedings 28a-NB-9 (Page 493) of the 39th Joint Lecture on Applied Physics at Spring 1992 (1992) is used.

First, the p-type 10 Ω · cm silicon substrate 21.
Then, a known surface treatment is performed in the same manner as in Example 1. A negative type resist 22 (RD-2000N (registered trademark of Hitachi Chemical Co., Ltd.)) is formed on this to a thickness of 1.5 μm by a known spin coating method. As shown in FIG. 3A, the latent image 24 of the pattern is formed by selectively irradiating the electron beam 23 having an accelerating voltage of 30 kV with an irradiation amount of ²⁰ μC / cm ² in the electron beam drawing apparatus. Then, the negative resist 22 and the silicon substrate 21 after the electron beam irradiation are immersed in a 2.38% tetramethylammonium hydroxide aqueous solution at room temperature for 30 seconds. As a result, as shown in FIG.
An opening 25 is formed in which the unirradiated portion is selectively removed. After that, monovalent phosphorus ions 26 accelerated at an acceleration voltage of 60 kV are implanted with an implantation amount of 5 × 10 ¹² / cm ² .

Subsequent to this, the negative resist 27 is again used.
To a thickness of 3.0 μm by a known spin coating method. As a result, the opening 25 is covered with the negative resist 27 as shown in FIG. Then, the surface of the negative resist 27 is removed by leaving it in a known oxygen plasma. As a result, as shown in FIG. 3D, the surface of the negative resist 22 applied first is exposed, and the negative resist 27 applied later can coexist.

Next, this is placed in a container containing a hot plate heated to 100 ° C. and capable of flowing a tetramethyldisilazane gas. After placing on a hot plate, allow tetramethyldisilazane gas to flow into the container for 5 minutes. As a result, tetramethyldisilazane molecules are diffused on the surface of the negative resist 27 as shown in FIG.
The surface modification layer 28 is formed. The reason why the tetramethyldisilazane molecules do not diffuse to the surface of the negative resist 22 is that the resist molecules are dense and the tetramethyldisilazane molecules cannot enter because this portion is irradiated with the electron beam 23. is there.

Then, these are installed in a known oxygen plasma reactive ion etching apparatus to etch the resist. Here, in the surface modification layer 28, silicon dioxide (S) having a large resistance to oxygen reactive ion etching is used.
An iO ₂ ) layer is formed. Therefore, etching does not proceed in the portion where the surface modification layer 28 is formed. On the other hand, in the portion of the negative resist 22 where the surface modification layer 28 is not formed, the etching proceeds, so that the resist is removed. As a result, as shown in FIG. 3F, the opening 25 initially formed remains, and an inverted resist pattern composed of the negative resist 27 having the surface modification layer 28 is formed. Then, after this, the acceleration voltage 6
BF ₂ ion 29 accelerated at 0 kV is implanted at a dose of 5
Drive at × 10 ¹² / cm ² . Next, the surface modification layer 28 and the negative resist 27 are removed by a known fluorine-based plasma and oxygen plasma treatment, heat treatment is performed at 1100 ° C., and the implanted ions are thermally diffused. Can be formed.

Although tetramethyldisilazane has been described in this description, the present invention is not limited to this, and the same effect can be obtained with a substance generally called a silane coupling agent such as hexamethyldisilazane. Although the case where a gas is used is described here, the same effect can be obtained by more simply immersing the resist and the substrate after the energy ray irradiation in the liquid of the silane coupling agent.

As described above, it is possible to selectively irradiate energy rays at one time when forming resist patterns which are inverted from each other. Here, the case where the electron beam is used as the energy ray has been described, but the invention is not limited to this, and electromagnetic waves such as visible light, ultraviolet rays, far ultraviolet rays, X-rays and gamma rays,
A particle beam such as an ion beam may be used. The resist used may be a positive type resist. The characteristics and types of the resist applied first and the resist applied subsequently do not necessarily have to be the same, and can be selected according to the resist. By the above method, the number of steps can be reduced and the degree of integration can be improved, and an expensive electron beam drawing apparatus or exposure apparatus can be used more efficiently, so that productivity is improved.

(Embodiment 4) In the above embodiment, the case where the resist is formed on the substrate by the known spin coating method has been described. However, the forming method is not limited to this, and a resist film may be formed on the substrate by a known vapor deposition method, chemical vapor deposition method, or Langmuir-Blodgett method.

(Embodiment 5) In the above embodiment, it is described that the formed resist pattern is applied to ion implantation. The resist pattern described above can also be used in other steps. For example, it can be used when etching a base substrate or depositing a thin film performed by a known lift-off method, and is generally applicable when a resist pattern is used in a semiconductor forming process.

[0046]

According to the present invention, selective energy beam irradiation can be performed only once in forming resist patterns which are mutually inverted, so that the number of steps can be reduced and an expensive electron beam drawing apparatus or exposure can be performed. Since the device can be used efficiently and the alignment process is unnecessary, the processing time is shortened and the degree of integration is improved.

[Brief description of drawings]

FIG. 1 is an explanatory view of the present invention by forming resists having different characteristics in an overlapping manner.

FIG. 2 is an explanatory diagram of the present invention due to a change in resist due to ion irradiation.

FIG. 3 is an illustration of the present invention by introducing a surface modification layer.

FIG. 4 is a sectional view of a CMOS structure.

FIG. 5 is an explanatory diagram of ion implantation using a resist inversion pattern.

FIG. 6 is an explanatory diagram of a pattern forming method using a resist.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Positive resist, 13, 1
8 ... Electron beam, 14 ... Latent image, 15 ... Aperture, 16 ... Phosphorus ion, 17 ... Negative resist, 19 ... BF ₂ ion.

Claims (5)

[Claims] 1. When forming a first resist pattern on a semiconductor substrate and then forming a second resist pattern having an inverted shape of the first resist pattern, a selective energy beam for pattern formation is formed. A pattern forming method, wherein the irradiation is performed only when the first resist pattern is formed. 2. The first resist pattern according to claim 1, wherein upon forming the second resist pattern, a resist having a different sensitivity to energy rays from the resist used at the time of forming the first resist pattern is used. A pattern forming method to be formed on. 3. The pattern forming method according to claim 1, wherein in forming the second resist pattern, a region having resistance to plasma is introduced on the surface of the resist. 4. The method according to claim 1, 2 or 3, wherein the first resist pattern is formed on the semiconductor substrate, and then the second resist pattern having an inverted shape of the first resist pattern is formed. A pattern forming method in which a process for alignment is not performed at the time of irradiating an energy ray when forming the second resist pattern. 5. A method of manufacturing a semiconductor element, which comprises forming a semiconductor element using the resist pattern formed by the method according to any one of claims 1 to 4.