JPH06326973A - Muse decoder - Google Patents

Abstract

PURPOSE:To prevent the breaking of a reproduced picture even in the case that the subsample phase or the motion vector gets erroneous during transmission by inter-field interpolation and cannot be corrected. CONSTITUTION:A preceding field signal is subjected to rate conversion by a subsampling circuit 91 and is subjected to inter-line interpolation by an 1H memory 93 and an adder 94 and is subjected to horizontal vector correction by a vector correction circuit 95 and is inputted to an inter-field interpolation part 96. A present field signal is subjected to rate conversion by a subsampling circuit 92 and is inputted to the inter-field interpolation part 96. Every sample is selected in the inter-field interpolation part 96 to obtain the field interpolation output. An arithmetic circuit 101 discriminates normalcy or abnormality based on a transmitted horizontal motion vector signal by relations between the calculation result of the motion vector in a field and the polarity obtained by monitoring inter-field subsample phase signals S5 and S5' and corrects the calculation result to output it as a signal S6' and gives it to the vector correction circuit 95.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE decoder for demodulating a band-compressed high-definition television signal into a broadband high-definition television signal, and more particularly to controlling a motion vector correction circuit of an inter-field interpolation circuit. It is an improved means.

[0002]

2. Description of the Related Art As a method of band-compressing a broadband high-definition television signal to a practical level for transmission, MUSE (Multiple Sub-Nyquist Sampling Encoding) is applied to the original high-definition television signal to make a sub-sample that makes a cycle of four fields. )
System ("New transmission system for high-definition television-MUSE
-", NHK STRL Monthly Report, Ninomiya, 27, No. 7, 1984
Years). As an example of a decoder for demodulating the band-compressed high-definition television signal (hereinafter referred to as MUSE signal) to the original broadband high-definition television signal, Japanese Patent Application No.
There is 90865 "High Definition Television Receiver". This technique is intended to reduce the field memory by inter-field interpolation, and its configuration is shown in FIG.

In FIG. 2, a MUSE signal (hereinafter referred to as signal S
1) is supplied to the input terminal 1 and introduced into the inter-frame inserting section 6. The MUSE signal has a sampling rate of 16.2 MHz. The inter-frame interpolating section 6 is M
The input switching circuit 2 into which the USE signal is introduced, the first field memory 4 to which the output signal of the input switching circuit 2 (hereinafter referred to as signal S2) is supplied, and the output signal of the first field memory 4 (hereinafter referred to as A second field memory 5 to which a signal S3) is supplied. The output signal of the second field memory 5 (hereinafter referred to as signal S4) is fed back to the input switching circuit 2.

In response to the control signal S8 supplied from the terminal 3, the input switching circuit 2 receives the signal S1 from the input terminal 1.
Then, the signal S4 is selectively switched in pixel units. By this operation, the signal S3 is a signal in which the signal one field before the signal S1 and the signal three fields before are interpolated between frames. The signal S4 is a signal in which the signal two fields before and the signal four fields before the signal S1 are interpolated between frames. Therefore, the signal S2 directly output from the input switching circuit 2 is a signal in which the MUSE signal (current field) and the signal two fields before are interpolated between frames. This signal S2 has a sampling rate of 3
It is 2.4 MHz.

The signal S2 is input to the first prefilter 7A. With this pre-filter 7A, 0-12 MHz
Frequency components up to are extracted. The output signal of the first prefilter 7A is input to the first sampling frequency conversion circuit 8A (hereinafter referred to as the first D / D conversion circuit 8A), and the sampling rate is converted to 48.6 MHz. The output signal of the first D / D conversion circuit 8A (hereinafter referred to as signal S8) is supplied to one input terminal of the inter-field interpolation circuit 9 as a signal of the current field.

The signal S2 output from the input switching circuit 2
Is also input to the signal sampling circuit 12. The signal sampling circuit 12 extracts only the data of the current field (the signal S1 at the input terminal, the 16.2 MHz rate) from the signal S2 based on the timing signal S11 (sub-sampling signal) supplied from the terminal 13. Signal sampling circuit 12
The output signal of is input to the field interpolation circuit 14. The field interpolation circuit 14 derives a signal subjected to field interpolation processing from the signal of the current field. The signal interpolated in the field is supplied to the third sampling frequency conversion circuit 15 (hereinafter referred to as the third D / D conversion circuit 15).
, And converted to a rate of 48.6 MHz. The converted signal is supplied to the other input terminal of the mixing circuit 18.

The above signal S2 is also supplied to the motion detection circuit 16. The motion detection circuit 16 detects a motion image and outputs a detection signal to the fourth sampling frequency conversion circuit 17
(Hereinafter referred to as the fourth D / D conversion circuit 17).
The fourth D / D conversion circuit 17 converts the motion detection signal into 48.6.
It is converted to a rate of MHz and supplied to the mixing ratio control terminal of the mixing circuit 18.

The signal S3 is the first pre-filter 7A.
It is input to the second prefilter 7B that performs the same operation as. The output signal of the second pre-filter 7B is supplied to the first sampling frequency conversion circuit 8B (hereinafter referred to as the second D / D conversion circuit 8B) and converted into the rate of 48.6 MHz. The second D / D conversion circuit 8B uses the first D / D
It has the same configuration as the D conversion circuit 8A and performs the same operation.
The output signal of the second D / D conversion circuit 8B (hereinafter referred to as signal S7) is supplied to the other input terminal of the inter-field interpolation circuit 9 as a signal one field before.

The inter-field interpolation circuit 9 has an input terminal 10
The signal S7 (previous field signal) and the signal S8 (current field signal) are subsampled by the inter-field sub-sampling phase signal (hereinafter referred to as signal S5) input from The horizontal motion vector signal (hereinafter referred to as signal S6)
Inter-field interpolation output is obtained while performing horizontal motion compensation. Output signal of inter-field interpolation circuit 9 (hereinafter referred to as signal S9
Is described below) is supplied to one input terminal of the mixing circuit 18.

As a result, the output signal S9 from the inter-field interpolation circuit 9 and the output signal S10 from the third D / D conversion circuit 15 are output from the mixing circuit 18 in a mixing ratio according to the motion detection signal. It is controlled, mixed, and output. The output signal S12 of the mixing circuit 18 is output to the output terminal 19.

The operation of the inter-field interpolation circuit 9 described above will be further described. FIG. 3 specifically shows an example of the inter-field interpolation circuit 9. Current field signal S8
Is a first sub-sampling circuit 92 (hereinafter, S / S circuit 92
Will be supplied). The first S / S circuit 92 extracts the signal S8 for each sample by the inter-field sub-sampling phase signal (signal S5: inter-field sub-sampling phase signal for the current field) input from the input terminal 10 and sampling rate 24 Convert to 3MHz. The output signal (S8 ′) of the first S / S circuit 92 is supplied to one input terminal of the inter-field interpolation unit 96.

The signal S5 input from the input terminal 10
Is a field delay circuit 97 and an inter-field interpolation unit 96.
It is also supplied to the control terminal of. The signal S7 in the previous field is supplied to the second sub-sampling circuit 91 (hereinafter referred to as the second S / S circuit 91). The second S / S circuit 91 uses the signal S5 ′ (inter-field sub-sampling phase signal for the previous field) obtained by delaying the signal S5 by one field by the field delay circuit 97 to generate the first S / S signal.
Similar to the circuit 92, the signal S7 is extracted for each sample and the sampling rate is converted to 24.3 MHz. The output signal S7 ′ of the second S / S circuit 91 is supplied to the 1H memory 93 and the adder 94 having a delay amount of one horizontal period.
The output signal of the 1H memory 93 is also input to the adder 94. Therefore, the output signal S7 ″ obtained by adding the upper and lower lines is obtained from the adder 94, and this signal S7 ″ is input to the vector correction circuit 95.

The horizontal motion vector signal S is applied to the input terminal 11.
6 is supplied and is introduced into the arithmetic circuit 98. The arithmetic circuit 98 calculates, from the value of the signal S6 (the transmitted horizontal motion vector value is the value of the motion vector between frames),
Calculate the value of the horizontal motion vector between fields. The horizontal motion vector signal S6 ′ obtained by this calculation is
It is supplied to the control terminal of the vector correction circuit 96.

The vector correction circuit 96 performs horizontal motion correction on the signal S7 '' in clock units of 48.6 MHz based on the signal S6 '. The output signal S7 ′ ″ from the vector correction circuit 95 is supplied to the other input terminal of the inter-field interpolation unit 96.

The inter-field interpolating section 96 has an input terminal 10
Signal S7 '''(previous field signal) and signal S8' (current field signal) by the signal S5 supplied from
And are selectively switched for each sample, and interpolation processing is performed.
The output signal S9 from the inter-field interpolation unit 96 is supplied to the mixing circuit 18. At this time, the signal S9 has a sampling rate of 48.6 MHz.

[0016]

The outline of inter-field interpolation and vector correction in the MUSE decoder is as described above. However, when performing motion vector correction in a system that performs subsampling such as the MUSE method, the relationship between the subsample phase (signal S5) and the motion vector (signal S6) is fixed, and the two are completely independent. is not. Therefore, if either of the two cannot be corrected or corrected during transmission, the relationship between the two is broken and the decoded image is broken.

Therefore, according to the present invention, in the inter-field interpolation of the decoder of the MUSE signal, even if the sub-sample phase (signal S5) or the motion vector (signal S6) is erroneous during transmission and cannot be corrected, the reproduced image is reproduced. It is an object of the present invention to provide a MUSE decoder that does not break down.

[0018]

According to the present invention, in the process of calculating the value of the horizontal motion vector between fields from the transmitted horizontal motion vector signal in the inter-field interpolation unit, the inter-field sub-sampling phase is newly added. Is also added as a determination element, and means is provided for generating a final motion vector correction signal.

[0019]

By the above means, even if the sub-sample phase signal or the motion vector phase is erroneous during transmission and cannot be corrected, the deterioration of the image quality can be suppressed to the minimum.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The overall structure of the decoder is as shown in FIG. 2, of which the structure of the inter-field interpolation circuit is improved. Therefore, the inter-field interpolation circuit 100 is shown in FIG. The inter-field interpolation circuit 100 shown in FIG. 1 is different from the circuit shown in FIG. 3 in the arithmetic circuit 101. The other blocks are the same as those in the circuit of FIG. 3 and are therefore given the same reference numerals as in FIG. Next, a specific description will be given.

From the input terminal 10, a signal S5 (current inter-field sub-sampling phase signal) is introduced, and this signal S5 is supplied to the first sub-sampling (S / S) circuit 92 and at the same time for one field. Is supplied to the field delay circuit 97 having the delay amount of. The signal S5 ′ output from the field delay circuit 97 is supplied to the second sub-sample (S / S) circuit 91.

The first S / S circuit 92 outputs the current field signal S8 (which is output from the D / D circuit 8A of FIG. 3).
Is subsampled, that is, extracted for each sample and converted to a sampling rate of 24.3 MHz. First S /
The output signal (S8 ′) of the S circuit 92 is supplied to one input terminal of the inter-field interpolation unit 96.

Further, the second S / S circuit 91 controls the sampling phase by the signal S5 ', extracts the signal S7 of the previous field for each sample, and converts the sampling rate into 24.3 MHz. Second S / S circuit 9
The output signal S7 ′ of 1 is 1H having a delay amount of 1 horizontal period.
It is supplied to the memory 93 and the adder 94. The output signal of the 1H memory 93 is also input to the adder 94. Therefore, the output signal S obtained by adding the upper and lower lines is output from the adder 94.
7 ″ is obtained, and this signal S7 ″ is obtained by the vector correction circuit 9
Input to 5. The vector correction circuit 95 corrects the horizontal movement of the signal in the previous field. Therefore, the control terminal has a horizontal motion correction signal S6 'in field units.
Is given from the arithmetic circuit 101. The output signal S7 ″ of the horizontal vector correction circuit 95 is the inter-field interpolation unit 9
6 is supplied to the other input terminal. The inter-field interpolation unit 96 receives the signal S7 ′ ″ (the signal of the previous field) and the signal S8 ′ according to the signal S5 supplied from the input terminal 10.
And (current field signal) are selectively switched for each sample, and interpolation processing is performed. The output signal S9 from the inter-field interpolation unit 96 is supplied to the mixing circuit 18. At this time, the signal S9 has a sampling rate of 48.6 MHz.
Has become.

Here, the arithmetic circuit 101 has an input terminal 1
The horizontal motion vector signal S6 is input from 1. The horizontal motion vector signal S6 indicates an image motion between frames, and is a signal transmitted from the transmission side as control information of the MUSE signal. The arithmetic circuit 101 first calculates the value of the horizontal motion vector between fields from the input signal S6 as in the conventional case. Then, the calculated horizontal motion vector value between fields and the signal S5 and the signal S5
The final output signal S6 'is determined while monitoring'. That is, (a) the polarities of the signal S5 and the signal S5 'are different, and the calculated horizontal motion vector values between fields have a predetermined relationship (the calculation result is an even number). (B) the signal S5 and the signal S5' Have the same polarity and the calculated horizontal motion vector values between fields have a predetermined relationship (the calculation result is an odd number) In the cases (a) and (b) above, the calculation result is regarded as a normal state. The signal S6 'is output.

(C) When the polarities of the signals S5 and S5 'are different and the calculated result of the value of the horizontal motion vector between the calculated fields is odd (d) The polarities of the signals S5 and S5' are the same. Yes, when the calculated result of the value of the horizontal motion vector between the calculated fields is an even number In the above cases (c) and (d), the calculation result is corrected as an abnormal state (a relationship that maintains the relationship between the two). Corrected to
The corrected signal S6 'is output. For example, the signal S5 '
When the signal S5 'is "1", the calculation result is corrected in the direction in which the calculation result becomes smaller.

As a result, even if the sub-sampled phase signal or the motion vector phase is erroneous during transmission and cannot be corrected, the deterioration of the image quality can be suppressed. In the above-described embodiment, the inter-field interpolation circuit 100 uses the inter-field sub-sampled phase signals S5 and S5 'and the horizontal motion vector signal S6 to perform the calculation. It does not depart from the scope of the present invention even if the signal reproduction processing section performs the same calculation and supplies the result to the inter-field interpolation circuit.

[0027]

As described above, according to the present invention,
In inter-field interpolation of MUSE signal decoder,
Even if the sub-sampling phase (signal S5) or the motion vector (signal S6) is erroneous during transmission and cannot be corrected, the reproduced image is not broken.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an overall configuration of a MUSE decoder.

FIG. 3 is a diagram showing a conventional inter-field interpolation circuit.

[Explanation of symbols]

91, 92 ... Sub-sample circuit (S / S circuit), 93 ...
1H memory, 94 ... Adder, 95 ... Vector correction circuit,
96 ... Interfield interpolating section, 97 ... Field delay circuit, 100 ... Interfield interpolating circuit, 101 ... Arithmetic circuit.

Claims (1)

[Claims] 1. A subfield of a signal of a previous field is subjected to horizontal image motion correction by a vector correction circuit, and a vector-corrected first subsample signal and a second subsignal of a current field signal are subsampled. In the inter-field interpolation circuit that performs inter-field interpolation processing according to the inter-field sub-sampled phase signal by using the sub-sampled signal of The horizontal motion vector between fields is calculated from the current horizontal motion vector, and the value of this horizontal motion vector, the polarity of the current interfield sub-sample phase that has been transmitted, and the one field before The relationship between the field and the polarity of the sub-sampling phase has a predetermined relationship, and If there is a predetermined relationship, the value of the calculated horizontal motion vector is given to the control terminal of the vector correction circuit, and if there is no predetermined relationship, the calculated horizontal motion vector An MU characterized by being provided with means for giving a corrected value
SE decoder.