JPH06303580A - High-definition/standard television circuit - Google Patents

Abstract

PURPOSE:To reduce the cost of a high-definition/standard TV receiver by sharing a delay circuit, a filter circuit and an arithmetic circuit and performing a moving picture processing. CONSTITUTION:MUSE signals and NTSC signals are selected and inputted to a frame memory, a moving picture processing circuit and a still picture processing circuit,' the operating modes of the respective circuits are switched corresponding to the signals and prescribed processings are respectively performed. In this case, in the moving picture processing circuit, delay for one horizontal scanning period is performed in line memories 22-25 at the time of inputting the MUSE signals. Also, the filter circuits 26-30 limit horizontal bands to prescribed values corresponding to a delay amount in a vertical direction, the total sum is obtained in the arithmetic circuit 31 and horizontal/vertical two-dimensional interpolation processing output is obtained. At the time of inputting the NTSC signals, the horizontal bands are respectively limited to the prescribed values corresponding to the delay amount in the vertical direction in the filter circuits 26-30, the total sum is obtained in the arithmetic circuit 31 and luminance signals by a two-dimensional. Y/C separation processing are obtained. By sharing the moving picture processing circuit in such a manner, the cost can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-purpose receiver capable of inputting and displaying both high-definition television signals and standard television signals, and rationalizing the circuits by integrating the processing circuits for both signals. The present invention relates to a high-definition / standard television receiver that achieves cost reduction.

[0002]

2. Description of the Related Art The NTSC system, which is the current standard color television system in Japan, has deterioration such as dot interference, cross color, line flicker, etc. based on the system itself. These deteriorations are caused by the recent S-VHS (registered trademark).
With the widespread use of high-definition video sources such as VTR and laser video discs, and the increase in size of displays, it has become very noticeable. Therefore, there is an increasing demand for higher image quality of television receivers.

Under such a trend, research on a new television system, high definition television (HDTV, High Definition TV) is being conducted in various countries around the world including Japan. In Japan, for example, the HDTV system, which NHK is developing mainly, is using the current N number of scanning lines, with 1125 scanning lines and a signal band of 20 MHz or more.
It has about 5 times the amount of information as the TSC system and realizes very high-definition video (Source: "Ninomiya: MUSE-Hi-Vision transmission system, The Institute of Electronics, Information and Communication Engineers, Corona Publishing Co., Ltd. 21.
February ").

MUSE (Multiple Sub-Ny) was developed for the transmission of this high-definition signal by a broadcasting satellite.
quist Sampling Encoding) method. A signal conversion circuit for converting the MUSE signal into the original high-definition signal and displaying it on the display is called a MUSE decoder.

[0005]

As described above, it has become possible to receive high-definition broadcasting at home, but even after the start of full-scale broadcasting scheduled for H8, the current broadcasting system, NTSC, will be used. The system is expected to continue to be broadcast for some time, and it is considered that the proportion of the NTSC system program in the entire broadcast program is quite large. Therefore, MUSE method and N
A receiver capable of supporting both types of the TSC system is required, but simply having the signal processing circuits for both types will increase the cost of the receiver. further,
Considering that a high image quality means such as a motion adaptive luminance signal / color signal (Y / C) separation is performed for the processing of the NTSC signal, the above cost increase becomes more and more significant.

The object of the present invention is to solve the above problems and to provide MUS
It is an object of the present invention to provide a low-cost, high-definition / standard television receiver by rationalizing a circuit in a receiver capable of supporting both the E system and the NTSC system.

[0007]

In order to achieve the above object, according to the present invention, a moving picture field interpolation processing circuit for motion adaptive decoding processing of a MUSE signal is used, and when a NTSC signal is input, an Y / Y field processing for EDTV processing is performed. It is configured to operate as a C separation circuit.

Specifically, in the present invention, as a means for achieving the above object, the present invention operates for a high definition TV,
A high-definition / standard TV mode selection signal input for notifying whether it operates for standard TV, and a video signal for selectively inputting either a high-definition TV signal or a standard TV signal in response to the mode selection signal. The input terminal and the selectively input video signal are input, delayed by an integer multiple of one horizontal scanning period corresponding to the video signal, and output.
A plurality of delay circuits in which the horizontal scanning period is switched according to the mode selection signal, and one of the selectively input video signal and the plurality of video signals delayed by the delay circuit are respectively input, A plurality of filter circuits that output by limiting the pass band of the video signal, and the characteristics of the pass band are switched according to the mode selection signal,
A plurality of video signals band-limited by the filter circuit are input and a calculation between the plurality of video signals is performed to create and output a moving picture signal of a high definition / standard television circuit. A high-definition / standard television circuit is constituted by an arithmetic circuit which is switched according to the mode selection signal.

[0009]

[Operation] High quality / standard TV mode selection signal is high quality /
It informs whether the standard television circuit operates for high definition TV or for standard TV.

From the video signal input terminal, either a high-definition TV signal or a standard TV signal is selected and input according to the mode selection signal.

The delay circuit receives the video signal selected in response to the mode selection signal, delays it by an integral multiple of one horizontal scanning period corresponding to the video signal, and outputs the delayed signal. That is, when a high-definition TV signal is input, it is delayed by an integral multiple of one horizontal scanning period of the high-definition TV signal, and when a standard TV signal is input, it is delayed by an integral multiple of one horizontal scanning period of the standard TV signal. To work.

The filter circuit inputs one of the video signal and the plurality of video signals delayed by the delay circuit, limits the pass band of the video signal, and outputs it. The characteristics of the pass band operate so as to be switched according to the mode selection signal. That is, when a high-definition TV signal is input, the operation is performed for the purpose of field interpolation and horizontal pass characteristics corresponding to each vertical delay time. When a standard TV signal is input, the operation is performed with the color signal band as the pass band for the purpose of in-field luminance signal / color signal (Y / C) separation processing.

The arithmetic circuit inputs a plurality of video signals band-limited by the filter circuit, performs arithmetic operations on the plurality of video signals, and creates and outputs a moving picture signal. The method of this calculation is switched according to the mode selection signal, and when operating for high-definition TV, the purpose is for field interpolation processing, and when operating for standard TV, it is for the field Y / C separation processing. To work as.

With the above structure, both a high-definition TV signal and a standard TV signal can be received, and both signals can be processed by the same circuit, and a low-cost high-definition / standard television receiver is provided. To be able to realize.

[0015]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. Note that, for convenience of explanation, high-definition television will be described by taking high-definition television and MUSE as examples.
Further, NTSC will be described as an example of the standard television. Further, in this embodiment, the luminance signal is explained.

FIG. 2 shows an example of the configuration of a MUSE / NTSC shared receiver, and the present invention is applied to the moving image processing circuit portion thereof. Further, FIG. 1 shows a specific example of the configuration of the present invention.

In FIG. 2, 1 is an input terminal for MUSE signal, 2 is an input terminal for NTSC signal, 3 is a selection circuit, 4 is a frame memory, 5 is a moving image processing circuit, 6 is a still image processing circuit, and 7 is motion detection. A circuit, 8 is a mixing circuit, 9 is an aspect ratio conversion circuit, 10 is an output terminal to a display, 11 is a MUSE signal discrimination circuit, 12 is a mode selection signal input terminal, and 13 is a control circuit.

The MUSE signal input from the input terminal 1 is supplied to one input of the selection circuit 3, and the NUSE signal from the input terminal 2 is input.
The TSC signal is selected and output. This selection operation is performed according to the control signal from the control circuit 13. The output signal of the selection circuit 3 is input to the frame memory 4, the moving image processing circuit 5, the still image processing circuit 6, and the motion detection circuit 7, respectively.

The frame memory 4 sets the input TV signal to 1
Or 2 frame periods later. At this time, input TV
If the signal is a MUSE signal, the frame period of the MUSE signal is delayed, and if the signal is an NTSC signal, the frame period of the NTSC signal is delayed. Specifically, the control circuit 1
Although not shown in the drawing, it operates in response to the control signal from 3 to change the clock for writing / reading of the frame memory and the time delayed by the frame memory.

The moving picture processing circuit 5 performs signal processing in the field to create a moving picture signal. At this time, MUSE
When a signal is selected, it operates for the purpose of inter-field interpolation processing, and when an NTSC signal is selected, it operates for the purpose of intra-field Y / C separation processing. This operation will be described later with reference to FIG.

In the still picture processing circuit 6, the MUSE signal is subjected to inter-frame and inter-field interpolation processing to create a still picture signal. Similarly, when the NTSC signal is selected, processing between frames is performed to separate the luminance signal and the color signal. At this time, the interpolation processing between frames and between fields may be the same processing as that described in the conventional example. Regarding the Y / C separation between frames, a configuration example thereof is described in Japanese Patent Application Laid-Open No. 62-136191 by the present inventors.

The motion detection circuit 7 detects the motion of the image based on the difference between the signals separated by one or two frame periods. The mixing circuit 8 changes the mixing ratio of the output signals of the moving image processing circuit 5 and the still image processing circuit 6 according to the movement of the image detected by the movement detection circuit 7, and outputs the signal. The motion detection circuit 7 and the mixing circuit 8 are also disclosed by the present inventors in Japanese Patent Laid-Open No. 2-81.
One configuration example is described in Japanese Patent No. 588.

The aspect ratio conversion circuit 9 performs conversion so that the input signal is displayed on the display with the correct roundness, and then supplies the signal to the output terminal 10 to the display. That is, when a signal having an original aspect ratio of 4: 3 is input, a horizontally long image is displayed on a 16: 9 display. Therefore, compression processing is performed in the horizontal direction to correct this. Further, when a signal having an original aspect ratio of 16: 9 is input, the aspect ratio conversion circuit 9 stops its operation. This structure is described in Japanese Patent Application Laid-Open No. 3-218192 by the present inventors.

The MUSE signal discriminating circuit 11 detects a frame pulse or an HD pulse included in the MUSE signal and discriminates whether or not the input signal is the MUSE signal. The control circuit 13 is a control signal for switching the operation of each component of the present embodiment to the MUSE signal or the NTSC signal based on the selection signal from the mode selection signal input terminal and the discrimination result from the MUSE signal discrimination circuit 11. Is output.

Due to the above operation, the MU
Even when the SE signal or the NTSC signal is input, the operation mode is switched to enable signal processing in the same circuit.

Next, referring to FIG. 1, the operation of the moving picture processing circuit 5 to which the present invention is applied will be divided into the case where the TV signal selected according to the control signal and inputted is the MUSE signal and the case of the NTSC signal. explain. In FIG. 1, 21 is an input terminal,
22 to 25 are line memories, 26 to 30 are filter circuits, 31 is an arithmetic circuit, 32 is an output terminal, and 33 is a control signal input terminal. In addition, the same control signal that controls the selection circuit 3 is input from the control signal input terminal 33,
Line memories 22 to 25, filter circuits 26 to 3
0, the operation circuit 31 is switched to the operation for the MUSE signal or the NTSC signal.

(1) At the time of inputting the MUSE signal From the input terminal 21, the MUS selected according to the control signal is input.
The E signal is input. The line memories 22 to 25 each delay the input TV signal by one horizontal scanning period of the MUSE signal. At this time, although not shown in the drawing, a clock for writing / reading the line memory and a control signal for changing the delay time in the line memory are MUSE.
It is switched to the one created based on the signal.

In the MUSE method, it is necessary to perform horizontal and vertical two-dimensional interpolation processing in order to perform decoding processing for moving images. Therefore, the filter circuits 26 to 30 are input to the TV
The horizontal band of the signal is band-limited to a predetermined value corresponding to the amount of delay in the vertical direction and output. The arithmetic circuit 31 inputs the output signals from the filter circuits 26, obtains the sum of these signals, obtains a two-dimensional interpolation processing output, and outputs this to the output terminal 32.

The filter circuits 26 to 30 may have the same configuration, and FIG. 3 shows an example of the configuration.
In FIG. 3, 41 is an input terminal, 42 to 45 are delay elements, 46 to 50 are coefficient circuits, 51 is an adder circuit, 52 is an output terminal, and 53 is a control signal input terminal. Input terminal 4
The signal input from 1 is delayed by a unit delay time by each of the delay elements 42 to 45. This delay element 42 to 4
Although not shown in the drawing, 5 operates by a clock generated based on the MUSE signal. Coefficient circuit 46
To 50 output the outputs of the delay elements 42 to 45, respectively, by multiplying them by a predetermined coefficient. At this time, the coefficient multiplied by the coefficient circuits 46 to 50 is switched by the signal from the control signal input terminal 53, and therefore different characteristics can be set depending on whether the MUSE signal is processed or the NTSC signal is processed. It will be possible. The adder circuit 51 obtains a filter output by obtaining the sum of the outputs of the coefficient circuits 46 and 50, and outputs this to the output terminal 52.

(2) At the time of inputting NTSC signal From the input terminal 21, the NTS selected according to the control signal is input.
The C signal is input. The line memories 22 to 25 each delay the input TV signal by one horizontal scanning period of the NTSC signal. At this time, although not shown in the drawing, a clock for writing / reading the line memory and a control signal for changing the delay time in the line memory are
It is switched to the one created based on the signal.

In the NTSC system, horizontal / vertical two-dimensional filter processing may be performed to perform luminance signal / color signal separation processing for moving images. Therefore, the filter circuits 26 to 30
Outputs the horizontal band of the input TV signal by limiting the band to a predetermined value corresponding to the delay amount in the vertical direction.
The arithmetic circuit 31 inputs the output signals of the filter circuits 26 and obtains the sum of these signals to obtain a luminance signal by the two-dimensional Y / C separation processing, and outputs this to the output terminal 32.

As described above, in this embodiment, the line memory, the filter circuit and the arithmetic circuit can be shared in the signal processing of both the MUSE signal and the NTSC signal, and the cost of the MUSE / NTSC common receiver can be reduced. .

Although the operation of the arithmetic circuit 31 in the previous embodiment is described as the sum of the input signals is calculated regardless of whether the MUSE signal or the NTSC signal is input, the present invention is not limited to this. As the processing for the NTSC signal, the Y / C separation processing may be performed by a logical operation such as magnitude comparison between the input signals, instead of the arithmetic operation for obtaining the sum of the input signals. Regarding the Y / C separation processing by this logical operation, a configuration example is described in JP-A No. 2-1604.

[0034]

As described above, according to the present invention, the high quality T
Regardless of whether a V signal or a standard TV signal is input, a delay circuit, a filter circuit and an arithmetic circuit can be shared when processing the input TV signal for a moving image, so a low-cost high-quality / standard TV receiver Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of a high-definition / standard TV receiver to which the present invention has been applied.

FIG. 3 is a block diagram of a configuration example of a filter circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... MUSE signal input terminal, 2 ... NTSC signal input terminal, 3 ... selection circuit, 4 ... frame memory, 5 ... moving image processing circuit, 6 ... still image processing circuit, 7 ... motion detection circuit, 8 ... mixing circuit, 9 ... Aspect ratio conversion circuit, 10 ... Output terminal to display, 11 ... MUSE signal discrimination circuit, 12 ... Mode selection signal input terminal, 13 ... Control circuit, 22, 23, 24, 25 ... Line memory, 26, 27, 28, 29, 30 ... Filter circuit, 31 ... Arithmetic circuit, 33 ... Control signal input terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hatsuji Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi Media Visual Media Research Institute (72) Daisuke Honda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Video Media Division

Claims (2)

[Claims] 1. A TV that operates as a high-definition TV or a standard TV
High-definition / standard TV mode selection signal input for notifying whether it operates as a video signal, and a video signal input terminal for selectively inputting either a high-definition TV signal or a standard TV signal in response to the mode selection signal. And the selectively input video signal is input, delayed by an integer multiple of one horizontal scanning period corresponding to the video signal, and output, and the one horizontal scanning period corresponds to the mode selection signal. A plurality of delay circuits that can be switched, and one of the selectively input video signal and the plurality of video signals delayed by the delay circuit are respectively input, and the pass band of the video signal is limited and output. , A plurality of filter circuits whose characteristics of the pass band are switched according to the mode selection signal, and a plurality of video signals band-limited by the filter circuit are input, An arithmetic circuit for generating and outputting a moving image signal of a high-definition / standard television circuit by performing an arithmetic operation between a number of video signals, and the arithmetic method can be switched according to the mode selection signal. High-definition / standard television circuit characterized by 2. A high-definition / standard television circuit according to claim 1, wherein said arithmetic circuit is intended for field interpolation processing when operating for high-definition TV in response to said mode selection signal. A high-definition / standard television circuit characterized in that it operates for the purpose of in-field luminance signal / chrominance signal separation processing when it is operated for use.