JPH06326748A - Data communication equipment - Google Patents

Abstract

PURPOSE:To attain efficient data transmission reception by counting the number of times of occurrence of a transmission tentative pause state and controlling a receiver side to be an optimum state depending on the result of count. CONSTITUTION:A clock with a predetermined frequency from a clock generating section 24 is fed to a terminal CK of a communication LSI 12. Moreover, a RAM 26 is a RAM reading/writing reception data or the like under the control of a CPU 11 and made up of a communication buffer and an FDD or the like. The communication buffer is a reception buffer and its capacity is selected so that a free area is in existence by taking the capacity of a sent data file into account. Then the capacity of the communication buffer is controlled variably by the CPU 11 in response to an occurrence rate of a transfer OFF signal indicating a tentative pause signal for data transmission.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a data communication device.

[0002]

SUMMARY OF THE INVENTION The present invention counts the occurrence of a transmission suspension state of transmission data caused by a delay in data processing on the receiving side, and variably controls the capacity of a buffer on the receiving side according to the count result. The data communication device is capable of efficiently transmitting and receiving data communication.

[0003]

2. Description of the Related Art Conventionally, in a data communication device, when starting transmission / reception of data, the receiving side first transmits a start code to the transmitting side, and in response to this, the transmitting side starts transmitting data. There is. During data transmission, the data processing time on the receiving side (processing such as data character conversion, error checking, writing to external storage such as FDD) becomes slower than the data transmission speed, and the buffer on the receiving side has a large capacity. When there is a shortage, the receiving side sends a transfer off signal to the sending side to pause the data transmission, and when the buffer becomes available for data processing thereafter, the receiving side sends a transfer on signal and sends the data. Is designed to start.

[0004]

In this case, the user empirically sets the baud rate of the transmitter / receiver when transmitting / receiving the data. However, when the data processing on the receiving side is slow, the data is transmitted at the high baud rate. The problem that the transfer off signal often occurs even though the data is being transmitted, and as a result, the data transmission takes a longer time than when the data is being transmitted with less transmission pause due to the slow baud rate. was there. An object of the present invention is to enable efficient data transmission / reception by counting the occurrence of a transmission pause state and controlling the receiving side to an optimum state according to the count result.

[0005]

The means of the present invention are as follows. FIG. 1 is a functional block diagram of the present invention. In FIG. 1, reference numeral 1 is a transmitting means including a transmitter and the like, and 2 is a receiving means including a receiver and the like, for performing data communication with the transmitting means 1. A counting unit 3 counts the occurrence of a pause state of data transmission that occurs due to a delay in the processing speed of the receiving unit 2. 4 is this counting means 3
It is a control means for changing the capacity of the buffer for the receiving means 1 according to the counting result of.

[0006]

[Operation] The operation of the means of the present invention is as follows. When the transmitting means 1 is transmitting data to the receiving means 2 that performs data communication with the transmitting means 1, the receiving means 2 causes the transmitting means 1 to operate due to a delay in data processing of the receiving means 2.
When a temporary stop signal for transmission is transmitted to, the signal is counted by the counting means 3. Then, the temporary suspension of data continues until the receiving means 2 transmits a release signal to the transmitting means 1. The count result of the count means 3 is given to the control means 4, and the control means 4 judges the count result and controls the receiving means 2 to change the capacity of the buffer, thereby achieving efficiency at an optimum speed. Data is often sent and received.

[0007]

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS.

Configuration FIG. 2 is a circuit configuration diagram of essential parts of the transmission device and the reception device. In this case, the circuit configuration of the main part is the same in the transmitter and the receiver. Now, assuming that the circuit of FIG. 2 is a transmitting device, the CPU 11 comprises a control program for controlling all operations of the transmitting device, an arithmetic circuit, etc., and supplies respective control signals and data to each circuit in the device.

The communication LSI 12 is under the control of the CPU 11.
Sends data to the receiver and also XOF from the receiver
F signal (transfer OFF signal meaning a pause signal), X
It is a circuit that receives an ON signal (a signal for canceling a pause of data transmission). In this case, the data and signals are transmitted and received between the receiving devices via the interface 13. Then, the communication LSI 12 is supplied with data from the CPU 11 via the data bus 14, and is also supplied with an R / W (read / write) control signal from the CPU 11.

The address decoder 15 is a decoder for decoding address data from the CPU 11, one of its output signals is supplied to the CE terminal of the communication LSI 12 as a chip enable signal, and the other signals are C of the latch 16.
It is supplied to the K terminal as a clock. Data from the CPU 11 is supplied to the latch 16 via the data bus 14. Then, the latch 16 outputs signals A, B, C, and D, each of which becomes a "1" signal in accordance with the content of the supplied data.
Is output.

The signals A, B, C and D are input to the respective one ends of the corresponding AND gates 17, 18, 19 and 20, respectively.
The other ends of the AND gates 17, 18, 19 and 20 are 9600 baud, 4800 baud, 2400 baud and 12 output from a clock generator 24 having a crystal oscillator 25.
A clock with each frequency of 00 baud is input. The output signals of the AND gates 17 and 18 are the OR gate 2
Input to OR gate 23 via 1 and AND gate 1
The outputs of 9 and 20 are supplied to the OR gate 2 via the OR gate 22.
3 and the output clock from the OR gate 23 is given to the terminals TXCK and RXCK of the communication LSI 12 as a transmission clock and a reception clock.

[0012] Operation Next, with reference to the flowchart and time charts of FIG. 4 in FIG. 3, the operation will be described.

First, the operation of the transmitter will be described.
The device is in a waiting state for receiving the start code and the baud rate message at the start of transmission from the receiving device (step S1), and when the start code and the baud rate message are sent from the receiving device, the CPU 1 in the transmitting device
1 outputs the data corresponding to the baud rate message, for example, only the signal A is "1" to the data bus 14 and causes the latch 16 to latch it. Therefore AND gate 17〜
Only the AND gate 17 of 20 is closed, and the 9600 baud clock from the clock generator 24 is passed through the AND gate 17, OR gates 21 and 23 to the communication LSI 1
2 is applied to the terminals TXCK and RXCK (step S
2). The initial setting operation of the communication LSI 12 in step S2 is the same on the receiving device side.

Next, the transmitter starts transmitting data. In this case, the data is transmitted to the receiving device side via the communication LSI 12 and the interface 13. Then, during the transmission, it is judged in step S3 whether or not the data file being transmitted is completed (END OF FILE),
If NO, one character is transmitted (step S4),
The transmission counter (TXCT) of the CPU 11 is incremented (step S5). Then, it is determined whether or not the data transmission for one block of the data file is completed (step S6). Also, until the transmission of one block is completed,
Steps S3 to S6 are repeated to transmit data for each character.

When the data transmission for one block is completed, the process proceeds from step S6 to S7 and the one-block transmission end code E
OB (END OF BLOCK or CR) is transmitted (step S7), and then it is determined whether or not the occurrence rate of the XOFF signal (transfer OFF signal) is equal to or higher than a specified value (step S8). If it is less than the specified value, step S3
Then, the data transmission of the next block is restarted, and if it is the specified value or more, the baud rate is changed and the message is transmitted to the receiving device side (step S9). Then, the process returns to step S2.

In this case, the determination of the generation rate of the XOFF signal in step S8 is performed by the following equation.

[Equation 1] However, XOFFC: Number of XOFF signal receptions XONC: Number of XON signal receptions VC: Transmission speed of one character WOFF: Time between XOFF and XON TXCT: Total number of transmission characters Therefore, the above designation is 50%. When it reaches 50% or more, a message with a baud rate that is slower than the baud rate that has been transmitted until then is transmitted to the receiving device side. For example, in the present example, it was 9600 baud, so a baud rate of 4800 baud is transmitted. Therefore, the CPU 11 applies the data for setting only the signal B to "1" to the latch 16 and causes the AND gate 18 to output the clock of 4800 baud, and simultaneously performs the processing of supplying the transmission LSI 12 to the transmission device and the reception device.

When the data transmission for one file is completed, the process proceeds from step S3 to step S10, and the signal EOF (E
ND OF FILE).

During the processing of steps S3 to S8, if an XOFF signal is transmitted from the receiving device side due to the processing delay of the received data, the transmitting device side receives the signal (step S11), and the CPU 11 in the CPU 11 receives the signal. XOFFC (XO
The FF counter) is incremented (step S1)
2). Then, the system waits for the transmission of the signal XON for canceling the suspension of the data transmission (step S13). Therefore, during this time, the time WOFF between the signals XOFF and XON is set to the CPU.
The counter in 11 counts.

Next, the operation of the receiving device will be described. Before the start of data reception, first, a predetermined baud rate is read from its setting file (step S14), and a baud rate message and a start code are transmitted to the transmitting device. (Step S15). Then, the clock of the baud rate is also started to be supplied to the own communication LSI 12 (step S16). Then, it waits for reception of the transmission data (step S17). Next, it is judged whether or not the baud rate switching message has been received (step S18), and it is initially NO.
Therefore, the process proceeds to step S20, where one character of transmission data is read from the reception buffer and character conversion is performed.
Perform processing such as error checking. Then, the BF set counter for down-counting the capacity of the reception buffer is decremented (step S21), and then it is determined whether or not the count value becomes equal to or less than the effective capacity of the reception buffer and immediately after the transmission of the XOFF signal (step S22). If NO, then the XON signal is transmitted in step S23, while if YES, the process immediately proceeds to step S24, where EOL (end of data transmission for one block) or EOF (data transmission for one file). End)) or not. If YES, step S2
5, the process proceeds to step S26 if NO.

The effective capacity of the reception buffer has an extra capacity of several characters in its effective length. In step S25, the process of writing the received data to the FDD is performed, and in step S26, it is determined whether the reception of one file is completed. If NO, the process returns to step S17, and if YES, the data reception ends.

When it is determined in step S18 that the baud rate switching message has been received, the new baud rate is written in the setting file, and other data is latched in the latch 16 to change the clock supplied to the communication LSI 12 (step S19).

In the data receiving operation, the transmission data for one character is set in the reception buffer (step S2).
7) Also, the BF set counter is incremented (step S28), and then it is determined whether or not the count value is equal to or larger than the effective capacity of the reception buffer (step S28).
29). When NO, the next data receiving operation for one character is started, and when YES, XOFF is performed.
Send a signal to the transmitter to request a pause in data transmission.

[0023]

Second Embodiment Next, a second embodiment will be described with reference to FIGS. In the second embodiment, the baud rate is changed when the XOFF signal is generated more than the specified number of times in the first embodiment, but the capacity of the receiving buffer is changed.

Configuration FIG. 5 shows a circuit configuration diagram of a main part on the receiving device side. The circuit configuration of the main part on the transmitter side is the same as in FIG. And FIG.
2 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 5, the clock generator 24
A clock having a constant frequency from, for example, a 9600 baud clock is supplied to the CK terminal of the communication LSI 12.
The RAM 26 is a RAM to / from which received data and the like are read / written by the CPU 11, and its detailed configuration is shown in FIG.
As shown in FIG. 5, it comprises a communication buffer 26A, an FDD 26B and the like. The communication buffer 26A is the reception buffer, and its capacity is set so that there is an empty area with respect to the capacity of the transmitted data file.
The capacity of the communication buffer 26A is variably controlled by the CPU 11 according to the generation rate of the XOFF signal.

[0026] By operating the above configuration, CPU 11 of the receiving device 11 likewise the transmission apparatus, performing calculations of the equation (1) described in the first embodiment at the time of data reception. If the generation rate of the XOFF signal is equal to or higher than the specified value, the CPU 11 on the receiving device side changes the capacity of the communication buffer 26A according to the generation rate. As a result, the communication buffer 26A having a capacity corresponding to the baud rate at that time is always prepared, and the efficiency of data reception can be improved.

[0027]

As described above, according to the present invention, the occurrence of the transmission suspension state of the transmission data caused by the delay of the data processing on the receiving side is counted, and the receiving side of the receiving side is detected according to the count result. Since it is a data communication device that variably controls the capacity of the buffer, data can be transmitted at the optimum transmission speed, and the receiving side can also receive without wasteful idle state. There is an advantage that communication can be sent and received.

[Brief description of drawings]

FIG. 1 is a functional block diagram of the present invention.

FIG. 2 is a circuit configuration diagram of a main part.

FIG. 3 is a flowchart.

FIG. 4 is a time chart.

FIG. 5 is a circuit configuration diagram of a main part.

FIG. 6 is a specific configuration diagram of a RAM 26.

[Explanation of symbols]

 11 CPU 12 Communication LSI 15 Address Decoder 16 Latch 24 Clock Generator 26A Communication Buffer 26B FDD

Claims (1)

[Claims] 1. A transmitting means, a receiving means for performing data communication with the transmitting means, a counting means for counting the occurrence of a transmission suspension state of transmission data occurring in the receiving means, and the receiving means. A data communication device comprising: a control unit that variably controls the capacity of the buffer according to the count result of the counting unit.