JPH0632562B2 - Control device for three-phase current source power converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a control device for a three-phase current source power converter in which a sine wave AC current is caused to flow to an AC terminal side by pulse width modulation control.

[Conventional technology]

2. Description of the Related Art As a current source inverter for driving an AC electric motor, there is known a current source inverter which supplies a sine wave current as disclosed in Japanese Patent Laid-Open No. 58-89073. This current source inverter has a structure in which a self-extinguishing element is connected by Graetz, a DC reactor is connected to the DC input side, and a smoothing capacitor is connected between each line on the AC output side. This current source power converter obtains a pulse-shaped current waveform with a pulse width distributed in a sinusoidal shape by the high-frequency switching operation of the self-extinguishing element, and at that time, a harmonic component of the current is connected between the output terminals for smoothing. It is absorbed by the capacitor. As a result, the current supplied to the load can have a waveform very close to a sine wave. Therefore, when the AC motor is driven, the torque pulsation of the motor caused by the harmonic component can be reduced, and the efficiency of the motor can be increased.

[Problems to be solved by the invention]

However, when an erroneous arc extinguishing pulse is superimposed on the gate signal due to noise or the like, an overvoltage occurs. In the current source inverter, it is necessary that the one-phase element in the positive arm group and the one-phase element in the negative arm group are always in the conductive state. At all times, the current loop of DC power supply-DC reactor-inverter positive arm-load-inverter negative arm-DC power supply is closed. However, the current loop is opened when a false arcing pulse is applied. Therefore, the circulating loop of energy stored in the DC reactor having a large inductance is lost. At this time, if an overvoltage is applied to the self-extinguishing element of the open-side polarity arm group, and the element is destroyed, there is a problem.

It is an object of the present invention to provide a control device for a three-phase current source inverter that surely prevents overvoltage breakdown of an element due to an erroneous arc extinguishing pulse caused by noise or the like.

[Means for solving problems]

According to the present invention, the distribution signal generating means generates the gate signal of any two phases of the three-phase inverter according to the pattern signal of the gate signal and the distribution signal, and the gate signal of the remaining one phase is the gate signal of any two phases. It is obtained by inversion OR.

[Action]

When an erroneous arc extinguishing pulse is superimposed on a certain phase and the element of that arm becomes non-conducting, the element of the other arm of the same polarity is brought into the conducting state, and the elements of all phases in each arm group of each polarity. Avoid non-conduction.

〔Example〕

 FIG. 1 shows an embodiment of the present invention.

In FIG. 1, the inverter INV is self-turn-off devices _{U P, V P, W P} , U N, V N, constituted by Graetz connecting the _{W N.} A DC reactor 6 for current smoothing and a DC power supply 5 are connected to the DC input terminal of the inverter INV. A load 4 and a smoothing capacitor 3 are connected to the AC output terminal of the inverter INV. Smoothing capacitor 3 absorbs overvoltage generated during switching of self turn-off devices U _P to _W-N. Self-turn-off devices _U P to _W-N is added to the gate signal _T UP _{through T WN} output from the gate control circuit 1 via a gate amplifier 2. The gate circuit control 1 inputs the PWM pattern signal G _P generated by the pattern generation circuit 11 and the distribution signals A to F generated by the distribution signal generation circuit 12 to the distribution synthesis circuit 13 according to the inverter frequency command *, and the distribution synthesis circuit 13 13 to U-phase and V-phase two-phase gate signal T
Obtain _UP , T _VP , T _UN and T _VN . The gate signals T _WP and T _WN of the W phase are the gate signals T _UP and T of the U phase and the V phase, respectively.
_VP , T _UN and T _UV are respectively NOR circuits 141 and 1
It is obtained by inputting into 42. NOR circuit 141,
Reference numeral 142 denotes an inverted logical sum IC, the gate signal T _WP can be the inverted logical sum of the gate signals T _UP and T _VP , and the gate signal T _WN is the gate signals T _UN and T _VN.
Inversion logical sum of can be taken.

FIG. 2 shows a detailed configuration of the distribution / synthesis circuit 13.

In FIG. 2, the distribution / synthesis circuit 13 is an AND circuit AND.
1 to AND10 and OR circuits OR1 to OR4. The pattern signal G _P is a PWM pattern and is repeated with one cycle being 60 degrees, which is the operation period of the inverter INV. Further, the distributed signals A to F have an electrical angle width of 60 degrees and are 6
It is a 0 degree phase difference signal.

Now, the pattern signal G_PAND the distribution signal A
The circuit 1 obtains the signal PTN · A, and the signal G_PInversion of
Signal ▲ AND the logical product of C by AND circuit 2 and signal ▲
▼ C is obtained. Output signal P of both AND circuits 1 and 2
TA / A, ▲ ▼ / C are ORed with the logical sum of distribution signal B
The output signal of the OR circuit 1 is taken by the circuit 1 and the self-extinguishing element U
_PGate signal T_UPAnd Gate signal T_VP, T
_UN, T_VNAlso for pattern signal G_PAnd distribution signal A
It can be made in the same manner by using combinations of ~ F. Next
In addition, the W-phase self-extinguishing element W_PGate signal T added to_WP
Is the gate signal T_UPAnd T_VPInput the NOR circuit 141
Then, it is created by taking the inversion logical sum. Also,
Signal T_WNIs the gate signal T_UNAnd T_VNNOR times
Created by inputting to path 142 and taking the inversion OR
To do.

FIG. 3 shows the gate signal patterns T _{UP to} T in the normal operation.
_WN and inverter INV, PWM control current i _{UI to} i
Shows the relationship between _WI and the output current _i U through i _W flowing through the load 4. The patterns of the gate signals T _{UP to} T _WN are exactly the same and are PWM-controlled in a sinusoidal manner, and the phase difference between them is 60 degrees of the inverter operation cycle. Self-turn-off devices U _P to _W-N becomes conductive when the gate signal is "1" level, the non-conductive state when the "0" level. For example, the PWM control current i _UI has the gate signal T
_The current pattern matches _UP and the gate signal T _UN on the negative side.

Next, FIG. 4 shows a waveform when noise is superimposed on the gate signal T _UP output from the distribution / combining circuit 13 at the time point X in FIG. 3 and an erroneous arc extinguishing pulse is output. When the pulse width of the false arc extinguishing pulse is d, the gate signal T _UP becomes “0” level at the time of X. Self normal In operation, the gate signal T _WP was filed with "0" level at time X, the gate signal is the output of the NOR circuit 141 by superposition of erroneous extinguishing pulse T _WP becomes the period d by "1" level Arc extinguishing element W
_{Make P} conductive. Thus, even if the arc extinguishing erroneous pulse is superimposed, it is possible to keep the element U _P of the positive electrode _arm, V _P, always conducting state one element among W _P.
Similarly, when the erroneous arc extinguishing pulse is superposed on T _VP , the gate signal T _WP is also set to “1” level. Also, be sure conduction 1 element of the gate signals _{T UN,} element by connexion anode the arms to the NOR circuit 142 when Ayamasho firing pulse is superimposed on _{T VN U N, V N,} W N of the negative electrode the arms Can be in a state.

As described above, even if noise is superposed on the output signal of the distribution / synthesis circuit 13 and an erroneous arc extinguishing pulse is generated, one element of the positive arm arm and one element of the negative arm arm must be in the conductive state. Can be kept. Therefore, it becomes possible to prevent the overvoltage breakdown of the element due to the opening of the current loop.

By the way, the superposition of the erroneous arc extinguishing pulse causes a conduction state different from that in the normal operation, which affects the output current waveform. In FIG. 4, when the pulse width d of the erroneous arc extinguishing pulse is short, the PWM control current i _UI has a slit.
It is absorbed by the output end capacitor 3 and has very little effect on the output current. On the contrary, when the pulse width d is long, the output current is distorted, but since the current loop is secured, overvoltage does not occur and the element is destroyed.
Also, if the noise is not mixed in at all times, if it is not continuous, it returns to the normal operation state when the noise is removed, and the output current can be kept in a sine wave again.

Further, according to the present embodiment, by adding the NOR circuits 141 and 142, the gate signals T _WP and T _WN similar to those of other arms which are conventionally required in the distribution / combining circuit 13 are added.
There is also an effect that a logic element for making the circuit becomes unnecessary and the structure of the gate control circuit 1 becomes simpler.

FIG. 5 shows another embodiment of the present invention.

FIG. 5 shows an embodiment in which the present invention is applied to a current source converter.

In FIG. 5, the current source converter CON is constructed by connecting the self-extinguishing elements R _{P to} T _N with the Graz connection. A load 25 is connected to a DC output terminal of the converter CON via a DC reactor 26. The AC input terminal of the converter CON is connected to an AC power supply 24, and a capacitor 23 for absorbing overvoltage is provided between the lines. Each self-extinguishing element R
Gate signals T _RP , T _SP , T _{TP of P to} T _N ,
T _RN , T _SN , and T _TN are created by the gate control circuit 21 according to the DC voltage command _ed * and added via the gate amplifier 22. The gate control circuit 21 includes a pattern / distribution signal generation circuit 211, a distribution / synthesis circuit 212, and a NO.
It is composed of R circuits 213 and 214.

In the embodiment shown in FIG. 5, a DC reactor 26 is connected to the output end in the same manner as the embodiment shown in FIG. 1, and a current loop (AC power supply-
The converter positive electrode arm-DC reactor-load-converter negative electrode arm-AC power supply) includes a DC reactor 26 in a current source configuration. Therefore, the NOR circuits 213 and 214 are connected to the output terminals of the distribution / synthesis circuit 212 so that the current loop is not opened. By this,
When the false arc extinguishing pulse is superimposed on the gate signal turns T _RP , T _SP , T _RN , and T _SN output from the distribution / combining circuit 212, it is possible to prevent the overvoltage breakdown of the element due to the opening of the current loop. Further, there is an effect that the configuration of the distribution / synthesis circuit 212 can be simplified.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the overvoltage breakdown of the element due to the erroneous extinguishing pulse generated due to noise or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a detailed circuit diagram of the distribution / combination circuit shown in FIG. 3, FIG. 3 is a waveform diagram for explaining the operation in the normal operation, FIG. 4 is a waveform diagram for explaining the operation in the abnormal state, and FIG. It is a block diagram. _{U P, V P, W P} ...... inverter positive electrode arm unit self-turn-off _{devices, U N, V N, W} N ...... inverter anode the arms self-turn-off _{device, R P, S P, T} P ...... converter positive The arms self-turn-off _{devices, R N, S N, T} N ...... converter anode the arms self-turn-off _{devices, T UP ~T WN, T RP} ~T
_TN ... Gate signal pattern, T _UP ′ to T _WN ′, T
_{RP 'through T TN'} ...... gate signal, PTN ...... PWM pattern (pulse width control pattern), to F ...... distribution signals, 1,21 ...... control circuit, 2,22 ...... gate amplifier, 11 ...... Pattern generation circuit, 12 ... Distribution signal generation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiko Sasaki 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi Research Institute, Ltd. (72) Toshiaki Kurosawa 4026 Kuji Town, Hitachi City, Ibaraki Corporation, Hitachi Corporation In Hitachi Research Laboratory (72) Inventor Sakai ▲ Yoshi ▼ O 1070 Ige, Katsuta City, Ibaraki Prefecture Hitachi Co., Ltd. Mito Plant (56) Reference JP-A-60-98876 (JP, A)

Claims (1)

[Claims] 1. A three-phase power converter configured by connecting a self-extinguishing element by Graetz connection, a smoothing reactor connected to the DC terminal side of the power converter, and an AC terminal side of the power converter. Smoothing capacitor, pattern generating means for generating a pattern signal of a gate signal to be given to the power converter at a frequency according to a frequency command, and for determining to which arm of the power converter the pattern signal is given. Distribution signal generating means for generating a distribution signal, distribution / combining means for outputting a gate signal of positive two-phase positive and negative arms of the power converter based on the pattern signal and the distribution signal, and positive two-phase positive electrodes First logic means for outputting a gate signal to be applied to the remaining one-phase positive electrode arm of the power converter by inverting logical sum of gate signals to be applied to the arm; The power converter of the remaining three-phase current power converter controller with a second logic means for outputting a gate signal to be supplied to the negative electrode arm of one phase by NOR gate signal applied to the electrode arm.