JPH06325591A - Redundant circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the generation of a delay time by mounting an address comparison circuit on a redundant circuit for detecting whether or not an input address coincides with a redundant address, a fault address, and inputting an address comparison line as an output from the address comparison circuit directly to the whole redundant usage detector through a unilateral two-terminal element. CONSTITUTION:In redundant address comparison circuits 1-1 to 1-N, first impedance not shown in the figure is interposed among an electric wire not shown in the figure and redundant address comparison lines 4-1 to 4-N when an input address AY coincides with a redundant address, second impedance having a value different from the first impedance is interposed when the input address does not agree with the redundant address, and outputs C-1 to C-N are generated in the comparison lines 4-1 to 4-N. In a voltage conversion type whole redundant usage detector 2, the outputs C-1 to C-N from the circuits 1-1 to 1-N are input as the synthetic output CT of unilateral elements C-1 to 6-N and corrected outputs CO, XCO are generated, and the outputs C-1 to C-N from the circuits 1-1 to 1-N are input to spare generating circuits 3-1 to 3-N and outputs SP-1 to SP-N are generated from spare lines 5-1 to 5-N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant circuit of a semiconductor memory, which is effective for a redundant circuit such as a detection circuit for detecting whether an input address matches a redundant address (that is, a defective address). It is about technology.

[0002]

2. Description of the Related Art A redundant circuit of a conventional semiconductor memory will be described with reference to FIGS. FIG. 12 shows a redundant circuit of a conventional semiconductor memory. In FIG.
Reference numerals 11-1 to 11-N are voltage conversion type redundant address comparison circuits which respectively receive the address AY, and outputs C-1 to C-N from the redundant address comparison lines 14-1 to 14-N.
To occur. 12 is N redundant address comparison circuits 11-
An output CO is generated by a voltage conversion type overall redundant use detection circuit which receives the outputs C-1 to C-N of 1 to 11-N as inputs.
Reference numerals 13-1 to 13-N are voltage conversion type spare generation circuits which receive the outputs C-1 to C-N of the N redundant address comparison circuits 11-1 to 11-N, respectively, and which are spare lines 15
Outputs SP-1 to SP-N are generated from -1 to 15-N.

An outline of a conventional redundancy judgment circuit is shown in FIG.
Explain. There are two types of redundancy judgment circuits, one is the input
Address AY (AY₁~ AY_m, XAY₁~ X
AY _m) Is, for example, a fuse ROM (read only memory)
Defective address (redundant address) stored in memory
Redundant address comparison circuit 11-which determines whether or not they match
1 to 11-N. The judgment result is the redundant address ratio.
As a comparison circuit, the dynamic NOR times shown in FIG.
Path (MOS transistor Q_a1~ Q_am, Q_b1~ Q _bm，
Q_p1, Q_q1， Fuse F_a1~ F_am, F_b1~ F_bm,dry
DR₁Etc. The figure shows a redundant array as an example.
The configuration of the dress comparison circuit 11-N is shown)
Therefore, whether the output voltage is logic level high or low is output.
Be done.

The other redundancy judgment circuit is a duplicated circuit as a whole.
There are several redundant address comparison circuits 11-1 to 11-N.
If any one of the addresses AY is a redundant address (defective address
Dress) or none match
It is the entire redundant use detection circuit 12 for determining whether or not it is. So
The result of the determination of FIG.
The dynamic NOR circuit (MOS transistor) shown in FIG.
Star Q_C1~ Q_CN, Q_p2, Q _q2, Driver DR₂Composed of etc.
The output voltage is at a logic level high.
It is output at low.

An outline of the above redundancy judgment operation is shown in FIG.
An explanation will be given using (a). For example, input address A
When Y _n and XAY _n change, the signal ATD which detects the change becomes pulse-like low, and the dynamic N
For example, the potential of the output C-N of the redundant address comparison circuit 11-N which is an OR circuit is changed. Then, the voltage change is input to the overall redundant use detection circuit 12 which is the dynamic NOR circuit in the subsequent stage, and the potential of the output CO is changed similarly. In this case, after the input addresses AY _n and XAY _n change, it takes time T _d until the potential of the output CO changes.
Operation delay occurs. FIG. 14B shows the operation delay time T
FIG. 14B shows the relationship between _d and the number N of nodes of the outputs C- ₁ to C-N. It can be seen from FIG. 14B that the operation delay time T _d increases substantially proportionally as the number N of nodes increases.

Redundant address comparison circuits 11-1 to 11-N
The outputs C-1 to C-N are also input to spare generation circuits 13-1 to 13-N provided in a one-to-one correspondence with each other. The spare generation circuits 13-1 to 13-N basically have the drivers DR ₃ and DR ₄ as shown in FIG.
It consists of a cascade circuit. FIG. 13C shows a circuit of the spare generation circuit 13-N as an example.

The output of the entire redundant use detection circuit 12 is used to generate an inhibit signal or an activation signal for the normal line. FIG. 15 shows a redundant address comparison circuit 11 (redundancy address comparison circuit 11-1) in a dynamic random access memory (hereinafter referred to as DRAM) chip.
11-N), a spare generation circuit 13 (represents a combination of spare generation circuits 13-1 to 13-N), and a general redundant use detection circuit 12 are generally arranged in a memory area. Memory array 30 in which cells are arranged
3 shows an outline of a signal path indicating how to finally access the memory sub array 31 in FIG. SP
Indicates the output of the spare generation circuit 13, and BLK indicates the memory array block selection signal for controlling the transfer gate.

With the increase in memory capacity, for example, in the case of 64 Mbit DRAM, the length of the signal path is 12 mm.
, The output SP of the spare generation circuit 13 arranged in the center of the chip is transmitted by a 12 mm signal line and reaches the memory sub array 31, and is selected by the transfer gate control by the memory array block selection signal BLK.
Finally, the target memory cell can be accessed.

However, during this period, the output SP of the spare generation circuit 13 is greatly delayed due to the wiring delay. As a result, the generation of the spare line is delayed, and the access to the spare cell is delayed.
This situation also applies to the output CO of the entire redundant use detection circuit 12. By the way, if the generation of the inhibit signal or the activation signal of the normal line is delayed, the following problems occur. If the prohibit signal is delayed, multiple selection of the normal line and the spare line, which is not prohibited temporarily, occurs and the reading speed is slowed down. On the other hand, if the activation signal is delayed, there is a problem in that the reading of the memory cell is delayed by that much, which is an obstacle to speeding up the reading.

[0010]

Conventionally, a fuse ROM has been used.
Since the redundant NOR comparison as shown in FIG. 13A is performed to determine whether the defective address (redundant address) stored in the (read-only memory) matches or does not match, the dynamic NOR circuit shown in FIG. Due to the increase in the stray capacitance of the node of the output CN due to the increase in the fuse ROM accompanying the increase in the capacity, the operation of the dynamic NOR circuit becomes slow as shown in FIG. 14B. That is, there is a problem that the charging time of the node of the output _CN by the P-type MOS transistor Q _{p1 in} FIG. The same applies to each node of the other outputs C-1 to C- (N-1).

The output voltage of the dynamic NOR circuit which is the redundant address comparison circuit 11 is input to another dynamic NOR circuit which is the overall redundancy use detection circuit 12 as shown in FIG. If the generation of the output voltage of the circuit 11 is delayed, naturally the generation of the output CO of the overall redundant use detection circuit 12 in the subsequent stage is also delayed. Further, the operation of the dynamic NOR circuit in the subsequent stage has the same cause as the delay of the dynamic NOR circuit in the previous stage with the increase in the capacity of the memory.
_Since the charging time of the node of the output C-N due to _p2 becomes long and a delay occurs, the generation of the inhibit signal of the normal line is delayed, and the multiple selection of the normal line and the spare line which is not temporarily inhibited occurs and the read There is the problem of slowing down.

An object of the present invention is to provide a redundant circuit of a semiconductor memory capable of achieving large capacity and high speed.

[0013]

In the redundant circuit of the semiconductor memory of the present invention, the first impedance is interposed between the power supply and the redundant address comparison line when the input address matches the redundant address. At the same time, when the input address does not match the redundant address, a plurality of redundant address comparison circuits are provided in which a second impedance having a value different from the first impedance is interposed between the power supply and the redundant address comparison line. A plurality of redundant address comparison lines of the plurality of redundant address comparison circuits are connected to the input terminals of the plurality of spare generation circuits, respectively, and a plurality of redundant address comparison lines of the plurality of redundant address comparison circuits pass current only in one direction. Connect to the cathode terminals of the unidirectional two-terminal element respectively, and connect the anode terminals of multiple unidirectional two-terminal elements in common, Connecting the anode terminal of the unidirectional two-terminal element to an input terminal of the entire redundant use detection circuit.

The above spare generating circuit is composed of an impedance input differential amplifier, one input terminal of the differential amplifier is connected to the redundant address comparison line, and the other input terminal of the differential amplifier has the first impedance and the first impedance. It is connected to a reference line connected to the power supply via a third impedance having an intermediate value between the impedance values of 2. The redundant use detection circuit is composed of an impedance input differential amplifier, one input terminal of the differential amplifier is connected to the anode terminal of the unidirectional two-terminal element, and the other input terminal of the differential amplifier is the first input terminal. It is connected to a reference line connected to a power source through a third impedance having an intermediate value between the impedance and the value of the second impedance.

[0015]

According to the structure of the present invention, when the input address matches the redundant address, the first impedance is inserted between the power supply and the redundant address comparison line, and the input address does not match the redundant address. Then, the second impedance is inserted between the power supply and the redundant address comparison line, and the difference in the impedance of the address comparison line is input to the spare generation circuit. In the spare generation circuit, the impedance input differential amplifier is used to judge the difference in the impedance of the address comparison line, so that the input address matches the defective address stored in the fuse ROM (read only memory), that is, the redundant address. It is determined whether or not they match. Further, almost simultaneously with the above determination operation, the redundant address comparison line is input to the overall redundant use detection circuit via the unidirectional two-terminal element that allows a current to flow only in one direction, thereby inputting the entire redundant use detection circuit. The impedance difference of the address comparison line is also transmitted to the terminal, and at the same time as the above determination operation, it is determined whether or not redundant use is performed using the impedance input differential amplifier.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the redundancy circuit of the first semiconductor memory of the present invention will be described below with reference to FIGS. 1 is a circuit diagram showing an outline of a redundant circuit of an impedance detection type semiconductor memory according to a first embodiment of the present invention. 2 (a) is a circuit diagram of the latter part of the redundant address comparison circuit shown in FIG. 1 (a part that switches impedances when the input address and the redundant address match / mismatch), and FIG. 2 (b) shows the redundant address comparison circuit shown in FIG. FIG. 3 is a circuit diagram of a front part (a part for comparing an input address and a redundant address), and m circuits of the front part are connected to the circuit of the rear part of FIG. 2A. Figure 3 (a)
3 is a circuit diagram showing a connection state between the address comparison lines 4-1 to 4-N in FIG. 1, that is, the nodes of the outputs C-1 to C-N and the overall redundant use detection circuit 2, and FIG. 3 is a circuit diagram of an impedance input differential amplifier used as the overall redundant use detection circuit 2 in FIG. FIG. 4 is an operation waveform diagram of the redundant circuit of the semiconductor memory of FIG.

As shown in FIG. 1, the redundancy circuit of this semiconductor memory is provided with a plurality of impedance conversion type redundancy address comparison circuits 1-1 to 1-N having an address AY as an input, and a plurality of redundancy address comparison circuits. The redundant address comparison lines 4-1 to 4-N of 1-1 to 1-N are respectively connected to the input terminals of the spare generation circuits 3-1 to 3-N, and the redundant address comparison circuits 1-1 to 1-1 are connected. The redundant address comparison lines 4-1 to 4-N of 1-N are respectively connected to the cathode terminals of the unidirectional two-terminal elements 6-1 to 6-N which allow a current to flow only in one direction, and a plurality of single-directional two-terminal elements 6-1 to 6-N are connected. Directional two-terminal elements 6-1 to 6-
The anode terminals of N are commonly connected, and the anode terminals of the plurality of unidirectional two-terminal elements 6-1 to 6-N are connected to the input terminals of the overall redundant use detection circuit 2.

The redundant address comparison circuits 1-1 to 1-N are
When the input address AY matches the redundant address, a power supply (not shown) and redundant address comparison lines 4-1 to 4-
A first impedance (not shown) is interposed between the power source and the redundant address comparison line 4-1 when the input address does not match the redundant address.
To 4-N, a second impedance (not shown) having a value different from the first impedance is interposed, and the output C is output from the redundant address comparison lines 4-1 to 4-N. -1 to C-N are generated.

The voltage conversion type overall redundant use detection circuit 2 is
Outputs C- of N redundant address comparison circuits 1-1 to 1-N
1 to CN are input with the combined output CT of the unidirectional two-terminal elements 6-1 to 6-N, and complementary outputs CO and XCO are generated. The voltage conversion type spare generation circuits 3-1 to 3-N are
Outputs C-1 of the redundant address comparison circuits 1-1 to 1-N
.. -C-N are input respectively, and spare lines 5-1 to 5-N generate outputs SP-1 to SP-N.

The redundant address comparison circuits 1-1 to 1-N have the impedance conversion function as described above and have the same configuration. For example, the redundant address comparison circuit 1-N is
The latter part (the part that switches the impedance when the input address and the redundant address match / mismatch) has the configuration shown in FIG. 2A, and the former part (the part that compares the input address and the redundant address) is the one shown in FIG. ) Is a configuration as shown in FIG.

That is, in the latter part of the redundant address comparison circuit 1-N, as shown in FIG. 2A, the node of the output C-N is connected to the power supply 20 (eg ground power supply) via the MOS transistor Q _np. In addition, it is connected to the power supply 20 via the MOS transistors Q _{n1 to} Q _nm connected in series. The gate signal is given to the MOS transistor Q _np so that it is always in the conductive state, and the impedance in the conductive state is R _ss . In the m MOS transistors Q _{n1 to} Q _nm connected in series, the series combined impedance is R _st when the gate signals AYI _{1 to} AYI _m are all high and are all in the conductive state.

Further, as shown in FIG. 2B, switches S ₁₁ and S ₁₂ are provided in the preceding stage of the redundant address comparison circuit 1-N, for example, the portion of the input address AY for the input address AY _m . , Inverters IN ₁₁ , IN ₁₂ ,
It is composed of a MOS transistor Q _g1 , a capacitor C ₁ and a fuse F _c1 , and when the high and low states of the input addresses AY _m and XAY _m match the intermittent state of the fuse F _c1 , the output AYI _m becomes high and they do not match. At that time, it becomes low. Such a circuit is
When Y is m bits up AY ₁ ~AY _m would m number exists.

In the configuration described above, the node of the output C-N of the redundant address comparison circuit 1-N, that is, the address comparison line 4-N is connected to the power supply 20 when the input address AY matches the redundant address. Are connected with a relatively low first impedance, and when the input address does not match the redundant address, the power source 20 is connected with a relatively high second impedance. In this case, the potential of the node of the output C-N is fixed to the ground potential.

As a method of generating the difference in impedance, for example, if the circuits as shown in FIGS. 2A and 2B are used, if the input addresses AY _{1 to} AY _m , XAY _{1 are used.}
~ XAY _m is a fuse ROM (read only memory)
Stored defective address when a match with the (redundant address) for all the output AY ₁ ~AY _m becomes all high within, a plurality of MOS transistors Q _n1 connected in series
To Q _nm are all turned on, is connected to the power supply 20 via a series resistor R _st plurality of MOS transistors Q _n1 to Q _nm.

On the other hand, input addresses AY _{1 to} AY _m , XA
If Y _{1 to} XAY _m do not match the defective address (redundant address) stored in the fuse ROM (read only memory), a plurality of MOS transistors Q _n1 to
Any one of Q _nm is turned off, and the series impedance of the plurality of MOS transistors Q _{n1 to} Q _nm becomes extremely large (open state).

By the way, in FIG. 2A, the transistor Q _np is designed to have an impedance R _ss which is considerably higher than the series combined impedance of the plurality of MOS transistors Q _{n1 to} Q _nm . Specifically, MOS
The impedance R _ss can be adjusted by designing the gate voltage and the channel width of the transistor Q _np . That is,
In the case of the circuit shown in FIG. 2A, the first impedance is R _ss · R _st / (R _ss + R _st ), and the second impedance is R _ss .

As shown in FIG. 1, the impedance information is input to the spare generation circuits 3-1 to 3-N as well as the address comparison line 4 of the redundant address comparison circuits 1-1 to 1-N. -1 to 4-N are respectively connected to the cathode terminals of the unidirectional two-terminal elements 6-1 to 6-N that do not flow current in one direction only, and the anode terminals are commonly connected. Since the anode terminal is connected to the overall redundant use detection circuit 2, it is also transmitted to the overall redundant use detection circuit 2.

Here, the unidirectional two-terminal elements 6-1 to 6-
As shown in FIG. 3A, N is a diode formed by a MOS transistor, but naturally a diode using a semiconductor PN junction may be used. The function of the diode electrically isolates the nodes of the outputs C-1 to C-N of the plurality of redundant address comparison circuits 1-1 to 1-N from each other, and the overall redundancy use detection circuit 2 From the viewpoint, it is to realize that the nodes of the respective outputs C-1 to C-N are electrically connected.

With the configuration shown in FIG. 3A, the impedance value seen from the overall redundant use detection circuit 2 is
Each output C of the plurality of redundant address comparison circuits 1-1 to 1-N
-1C-N node, MOS transistors Q _n1 ~
Whether all of the Q _nm series circuits (see FIG. 2 (a)) are turned on is present or absent is determined by checking the combined output CT of the unidirectional two-terminal elements 6-1 to 6-N. Judging by the magnitude of the impedance between the node and the power supply 20, it is possible to judge whether or not there is redundant use as a whole.

MOS transistor Q_n1~ Q_nmSeries circuit of
If all are turned on, then above
The impedance between the output CT node and the power supply 20 is
1 / (1 / R_st+ N / R_ss), And if it does not exist
If the impedance is R _ss/ N. Where N
Is the number of redundant address comparison circuits 1-1 to 1-N.
Impedance R_ssIs the value of R_st<R_ss/ N
Is designed.

FIG. 3 (b) shows a concrete example of the entire redundant use detection circuit 2 including an impedance input differential amplifier for reading the impedance difference between the nodes of the output CT and judging whether or not the impedance value is in the redundant state. The configuration is shown. The impedance input differential amplifier, which is the overall redundant use detection circuit 2, will be described below with reference to the circuit diagram of FIG. 3B and the operation diagram of FIG.

In FIG. 3B, S ₂₁ is a switch and Q is
_{d1 to} Q _d4 , Q _pr and Q _d5 are MOS transistors. C
Of MOS type cross-coupled amplifier (Q _d1 ~Q _d4), N-type constituting the N-type cross-coupled amplifier MO
The source electrodes of the S transistor pair Q _d3 and Q _d4 are separated, and one N-type MOS transistor Q _d3 is connected to the node of the output CT having information on whether or not the redundancy is used, and the other N-type MOS transistor.
The transistor Q _d4 is connected to the reference line 7 having an appropriate impedance (impedance when the MOS transistor Q _pr is conducting) as a reference value.

When this impedance input differential amplifier is used in the overall redundant use detection circuit 2, appropriate impedance values are 1 / (1 / R _st + N / R _ss ) and R _ss / N.
The impedance of the reference line 7 may be set approximately in the middle of However, in this case, a diode (unidirectional two-terminal element)
Although the resistance value (R _do ) of is not taken into consideration, when it is taken into consideration, {R _do / N + 1 / ((1 / R _st + N / R _ss )} and {R _do / N + R _ss / N} are almost the same. It may be set in the middle.

The operation will be described. For example, the input address A
When Y _m and XAY _m change, the output AYI _m via the circuit shown in FIG. 2B changes, the impedance of the node of the output C-N of the redundant address comparison circuit 1-N changes, and at the same time, the output C-N is a unidirectional two-terminal element 6-1 to 6
The impedance of the node of the output CT bundled via −N changes. The output C-N node and the output CT
Potentials of the nodes are ground potential (GND) and V _TN , respectively.
And does not change. Note that V _TN is a unidirectional two-terminal element 6-
1 to 6-N is the threshold voltage of the NMOS transistor.

The complementary outputs CO and XCO of the impedance input differential amplifier are once equalized with the PC and XPC signals, and then released. Then, one of the complementary outputs CO and XCO becomes high and the other becomes low due to the difference in impedance. Specifically, if the impedance of the output CT is lower than the reference line 7, the point a becomes lower than the point b, the output CO becomes high and the output XCO becomes low. In FIG. 4, considering the operation delay time represented by T _d , in this embodiment, the redundant address comparison circuit 1
The number N of -1 to 1-N becomes large, and outputs C-1 to C-N
Even if the stray capacitance of the node of the above and the node of the output CT becomes large, the voltage of each node does not change, and the charging and discharging time is not required. Therefore, the operation delay time T _d is as shown in FIG. And the redundant address comparison circuits 1-1 to 1-
It hardly depends on the number N of N.

Here, the PC and XPC signals and the conventional AT
The difference between the D signals is the same, except that the ATD signal has a few nanoseconds and a wider pulse width. PC and XPC signals are
Since the load capacitance to be equalized is lighter than that of the ATD signal, the pulse width is narrowed because the time required for equalization can be shortened. As a result, the activation timing of the impedance input differential amplifier is advanced, and the effect of speeding up can be expected.

In FIG. 6, an input used as a spare circuit 3-N is used.
The circuit diagram of a impedance input differential amplifier is shown. Smell in Figure 6
S_{twenty two}Is a switch, Q_e1~ Q_e4, Q_ps, Q_e5Is MOS
Transistor, IN_{twenty one}, IN_{twenty two}Is an inverter and
In terms of road, it has a configuration similar to that of the entire redundant use detection circuit.
It CMOS cross-coupled amplifier (Q_e1~
Q_e4), An N-type cross-coupled amplifier is constructed.
N-type MOS transistor pair Q _e3, Q_e4The source electrode of
Separated, one N-type MOS transistor Q_e3Is the output C-N
Of the other N-type MOS transistor Q_e4
Is an appropriate impedance (MOS transistor) as a reference value.
Dista Q_psReference line 8 having impedance when conducting)
Connected to.

When the impedance input differential amplifier is used for the spare circuit 3-N, an appropriate impedance value is, for example, used for the spare generation circuits 3-1 to 3-N. In case of R
_It may be set approximately in the middle of _st and R _ss . Hereinafter, a redundant circuit of a semiconductor memory according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 7 and FIG. 8 respectively show an entire redundant use detecting circuit 2 (or spare circuits 3-3 to 3-3) in a semiconductor memory redundant circuit showing a second embodiment of the present invention.
FIG. 3 is a circuit diagram and an operation waveform diagram of an impedance input differential amplifier used in N). Only the points different from the first embodiment will be described below. As shown in FIG. 7, among the CMOS type cross-coupled amplifiers (Q _{d1 to} Q _d4 ), the source electrode of the N-type MOS transistor pair (Q _d3 , Q _d4 ) forming the N-type cross-coupled amplifier is The output CT node (spare circuit 3)
-3 to 3-N, output C-1 to C-N nodes)
In addition to connecting to the reference line 7 (reference line 8 in the case of the spare circuits 3-3 to 3-N) having the appropriate impedance as a reference value, the following circuit is added.

That is, the P-type MOS transistor Q _pp1
And the MOS transistor Q _pp2 are connected in series, and the gate of the MOS transistor Q _pp1 is controlled by the PC signal.
The gate of the transistor Q _pp2 has a node of the output CT (in the case of the spare circuits 3-3 to 3-N, the outputs C-1 to C-N).
Unidirectional two-terminal elements 6-1 to 6-connected to the node
N drain).

Similarly, a P-type MOS transistor Q _pp3
And the MOS transistor Q _pp4 are connected in series, the gate of the MOS transistor Q _pp3 is controlled by the PC signal, and the MOS
The gate of the transistor Q _pp4 is connected to the point b to which the drain of the MOS transistor Q _pr forming the reference impedance is connected, that is, the drain of the MOS transistor Q _pp4 .

With this configuration, as shown in FIG.
The potential at point a rises by the amount indicated by V ₁ from the relationship between the output CT and the series impedance of the MOS transistors Q _pp1 and Q _pp2 while the PC signal is in a pulsed low state. The potential at the point b rises by V _{2 due} to the relationship between the impedance at the point b on the reference line 7 and the series impedance of the MOS transistors Q _pp3 and Q _pp4 . The difference of the increase (V ₁ −V ₂ ) is several hundred mV.
Yes, CMOS type cross-coupled amplifier (Q _d1 ~
This leads to the stabilization of the operation of Q _d4 ) and the realization of high speed.

As described above, according to this embodiment, the CM
Of the OS type cross-coupled amplifiers (Q _{d1 to} Q _d4 ),
The potential difference between the source electrodes of the N-type MOS transistor pair Q _d3 and Q _d4 forming the N-type cross-coupled amplifier can be increased, and the speed can be increased. In addition,
In the above embodiment, the modification of the overall redundant use detection circuit 2 has been mainly described, but the spare circuits 3-1 to 3-N.
It goes without saying that the same can be modified in the same manner as the overall redundant use detection circuit 2.

The third embodiment of the present invention will be described below with reference to the drawings. 9, 10, and 11
3A and 3B respectively show an on-chip layout diagram and a circuit diagram of a spare generation circuit used in a redundancy circuit of a semiconductor memory according to a third embodiment of the present invention and an impedance input differential amplifier used in an overall redundancy use detection circuit. . Only the points different from the first embodiment will be described below.

FIG. 9 shows where in the DRAM chip the redundant address comparison circuit 1, the spare generation circuit 3 and the overall redundant use detection circuit 2 are arranged and the memory cells are arranged in the third embodiment. The outline of the signal path of how to finally access the memory sub array 31 in the memory array 30 is shown. Explaining only the points different from the conventional example shown in FIG. 15, in the third embodiment, as shown in FIG. 9, for example, the address comparison lines CN are arranged from the center on the memory chip to the corners on the memory chip. Up to the memory sub-array 31 up to and the impedance input differential amplifier used for the spare generation circuit 3 is arranged for each memory sub-array 31.
As shown in, the selection signal BLK of the memory sub array 31
Output C- through a transfer gate G ₁ controlled by
The N node (address comparison line 4) and the spare generation circuit (impedance input differential amplifier) 3 are connected. Similarly, the node 5 of the output CT is routed as it is to the memory sub-array 31 from the center of the chip to the corners of the chip, and the impedance input differential amplifier used in the overall redundancy use detection circuit 2 is provided for each memory sub-array 31. As shown in FIG. 11, the node of the output CT and the entire redundant use detection circuit (impedance input differential amplifier) 2 are connected via the transfer gate G ₂ controlled by the sub array selection signal BLK of the memory sub array 31. To do.

With such a structure, even if the length of the signal path of, for example, 64 Mbit DRAM class, which is 12 mm due to the increase in the capacity of the memory, exceeds 12 mm, that signal line, that is, the outputs C-1 to C. The potentials of the node of −N and the node of output CT remain fixed near the ground level and do not change the voltage of the power supply voltage level, that is, a large wiring capacitance of several tens pF is hardly charged and discharged. There is no delay time and the speedup is possible.

[0047]

According to the redundancy circuit of the semiconductor memory of the present invention, the address comparison line, which is the output of the address comparison circuit, can be directly input to the entire redundancy use detection circuit through the unidirectional two-terminal element. The operation of the redundant use detection circuit can be started almost at the same time as the address input, and the speed can be increased. Moreover, since the impedance of the address comparison line only changes and it is not necessary to charge and discharge it for a voltage change, there is no delay time for that and speeding up is possible. As described above, the present invention can solve the problem of the read delay of the memory in which the redundant circuit is mounted, and its practical effect is great in the read circuit of the high density and high speed DRAM.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a redundant circuit according to a first embodiment of the present invention.

2A is a circuit diagram of a rear stage portion of the redundant address comparison circuit in FIG. 1, and FIG. 2B is a circuit diagram of a front stage portion of the redundant address comparison circuit in FIG.

3A is a circuit diagram showing a connection state of an address comparison line and an entire redundant use detection circuit in FIG. 1, and FIG.
3 is a circuit diagram of an impedance input differential amplifier used in the overall redundant use detection circuit in FIG.

FIG. 4 is an operation waveform diagram of a redundant circuit of the semiconductor memory in FIG.

FIG. 5 is a relationship diagram between the operation delay time and the number of redundant address comparison circuits of the redundant circuit of the semiconductor memory of the present invention and the conventional example.

FIG. 6 is a circuit diagram of an impedance input differential amplifier used in the spare generation circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of an impedance input differential amplifier used in the overall redundant use detection circuit according to the second embodiment of the present invention.

FIG. 8 is an operation waveform diagram of the impedance input differential amplifier according to the second embodiment of the present invention.

FIG. 9 is an on-chip layout diagram of a redundant circuit of a semiconductor memory according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram of an impedance input differential amplifier used in a spare generation circuit according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram of an impedance input differential amplifier used in the overall redundant use detection circuit according to the third embodiment of the present invention.

FIG. 12 is a conceptual diagram of a redundant circuit of a semiconductor memory in a conventional example.

13A is a circuit diagram of a redundant address comparison circuit in a conventional example, FIG. 13B is the same overall redundant use detection circuit, FIG.
(C) is a circuit diagram of the spare generation circuit.

FIG. 14A is an operation waveform diagram of a redundant circuit of a semiconductor memory in a conventional example, and FIG. 14B is a relationship diagram of an operation delay time of the redundant circuit and the number of redundant address comparison circuits.

FIG. 15 is an on-chip layout diagram of a redundant circuit of a semiconductor memory in a conventional example.

[Explanation of symbols]

 1-1 to 1-N redundant address comparison circuit 2 overall redundant use detection circuit 3-1 to 3-N spare generation circuit 4-1 to 4-N address comparison line 5-1 to 5-N spare line 6-1 to 6-N Unidirectional two-terminal element

Claims (7)

[Claims] 1. When a first impedance is interposed between a power supply and a redundant address comparison line when the input address matches the redundant address and the input address does not match the redundant address. Of a plurality of redundant address comparison circuits, in which a second impedance having a value different from the first impedance is interposed between the power supply and the redundant address comparison line; A plurality of spare generation circuits each having an input terminal connected to the redundant address comparison line, and a plurality of unidirectional two-way circuits each having a cathode terminal connected in common and an anode terminal commonly connected to the redundant address comparison lines of the plurality of redundant address comparison circuits. Detection of overall redundant use by connecting an input terminal to the terminal element and the anode terminals of the plurality of unidirectional two-terminal elements A redundant circuit of a semiconductor memory including a circuit. 2. The spare generation circuit comprises an impedance input differential amplifier, one input terminal of the differential amplifier is connected to a redundant address comparison line, and the other input terminal of the differential amplifier has a first impedance. 2. The redundancy circuit for a semiconductor memory according to claim 1, wherein the redundancy circuit is connected to a reference line connected to a power source through a third impedance having an intermediate value between the second impedance and the second impedance. 3. The redundant use detection circuit comprises an impedance input differential amplifier, one input terminal of the differential amplifier is connected to an anode terminal of a unidirectional two-terminal element, and the other input of the differential amplifier is provided. 2. The redundant circuit of the semiconductor memory according to claim 1, wherein the terminal is connected to a reference line connected to a power supply via a third impedance having an intermediate value between the first impedance and the second impedance. 4. The redundant circuit of a semiconductor memory according to claim 2, wherein another power supply is connected to the redundant address comparison line and the reference line via a transistor which is conductive in a pulse manner. 5. The redundant circuit of the semiconductor memory according to claim 3, wherein another power source is connected to the anode terminal of the unidirectional two-terminal element and the reference line through a transistor which is conductive in a pulsed manner. 6. The spare generation circuit comprises an impedance input differential amplifier, and one input terminal of the differential amplifier is connected to a redundant address comparison line wired from a central memory block to a corner memory block of a semiconductor chip. The other input terminal of the differential amplifier is connected via a transfer gate controlled by a selection signal, and is connected to a power supply via a third impedance having an intermediate value between the first impedance and the second impedance. The redundant circuit of the semiconductor memory according to claim 1, wherein the redundant circuit is connected to the reference line. 7. The redundant use detection circuit comprises an impedance input differential amplifier, and one input terminal of the differential amplifier is a unidirectional two-terminal wired from a central memory block to a corner memory block of a semiconductor chip. The anode terminal of the element is connected via a transfer gate controlled by a block selection signal, and the other input terminal of the differential amplifier is a first input terminal.
2. The redundant circuit of the semiconductor memory according to claim 1, wherein the redundant circuit is connected to a reference line connected to a power supply through a third impedance having an intermediate value between the impedance of the second impedance and the impedance of the second impedance.