JP2928049B2 - Redundancy circuit for semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant circuit of a semiconductor memory, and is effective for a redundant circuit such as a detection circuit for detecting whether or not an input address matches a redundant address (that is, a defective address). It is about technology.

[0002]

2. Description of the Related Art A conventional redundant circuit of a semiconductor memory will be described with reference to FIGS. FIG. 12 shows a redundant circuit of a conventional semiconductor memory. In FIG.
Reference numerals 11-1 to 11-N denote voltage conversion type redundant address comparison circuits which receive the address AY as inputs, and outputs C-1 to CN from redundant address comparison lines 14-1 to 14-N, respectively.
Occurs. Reference numeral 12 denotes N redundant address comparison circuits 11-
An output CO is generated by a voltage conversion type entire redundant use detection circuit which receives the outputs C-1 to CN of 1 to 11-N as inputs.
Reference numerals 13-1 to 13-N denote voltage conversion type spare generating circuits which receive outputs C-1 to CN of N redundant address comparing circuits 11-1 to 11-N, respectively.
Outputs SP-1 to SP-N are generated from -1 to 15-N.

A conventional redundancy judgment circuit will be schematically described with reference to FIG.
Will be explained. There are two types of redundancy judgment circuits.
Address AY (AY₁~ AY_m, XAY₁~ X
AY _m) Is, for example, a fuse ROM (read only
Memory) and the defective address (redundant address)
Redundant address comparison circuit 11- for determining whether they match
1 to 11-N. The judgment result is the redundant address ratio.
The dynamic NOR circuit shown in FIG.
Path (MOS transistor Q_a1~ Q_am, Q_b1~ Q _bm,
Q_p1, Q_q1, Fuse F_a1~ F_am, F_b1~ F_bm,dry
BA DR₁And so on. The figure shows an example of a redundant
(Shows the configuration of the dress comparison circuit 11-N).
This allows the output voltage to be output whether the logic level is high or low.
It is.

[0004] Another redundancy judgment circuit is a duplication circuit as a whole.
Several redundant address comparison circuits 11-1 to 11-N
At least one of the addresses AY is a redundant address (defective address).
Dress) or none of them
This is the entire redundant use detection circuit 12 for judging whether or not there is a failure. So
The determination result of FIG.
The dynamic NOR circuit shown in FIG.
Star Q_C1~ Q_CN, Q_p2, Q _q2, Driver DR_TwoEtc.
Is used, the output voltage becomes a logic level high.
Or low.

The operation of the above redundancy judgment is schematically shown in FIG.
This will be described with reference to FIG. For example, input address A
When Y _n and XAY _n change, the signal ATD that detects the change becomes pulse-like low, and the first stage dynamic N
For example, the potential of the output CN of the redundant address comparison circuit 11-N, which is an OR circuit, is changed. Then, the voltage change is input to the entire redundant use detection circuit 12, which is a subsequent dynamic NOR circuit, and similarly changes the potential of the output CO. In this case, after the input addresses AY _n and XAY _n change, the time T _d is required until the potential of the output CO changes.
Operation delay occurs. FIG. 14B shows the operation delay time T
FIG. 14B shows the relationship between _d and the number N of nodes of the outputs C- ₁ to C-N, and it can be seen from FIG. 14B that the operation delay time T _d increases substantially proportionally as the number N of nodes increases.

The redundant address comparison circuits 11-1 to 11-N
Are output to spare generating circuits 13-1 to 13-N which are provided in one-to-one correspondence. Spare generation circuits 13-1 to 13-N basically include drivers DR ₃ and DR ₄ as shown in FIG.
Cascaded circuits. FIG. 13C shows a spare generation circuit 13-N as an example.

The output of the entire redundant use detection circuit 12 is used to generate a normal line inhibition signal or an activation signal. FIG. 15 shows a redundant address comparison circuit 11 (redundancy address comparison circuit 11-1) in a chip of a dynamic random access memory (hereinafter referred to as DRAM).
To 11-N), a spare generation circuit 13 (representing a collection of spare generation circuits 13-1 to 13-N), and a general redundant use detection circuit 12 where the memory is generally located. Memory array 30 in which cells are arranged
3 schematically shows a signal path that represents how to finally access the memory sub-array 31 in FIG. SP
Indicates an output of the spare generation circuit 13, and BLK indicates a memory array block selection signal for controlling a transfer gate.

With the increase in memory capacity, for example, in the case of a 64 Mbit DRAM, the length of a signal path is 12 mm.
For example, when the output SP of the spare generating circuit 13 arranged at the center of the chip reaches the memory sub-array 31 by transmitting a signal line of 12 mm, the output SP is selected by the transfer gate control by the memory array block selection signal BLK,
Finally, the target memory cell can be accessed.

However, during this time, the output SP of the spare generating circuit 13 is greatly delayed due to wiring delay. As a result, the generation of the spare line is delayed, and the access of the spare cell is delayed.
In this situation, the output CO of the entire redundant use detection circuit 12 is the same. Incidentally, if the generation of the inhibit signal or the activation signal of the normal line is delayed, the following problems occur. If the prohibition signal is delayed, multiple selection of a normal line and a spare line that are not temporarily prohibited occurs, and the reading speed is reduced. On the other hand, if the activation signal is delayed, there is a problem that the reading of the memory cell is delayed by that amount, and all of these problems become obstacles to speeding up the reading.

[0010]

A conventional fuse ROM
Since the redundant address comparison determination as to whether or not it matches the defective address (redundant address) stored in the (read only memory) is performed by a dynamic NOR circuit as shown in FIG. As shown in FIG. 14B, the operation of the dynamic NOR circuit is slowed down due to an increase in stray capacitance at the node of the output CN due to an increase in the number of fuse ROMs associated with an increase in capacity. That is, there is a problem that the charging time of the node of the output C-N by the P-type MOS transistor Q _{p1 in} FIG. The same applies to each node of the other outputs C-1 to C- (N-1).

The output voltage of the dynamic NOR circuit which is the redundant address comparing circuit 11 is inputted to another dynamic NOR circuit which is the entire redundant use detecting circuit 12 as shown in FIG. If the generation of the output voltage of the circuit 11 is delayed, the generation of the output CO of the subsequent overall redundant use detection circuit 12 is naturally delayed. Further, the operation of the subsequent dynamic NOR circuit is also the same as the delay of the previous dynamic NOR circuit due to the increase in memory capacity, and the P-type MOS transistor Q in FIG.
_Since the charging time of the node of the output _CN by _p2 becomes long and a delay occurs, the generation of the inhibit signal of the normal line is delayed, and the multiple selection of the normal line and the spare line which are not temporarily inhibited occurs, and the read operation is performed. There is a problem of slowing down.

An object of the present invention is to provide a redundant circuit of a semiconductor memory which can achieve a large capacity and a high speed.

[0013]

A redundant circuit of a semiconductor memory according to the present invention has a first impedance interposed between a power supply and a redundant address comparison line when an input address matches a redundant address. A plurality of redundant address comparison circuits for setting a state in which a second impedance having a value different from the first impedance is interposed between the power supply and the redundant address comparison line when the input address does not match the redundant address. A plurality of redundant address comparison lines of a plurality of redundant address comparison circuits are connected to input terminals of a plurality of spare generation circuits, respectively, and a plurality of redundant address comparison lines of a plurality of redundant address comparison circuits that allow current to flow only in one direction. The anode terminals of a plurality of unidirectional two-terminal devices are connected in common to the cathode terminals of the unidirectional two-terminal device, Connecting the anode terminal of the unidirectional two-terminal element to an input terminal of the entire redundant use detection circuit.

The spare generating circuit comprises an impedance input differential amplifier. One input terminal of the differential amplifier is connected to the redundant address comparison line, and the other input terminal of the differential amplifier has the first impedance and the first input terminal. It is connected to a reference line connected to a power supply via a third impedance having an intermediate value between the two impedance values. The redundant use detection circuit includes an impedance input differential amplifier, one input terminal of the differential amplifier is connected to the anode terminal of the unidirectional two-terminal element, and the other input terminal of the differential amplifier is connected to the first input terminal. It is connected to a reference line connected to a power supply via a third impedance having a value intermediate between the values of the impedance and the second impedance.

[0015]

According to the structure of the present invention, when the input address matches the redundant address, the first impedance is inserted between the power supply and the redundant address comparison line, and the input address does not match the redundant address. Then, the second impedance is inserted between the power supply and the redundant address comparison line, and the difference in impedance of the address comparison line is input to the spare generation circuit. In the spare generating circuit, the input address matches the defective address stored in the fuse ROM (read only memory), that is, the redundant address, by determining the difference in the impedance of the address comparison line using the impedance input differential amplifier. Is determined. Almost simultaneously with the determination operation, the redundant address comparison line is input to the entire redundant use detection circuit through a unidirectional two-terminal element that allows current to flow only in one direction, thereby allowing the input of the entire redundant use detection circuit to be input. The difference in impedance of the address comparison line is also transmitted to the terminal, and at the same time as the above determination operation, it is determined whether or not redundant use has been performed using the impedance input differential amplifier.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a redundant circuit of a first semiconductor memory according to the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram schematically showing a redundant circuit of an impedance detection type semiconductor memory according to a first embodiment of the present invention. FIG. 2A is a circuit diagram of the latter part of the redundant address comparison circuit in FIG. 1 (part where the impedance is switched by matching / mismatch between the input address and the redundant address), and FIG. 2B is a circuit diagram of the redundant address comparison circuit in FIG. FIG. 3 is a circuit diagram of a former part (a part for comparing an input address and a redundant address), and m circuits in the former part are connected to circuits in a latter part of FIG. FIG. 3 (a)
FIG. 3B is a circuit diagram showing a connection state between the address comparison lines 4-1 to 4-N, that is, the nodes of the outputs C-1 to C-N in FIG. 1 and the entire redundant use detection circuit 2, and FIG. 3 is a circuit diagram of an impedance input differential amplifier used as the entire redundant use detection circuit 2 in FIG. FIG. 4 is an operation waveform diagram of the redundant circuit of the semiconductor memory of FIG.

As shown in FIG. 1, the redundancy circuit of this semiconductor memory is provided with a plurality of impedance conversion type redundancy address comparison circuits 1-1 to 1-N having an address AY as an input, and a plurality of redundancy address comparison circuits. The redundant address comparison lines 4-1 to 4-N of 1-1 to 1-N are connected to the input terminals of a plurality of spare generation circuits 3-1 to 3-N, respectively. 1-N redundant address comparison lines 4-1 to 4-N are respectively connected to the cathode terminals of a plurality of unidirectional two-terminal elements 6-1 to 6-N that allow current to flow in only one direction, and Directional two-terminal elements 6-1 to 6-
N anode terminals are commonly connected, and anode terminals of the plurality of unidirectional two-terminal elements 6-1 to 6-N are connected to input terminals of the overall redundant use detection circuit 2.

The redundant address comparison circuits 1-1 to 1-N
When the input address AY matches the redundant address, a power supply (not shown) and redundant address comparison lines 4-1 to 4-
N and a first impedance (not shown) between the power supply and the redundant address comparison line 4-1 when the input address does not match the redundant address.
To 4-N, and a second impedance (not shown) having a value different from the first impedance is interposed between the redundant address comparison lines 4-1 to 4-N. -1 to CN are generated.

The voltage conversion type entire redundant use detection circuit 2
Output C- of N redundant address comparison circuits 1-1 to 1-N
Complementary outputs CO and XCO are generated by inputting the combined outputs CT of the unidirectional two-terminal elements 6-1 to 6-N to 1 to CN. The voltage conversion type spare generation circuits 3-1 to 3-N have N
Output C-1 of the redundant address comparison circuits 1-1 to 1-N
To CN respectively, and outputs SP-1 to SP-N from spare lines 5-1 to 5-N.

The redundant address comparison circuits 1-1 to 1-N have an impedance conversion function as described above, and have the same configuration. For example, the redundant address comparison circuit 1-N
The latter part (the part where the impedance is switched by matching / mismatch between the input address and the redundant address) has the configuration shown in FIG. 2A, and the former part (the part comparing the input address and the redundant address) is shown in FIG. ).

That is, as shown in FIG. 2A, the subsequent stage of the redundant address comparison circuit 1-N connects the node of the output _CN to the power supply 20 (for example, a ground power supply) via the MOS transistor _Qnp. In addition, it is connected to a power supply 20 via MOS transistors Q _{n1 to} Q _nm connected in series. At this time, as viewed from the output CN, the power supply 20 (for example,
MOS transistor Q commonly connected to
and the MOS transistor Q _n1 ~Q _nm was said and _np series connection
Are connected in parallel with each other, and
The impedance between the power supplies 20 is determined. MOS
The transistor Q _np is _supplied with a gate signal so as to be always in a conductive state, and the impedance of the conductive state is R _ss
Becomes _M MOS transistors Q _n1 connected in series
ＱQ _nm , the series combined impedance when all of the gate signals AYI _{1 to} AYI _m are high and all of them are conductive is R _st . In FIG. 2A, i is an output
A current flowing through the node C-N, i ₁ is the current i
M MOs connected in series from the output C-N node
Is a current flowing to S transistors Q _{n1 to} Q _nm , and i ₂ is
From the node of the output CN of the current i, the MOS transistor
This is a current flowing to the star Q _np .

Further, preliminary portion of the redundant address comparator 1-N, for example, for example, part of the input address AY _m of the input address AY, as shown in FIG. 2 (b), the switch S _11, S ₁₂ , Inverters IN ₁₁ , IN ₁₂ ,
MOS transistor Q _g1, consist capacitor C ₁ and a fuse F _c1, the input address AY _m, high in Xay _m, output AYI _m becomes high when the intermittent state of the low state and the fuse F _c1 match, mismatch When it is, it becomes low. Such a circuit is called address A
When Y is m bits from AY ₁ to AY _m, there are m bits.

In the above configuration, the node of the output CN of the redundant address comparing circuit 1-N, that is, the address comparing line 4-N is connected to the power supply 20 when the input address AY matches the redundant address. If the input address does not match the redundant address, the power supply 20 is connected to the power supply 20 with a relatively high second impedance.

As a method of generating a difference in impedance, for example, a circuit as shown in FIGS. 2A and 2B may be used if input addresses AY _{1 to} AY _m and XAY _{1 are used.}
~ XAY _m is fuse ROM (read only memory)
, All outputs AY _{1 to} AY _m go high, and a plurality of MOS transistors Q _n1 connected in series.
To Q _nm are turned on, and are connected to the power supply 20 via the series resistor R _st of the plurality of MOS transistors Q _{n1 to} Q _nm .

On the other hand, input addresses AY _{1 to} AY _m , XA
If Y _{1 to} XAY _m do not match the defective address (redundant address) stored in the fuse ROM (read only memory), the plurality of MOS transistors Q _n1 to
Any of Q _nm is turned off, and the series impedance of the plurality of MOS transistors Q _{n1 to} Q _nm becomes extremely large (open state).

In FIG. 2A, the transistor Q _np is designed to have an impedance R _ss which is considerably larger than the series combined impedance of the plurality of MOS transistors Q _{n1 to} Q _nm . Specifically, MOS
The impedance R _ss can be adjusted by designing the gate voltage and channel width of the transistor Q _np . That is,
In the case of the circuit shown in FIG. 2A, the first impedance is R _ss · R _st / (R _ss + R _st ), and the second impedance is R _ss .

As shown in FIG. 1, the information on the impedance is input to the spare generation circuits 3-1 to 3-N and, of course, the address comparison lines 4 of the redundant address comparison circuits 1-1 to 1-N. -1 to 4-N are connected to the cathode terminals of the unidirectional two-terminal elements 6-1 to 6-N which allow current to flow only in one direction and to which the current does not flow, respectively, and the anode terminals are all connected in common. Since the anode terminal is connected to the entire redundant use detection circuit 2, the signal is also transmitted to the full redundant use detection circuit 2.

Here, the unidirectional two-terminal elements 6-1 to 6-
N is a diode formed by a MOS transistor as shown in FIG. 3A, but may naturally be a diode using a semiconductor PN junction. The function of this diode is to electrically isolate the nodes of the respective outputs C-1 to CN of the plurality of redundant address comparison circuits 1-1 to 1-N, and to detect the entire redundant use detection circuit 2 Accordingly, it is to realize that the nodes of the respective outputs C-1 to C-N are electrically connected.

In the configuration shown in FIG. 3A, the impedance value as viewed from the entire redundant use detection circuit 2 is:
Each output C of the plurality of redundant address comparison circuits 1-1 to 1-N
-1C-N, MOS transistors Q _n1 .
The presence or absence of all the Q _nm series circuits (see FIG. 2 (a)) turned on is determined by the combined output CT of the unidirectional two-terminal elements 6-1 to 6-N. Judging from the magnitude of the impedance between the node and the power supply 20, it is possible to judge whether or not there is redundant use as a whole.

MOS transistor Q_n1~ Q_nmSeries circuit
If there is something with all of
The impedance between the output CT node and the power supply 20 is
1 / (1 / R_st+ N / R_ss), And if it does not exist
If the impedance is R _ss/ N. Where N
Is the number of redundant address comparison circuits 1-1 to 1-N.
Impedance R_ssIs R_st<R_ss/ N
Designed.

FIG. 3B shows a specific example of the entire redundant use detection circuit 2 comprising an impedance input differential amplifier for reading the impedance difference between the nodes of the output CT and judging whether or not the value is the impedance value at the time of redundancy. 1 shows the configuration. Hereinafter, the impedance input differential amplifier which is the entire redundant use detection circuit 2 will be described with reference to the circuit diagram of FIG. 3B and the operation diagram of FIG.

In FIG. 3B, S ₂₁ is a switch, Q
_{d1 ~Q d4, Q pr, Q} d5 is a MOS transistor. C
Of the MOS cross-coupled amplifiers (Q _{d1 to} Q _d4 ), an N-type MO constituting an N-type cross-coupled amplifier
The source electrodes of the pair of S transistors Q _d3 and Q _d4 are separated, and one N-type MOS transistor Q _d3 is connected to the node of the output CT having information on whether or not to use the redundancy, and the other N-type MOS transistor
Transistor _Qd4 is connected to reference line 7 having an appropriate impedance (impedance when MOS transistor _Qpr is conductive) as a reference value.

When this impedance input differential amplifier is used in the entire redundant use detection circuit 2, appropriate impedance values are 1 / (1 / _Rst + N / _Rss ) and _Rss / N
The impedance of the reference line 7 may be set to approximately the middle of the above. However, in this case, a diode (unidirectional two-terminal element)
The resistance value (R _do ) is not taken into account, but when it is taken into account, approximately {R _do / N + 1 / ((1 / R _st + N / R _ss )}} and {R _do / N + R _ss / N} It may be set in the middle.

The operation will be described. For example, the input address A
Y _m, the Xay _m is changed, the circuit output AYI _m is changed over as shown in FIG. 2 (b), the impedance of the node of the output C-N of the redundant address comparator 1-N is changed, at the same time the output CN is a unidirectional two-terminal element 6-1 to 6
The impedance of the node of the output CT bundled via −N changes. Note that the node of the output CN and the output CT
Are the ground potential (GND) and V _{TN respectively.}
And does not change. V _TN is a unidirectional two-terminal element 6−
This is the threshold voltage of the NMOS transistors constituting 1 to 6-N. Also, i is the total redundant use detection circuit 2
The output C-N of the internal and full redundant use detection circuit 2
This is the current flowing through the node.

The complementary outputs CO and XCO of the impedance input differential amplifier are once equalized by the PC and XPC signals, and then released. Then, one of the complementary outputs CO and XCO goes high and the other goes low due to the impedance difference. Specifically, if the impedance of the output CT is lower than the reference line 7, the point a becomes lower than the point b, the output CO becomes high, and the output XCO becomes low. In FIG. 4, considering the operation delay time represented by _Td , in this embodiment, the redundant address comparison circuit 1
The number N of -1 to 1-N increases, and the outputs C-1 to C-N
Even if the stray capacitance of the output node and the node of the output CT becomes large, the voltage does not change at each node, and the charging and discharging time is not required. Therefore, the operation delay time _Td is as shown in FIG. The redundant address comparison circuits 1-1 to 1-
It hardly depends on the number N of N.

Here, the PC and XPC signals and the conventional AT
The difference between the D signals is the same except that the ATD signal is several nanoseconds and has a wider pulse width. PC and XPC signals are
Since the load capacity to be equalized is lighter than the ATD signal, the pulse width is narrowed because the time required for equalization can be reduced. Thereby, the activation time of the impedance input differential amplifier is advanced, so that an effect of speeding up can be expected.

FIG. 6 shows a circuit used as a spare circuit 3-N.
FIG. 2 shows a circuit diagram of a impedance input differential amplifier. Figure 6
And S_{twenty two}Is a switch, Q_e1~ Q_e4, Q_ps, Q_e5Is MOS
Transistor, IN_{twenty one}, IN_{twenty two}Is the inverter,
In terms of circuit, the configuration is substantially the same as that of the entire redundant use detection circuit.
You. CMOS type cross-coupled amplifier (Q_e1~
Q_e4), Configure an N-type cross-coupled amplifier
N-type MOS transistor pair Q _e3, Q_e4Source electrode
Release one N-type MOS transistor Q_e3Is the output CN
And the other N-type MOS transistor Q_e4
Is a suitable impedance (MOS transformer) as a reference value.
Jista Q_psLine 8 with impedance when conducting
Connected to.

When the impedance input differential amplifier is used for the spare circuit 3-N, an appropriate impedance value is set, for example, by using the impedance input differential amplifier for the spare generation circuits 3-1 to 3-N. In that case, R
It may be set approximately halfway _st and R _ss. Hereinafter, a redundant circuit of a semiconductor memory according to a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 7 and 8 show a redundant circuit of a semiconductor memory according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram and an operation waveform diagram of an impedance input differential amplifier used in N). Hereinafter, only different points from the first embodiment will be described. As shown in FIG. 7, of the CMOS cross-coupled amplifiers (Q _{d1 to} Q _d4 ), the source electrode of the N-type MOS transistor pair (Q _d3 , Q _d4 ) constituting the N-type cross-coupled amplifier is changed. One of the nodes is connected to the output CT node (spare circuit 3)
In the case of -3 to 3-N, nodes of outputs C-1 to CN)
The other circuit is connected to the reference line 7 (in the case of the spare circuits 3-3 to 3-N, the reference line 8) having the appropriate impedance as the reference value, and the following circuit is added.

That is, the P-type MOS transistor Q _pp1
And the MOS transistor Q _pp2 are connected in series, the gate of the MOS transistor Q _pp1 is controlled by the PC signal,
The gate of the transistor Q _pp2 is _connected to the node of the output CT (in the case of the spare circuits 3-3 to 3-N, the outputs C-1 to CN).
Unidirectional two-terminal elements 6-1 to 6-
N drain).

Similarly, a P-type MOS transistor Q _pp3
And the MOS transistor Q _pp4 are connected in series, the gate of the MOS transistor Q _pp3 is controlled by the PC signal,
The gate of the transistor Q _pp4 is connected to the point b to which the drain of the MOS transistor Q _pr for creating a reference impedance is connected, that is, the drain of the MOS transistor Q _pp4 .

With this configuration, as shown in FIG.
The potential of the point a, the duration of the pulsed low state PC signal, from the ratio of the relationship between the series impedance of the output CT and MOS transistor Q _pp1, Q _pp2, increased by the amount indicated by V _1, similarly, the potential of the point b, the ratio of the relationship between the series impedance of the impedance of the point b on the reference line 7 and the MOS transistor Q _pp3, Q _pp4, rises by an amount indicated by V _2. The difference (V ₁ −V ₂ ) of the rise is several hundred mV
There is a CMOS type cross-coupled amplifier (Q _d1-
This leads to the stabilization of the operation of Q _d4 ) and the realization of high speed.

As described above, according to this embodiment, the CM
Of the OS type cross-coupled amplifiers (Q _{d1 to} Q _d4 ),
The potential difference between the source electrodes of the N-type MOS transistor pair Q _d3 and Q _d4 constituting the N-type cross-coupled amplifier can be increased, and the speed can be increased. In addition,
In the above embodiment, the modification of the entire redundant use detection circuit 2 has been mainly described, but the spare circuits 3-1 to 3-N
Needless to say, this can be modified in the same manner as the entire redundant use detection circuit 2.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. 9, 10, and 11
Shows a layout diagram and a circuit diagram, respectively, of a spare generation circuit used in a redundant circuit of a semiconductor memory according to a third embodiment of the present invention and an impedance input differential amplifier used in an entire redundant use detection circuit on a chip. . Only the differences from the first embodiment will be described below.

FIG. 9 shows where, in the third embodiment, the redundant address comparing circuit 1, spare generating circuit 3 and entire redundant use detecting circuit 2 are arranged in the DRAM chip, and the memory cells are arranged. The outline of a signal path of how to finally access the memory sub-array 31 in the memory array 30 is shown. Only the differences from the conventional example shown in FIG. 15 will be described. In the third embodiment, as shown in FIG. 9, for example, an address comparison line CN is moved from the center on the memory chip to the corner on the memory chip. 10 and the impedance input differential amplifier used in the spare generating circuit 3 is arranged for each memory sub-array 31.
As shown in FIG.
Through the transfer gate G _1, which is controlled by the output C-
A node N (address comparison line 4) and a spare generation circuit (impedance input differential amplifier) 3 are connected. Similarly, the node 5 of the output CT is directly routed from the center on the chip to the memory sub-array 31 from the corner to the corner of the chip, and the impedance input differential amplifier used in the entire redundant use detection circuit 2 is provided for each memory sub-array 31. arrangement and, as shown in FIG. 11, through the transfer gate G ₂ which is controlled by the sub-array selection signals BLK memory sub array 31, connecting the output node and the entire redundant use detection circuit CT (impedance input differential amplifier) 2 I do.

With such a configuration, even if the length of the signal path exceeds, for example, 12 mm, which is a 64-Mbit DRAM class signal path due to the increase in memory capacity, the signal line, that is, the outputs C-1 to C- Since the potential of the -N node and the node of the output CT remain fixed near the ground level and the voltage of the power supply voltage level does not change, that is, a large wiring capacitance of several tens of pF is hardly charged / discharged. No delay time, and high-speed operation is possible.

[0047]

According to the redundancy circuit of the semiconductor memory of the present invention, the address comparison line, which is the output of the address comparison circuit, can be directly input to the entire redundancy use detection circuit via the unidirectional two-terminal element. The operation of the redundant use detection circuit can be started almost simultaneously with the address input, and the speed can be increased. Further, since the address comparison line only changes in impedance and does not need to be charged / discharged for voltage change, it is possible to increase the speed without delay time. As described above, the present invention can solve the problem of reading delay of a memory having a redundant circuit, and has a great practical effect in a high-density, high-speed DRAM reading circuit.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a redundant circuit according to a first embodiment of the present invention.

FIG. 2A is a circuit diagram of a subsequent stage of the redundant address comparison circuit in FIG. 1, and FIG. 2B is a circuit diagram of a preceding stage of the redundant address comparison circuit in FIG.

3A is a circuit diagram showing a connection state between an address comparison line and an entire redundant use detection circuit in FIG. 1, and FIG.
FIG. 4 is a circuit diagram of an impedance input differential amplifier used in the entire redundant use detection circuit in FIG.

FIG. 4 is an operation waveform diagram of the redundant circuit of the semiconductor memory in FIG. 1;

FIG. 5 is a diagram showing the relationship between the operation delay time of the redundant circuit of the semiconductor memory of the present invention and the conventional example and the number of redundant address comparison circuits.

FIG. 6 is a circuit diagram of an impedance input differential amplifier used in a spare generation circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of an impedance input differential amplifier used in a full redundant use detection circuit according to a second embodiment of the present invention.

FIG. 8 is an operation waveform diagram of the impedance input differential amplifier according to the second embodiment of the present invention.

FIG. 9 is a layout diagram of a redundant circuit of a semiconductor memory in a chip according to a third embodiment of the present invention;

FIG. 10 is a circuit diagram of an impedance input differential amplifier used in a spare generating circuit according to a third embodiment of the present invention.

FIG. 11 is a circuit diagram of an impedance input differential amplifier used in a full redundant use detection circuit according to a third embodiment of the present invention.

FIG. 12 is a conceptual diagram of a redundant circuit of a semiconductor memory in a conventional example.

FIG. 13A is a circuit diagram of a redundant address comparison circuit in a conventional example, FIG.
(C) is a circuit diagram of the spare generating circuit.

FIG. 14A is an operation waveform diagram of a redundant circuit of a semiconductor memory in a conventional example, and FIG. 14B is a relationship diagram of the operation delay time of the redundant circuit and the number of redundant address comparison circuits.

FIG. 15 is a layout diagram in a chip of a redundant circuit of a semiconductor memory in a conventional example.

[Explanation of symbols]

 1-1 to 1-N redundant address comparison circuit 2 overall redundancy use detection circuit 3-1 to 3-N spare generation circuit 4-1 to 4-N address comparison line 5-1 to 5-N spare line 6-1 6-N unidirectional two-terminal element

Claims (7)

(57) [Claims] 1. A state where a first impedance is interposed between a power supply and a redundant address comparison line when an input address matches a redundant address, and when the input address does not match the redundant address. A plurality of redundant address comparison circuits, wherein a second impedance having a value different from the first impedance is interposed between the power supply and the redundant address comparison line; A plurality of spare generating circuits each having an input terminal connected to a redundant address comparison line; and a plurality of unidirectional dual circuits each having a cathode terminal connected to a redundant address comparison line of the plurality of redundant address comparison circuits and an anode terminal commonly connected. Terminal element and an input terminal connected to an anode terminal of the plurality of unidirectional two-terminal elements; Circuit for semiconductor memory, comprising: 2. The spare generating circuit includes an impedance input differential amplifier, one input terminal of the differential amplifier is connected to a redundant address comparison line, and the other input terminal of the differential amplifier has a first impedance. 2. The semiconductor memory redundant circuit according to claim 1, wherein the redundant circuit is connected to a reference line connected to a power supply via a third impedance having a value intermediate between the second impedance and the second impedance. 3. The redundant use detection circuit comprises an impedance input differential amplifier, one input terminal of the differential amplifier is connected to an anode terminal of a unidirectional two-terminal element, and the other input terminal of the differential amplifier. 2. The semiconductor memory redundancy circuit according to claim 1, wherein the terminal is connected to a reference line connected to a power supply via a third impedance having an intermediate value between the first impedance and the second impedance. 4. The redundant circuit of a semiconductor memory according to claim 2, wherein another power supply is connected to each of the redundant address comparison line and the reference line via a transistor that conducts in a pulsed manner. 5. The redundant circuit of a semiconductor memory according to claim 3, wherein another power supply is connected to the anode terminal and the reference line of the unidirectional two-terminal element via respective transistors that conduct in a pulsed manner. 6. The spare generating circuit comprises an impedance input differential amplifier, and one input terminal of the differential amplifier is blocked by a redundant address comparison line wired from a central memory block to a corner memory block of the semiconductor chip. The other input terminal of the differential amplifier is connected to a power supply via a third impedance having an intermediate value between the first impedance and the second impedance, which is connected via a transfer gate controlled by a selection signal. 2. The semiconductor memory redundancy circuit according to claim 1, wherein the redundancy circuit is connected to the reference line. 7. The redundant use detection circuit comprises an impedance input differential amplifier, and one input terminal of the differential amplifier is a unidirectional two terminal wired from a central memory block to a corner memory block of the semiconductor chip. The other input terminal of the differential amplifier is connected to the anode terminal of the element via a transfer gate controlled by a block selection signal.
2. The redundant circuit of a semiconductor memory according to claim 1, wherein said redundant circuit is connected to a reference line connected to a power supply via a third impedance having an intermediate value between said impedance and said second impedance.