JPH06325578A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To inhibit the peak value of the currents of the whole device at a value lower than conventional devices, and to lower stress applied to an aluminum wiring as a power supply wiring by dividing the peak value of currents at the time of read in a semiconductor storage device. CONSTITUTION:Stored data are read from memory cells MC connected to a read word line WL selected and brought into an active state, and the stored data are transmitted to bit lines RBL. One selecting line L2 in a plurality of selecting lines L2 is brought into the active state on the basis of a bit-line selecting signal not shown in the figure in a column selector 2, and transfer gates 3 connected to the selecting line L2 are turned on selectively. Signals obtained in the bit lines RBL are amplified by each sense amplifier 4, and the signals are input to tristate buffers 5 as amplifying signals. An output enable signal OE is made to rise at the time of 'H', a plurality of the buffers 5 are brought into the active state simultaneously under the control of the internal output enable signal Oe of a buffer 6 by using the output enable signal OE, and time difference is generated among output data DO1-DOi and DO(i+1) and DOn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to reduction of peak current during reading.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing the periphery of a read circuit portion of a multi-port memory having a conventional n-bit length (n is a natural number) configuration with one write port and one read port.

As shown in FIG. 1, the memory cells MC are arranged in a matrix to form the memory cell array 1.
Is configured. Each memory cell MC has a write word line and a read word line (in FIG. 4, word line WL
And the read bit line RBL and the write bit line WBL in column units.

Each read bit line RBL is connected to a sense amplifier 4 via a transfer gate 3. At this time, a plurality of (two in FIG. 4) read bit lines RBL are connected to the common sense amplifier 4 via the transfer gate 3.

There are a plurality of column selectors 2 (two in FIG. 4).
One of the (main) selection lines L2 is activated, and the transfer gate 3 whose gate is connected to the activated selection line L2 is selectively turned on.

Each of the n sense amplifiers 4 amplifies the potential of the read bit line RBL obtained via the transfer gate 3 in the ON state and outputs an amplified signal S4 to the corresponding n tristate buffers 5.

Each of the n tristate buffers 5 has an internal output enable signal oe from which an output enable signal oe (“H” enable) is obtained via the buffer 6.
To the control input section C, activation / deactivation is controlled under the control of the internal output enable signal oe, and the output data DO based on the amplified signal S4 obtained from the sense amplifier 4 in the activated state.
1 to DOn are output. It should be noted that the illustration and description of the portions that have little relation to the read circuit are omitted.

In such a structure, the read operation of the multiport memory is executed as follows.

First, the read word line R which has been activated by being selected by the read word line selection means (not shown).
Data stored in the memory cell MC connected to WL is transmitted to the read bit line RBL.

Then, the column selector 2 selects one of the plurality of selection lines L2 based on a bit line selection signal (not shown).
One select line L2 is activated and the select line L2 in the active state
The transfer gate 3 whose gate is connected to is selectively turned on.

As a result, the signal obtained from the read bit line RBL connected to the transfer gate 3 in the ON state is amplified by each sense amplifier 4 and input to the tristate buffer 5 as an amplified signal S4.

The output enable signal OE is "H".
Then, under the control of the internal output enable signal oe, the n tristate buffers 5 are activated at the same time, and the n tristate buffers 5 simultaneously output the output data DO1 to DOn.

[0013]

A semiconductor memory device, such as the multi-port memory shown in FIG. 4, which outputs a plurality of bits of read data from a plurality of data reading units (tri-state buffers 5) at once is required. , Are simultaneously read out under the control of a control signal such as the output enable signal OE (internal output enable signal oe).

Therefore, since a plurality of bits are read at the same time, the peak values of the currents at the time of reading are overlapped with each other, so that the current peak value of the entire semiconductor memory device is increased. However, there is a problem in that the stress applied to the device is increased and the reliability of the device is reduced.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device in which the peak value of the current at the time of reading is reduced.

[0016]

According to another aspect of the present invention, there is provided a semiconductor memory device having n (n ≧ 2) data read units each of which outputs output data when in an active state. Control signal giving means for giving a control signal instructing activation / deactivation of the data reading units to a part of the n data reading units, and at least when the control signal indicates an active state, the control And a delay control signal giving means for outputting a delay control signal obtained by delaying the signal for a predetermined time to another part of the n data reading units.

Preferably, as in the semiconductor memory device according to a second aspect of the invention, the control signal giving means is externally provided with the n
The delay control signal giving means is provided with a first buffer for receiving an external control signal for instructing activation / inactivation of each of the data reading units, buffering the external control signal and outputting the control signal. A second buffer is provided that receives a control signal, buffers the control signal, delays the control signal for the predetermined time, and outputs the delay control control signal.

Preferably, the semiconductor memory device according to a third aspect of the present invention is such that the control signal applying means externally supplies the n signals.
A delay control signal giving means for receiving the external control signal for instructing activation / inactivation of each of the data reading units and buffering the external control signal to output the control signal; A delay component for delaying the control signal for the predetermined time and outputting the delayed control control signal.

Preferably, as in the semiconductor memory device according to a fourth aspect, the control signal giving means is externally provided with the n.
A delay control signal giving means for receiving the external control signal for instructing activation / inactivation of each of the data reading units and buffering the external control signal to output the control signal; A delay circuit for delaying the control signal by the predetermined time and outputting the delay control control signal; and a n-th data reading section for the control signal based on an activation / deactivation instruction of the delay control signal. And a switching means for transmitting / cutting off a part of the signal.

[0020]

According to the semiconductor memory device of the present invention, a control signal for instructing activation / deactivation of the n data read sections is applied to a part of the n data read sections. A control signal applying means, and a delay control signal applying means for outputting a delay control signal obtained by delaying the control signal by a predetermined time to at least another part of the n data reading units when at least the control signal indicates an active state. Is equipped with.

Therefore, when the control signal indicates the active state, the transmission timing of the active state instruction of the control signal differs by a predetermined time between a part of n pieces of data and another part.

According to another aspect of the semiconductor memory device of the present invention, the switching means transmits / shuts off the control signal to another part of the n data reading units based on the activation / inactivation instruction of the delay control signal. Therefore, when the control signal indicates the active state, it is equivalent to outputting the delayed control signal obtained by delaying the control signal by the predetermined time to the other part of the n data reading units.

[0023]

【Example】

<First Embodiment> FIG. 1 is a circuit diagram showing the periphery of a read circuit of a multiport memory according to a first embodiment of the present invention. As shown in the figure, the output enable signal OE (“H” enable), which is an external signal, is passed through the buffer 6 as the internal output enable signal oe, and DO1 to DOi (1
It is commonly given to the control input sections C of the i number of tristate buffers 5 that output ≦ i ≦ (n−1)).

The internal output enable signal oe is shared by the control input sections C of the (n−i) tristate buffers 5 which output DO (i + 1) to DOn as the delayed internal output enable signal doe via the buffer 7. Granted to. Since the buffer 7 has the signal propagation delay time ΔT1, the delayed internal output enable signal doe is a signal obtained by delaying the internal output enable signal oe by ΔT1 time. Further, other configurations are similar to those of the conventional example shown in FIG.

In such a configuration, the multiport read operation of the first embodiment is executed as follows.

First, the read word line R which has been activated by being selected by the read word line selection means (not shown).
Data stored in the memory cell MC connected to WL is transmitted to the read bit line RBL.

Then, the column selector 2 selects one of the plurality of selection lines L2 based on a bit line selection signal (not shown).
One select line L2 is activated and the select line L2 in the active state
The transfer gate 3 whose gate is connected to is selectively turned on.

As a result, a signal obtained from the read bit line RBL connected to the transfer gate 3 in the ON state is amplified by each sense amplifier 4 and input to the tristate buffer 5 as an amplified signal S4.

The output enable signal OE is "H".
And the output enable signal OE is controlled by the internal output enable signal oe through the buffer 6 only, i
The three tri-state buffers 5 are activated at the same time, and the output data DO1 is output from each tri-state buffer 5.
~ DOi is output at the same time.

After that, the signal propagation delay time Δ of the buffer 7
After the delay of T1, the output enable signal OE passes through the buffer 6 and the buffer 7 and the delayed internal output enable signal doe
Under control of (n−i) tristate buffers 5
Are activated at the same time, and each tri-state buffer 5
Output data DO (i + 1) to DOn are output simultaneously.

In this way, the output data DO (i + 1)-
By configuring the control input section C of the tri-state buffer 5 that outputs DOn to additionally provide the delayed internal output enable signal doe obtained by delaying the internal output enable signal oe by ΔT1 time via the buffer 7,
A time difference of the signal propagation delay time ΔT1 can be provided between the output timing of the output data DO1 to DOi and the output timing of the output data DO (i + 1) to DOn.

As a result, the current peak value of the entire semiconductor memory device can be suppressed lower than before by dividing the generation timing of the current peak value during reading into two. Therefore, the stress applied to the aluminum wiring or the like serving as the power supply wiring is reduced, and the reliability of the device can be maintained at a high level.

<Second Embodiment> FIG. 2 is a circuit diagram showing the periphery of a read circuit of a multiport memory according to a second embodiment of the present invention. As shown in the figure, an output enable signal OE (“H” enable), which is an external signal, is passed through the buffer 6 as an internal output enable signal oe to DO1.
.About.DOi (1.ltoreq.i.ltoreq. (N-1)) is commonly given to the control input sections C of the i-number of tri-state buffers 5.

Then, the internal output enable signal oe is passed through the resistor 8 as the delayed internal output enable signal doe,
It is applied to the control inputs C of the (n−i) tristate buffers 5 that output DO (i + 1) to DOn. Since the resistor 8 has the signal propagation delay time ΔT2, the delayed internal output enable signal doe is a signal obtained by delaying the internal output enable signal oe by ΔT2. Further, other configurations are similar to those of the conventional example shown in FIG.

In such a configuration, the multiport read operation of the second embodiment is executed as follows.

A signal obtained from the read bit line RBL connected to the transfer gate 3 in the ON state through the same process as in the first embodiment is amplified by each sense amplifier 4 and is output as an amplified signal S4 in the tristate buffer. Enter in 5.

The output enable signal OE is "H".
And the output enable signal OE is controlled by the internal output enable signal oe through the buffer 6 only, i
The three tri-state buffers 5 are activated at the same time, and the output data DO1 is output from each tri-state buffer 5.
~ DOi is output at the same time.

After that, the signal propagation delay time ΔT2 of the resistor 8
After a delay, the output enable signal OE is activated under the control of the delayed internal output enable signal doe via the buffer 6 and the resistor 8, and the (n−i) tri-state buffers 5 are activated at the same time. Output data DO (i + 1) to DOn are output at the same time.

In this way, the output data DO (i + 1)-
By configuring the control input portion C of the tri-state buffer 5 that outputs DOn to additionally provide the delayed internal output enable signal doe obtained by delaying the internal output enable signal oe by ΔT2 time through the resistor 8, Output timing of output data DO1 to DOi and output data D
A time difference of signal propagation delay time ΔT2 can be provided between the output timing of O (i + 1) to DOn.

As a result, the current peak value of the entire semiconductor memory device can be suppressed lower than before by dividing the generation timing of the current peak value during reading into two. Therefore, similarly to the first embodiment, the stress applied to the aluminum wiring or the like which is the power supply wiring is reduced, and the reliability of the device can be maintained at a high level.

<Third Embodiment> FIG. 3 is a circuit diagram showing the periphery of a read circuit of a multiport memory according to a third embodiment of the present invention. As shown in the figure, an output enable signal OE (“H” enable), which is an external signal, is passed through the buffer 6 as an internal output enable signal oe to DO1.
.About.DOi (1.ltoreq.i.ltoreq. (N-1)) is commonly given to the control input sections C of the i-number of tri-state buffers 5.

Further, the internal output enable signal oe is
Via the CMOS transfer gate 10, DO (i +
1) to DOn are commonly given to the control input units C of the (n−i) tristate buffers 5.

The internal output enable signal oe is also transmitted to the delay circuit 12. The delay circuit 12 has a signal propagation delay time ΔT3, and applies its output as a delayed internal output enable signal doe to the NMOS gate of the CMOS transfer gate 10 and, via the inverter 11, the PMOS gate and the NMOS gate of the CMOS transfer gate 10. It is applied to the gate of the transistor 9. The n tristate buffers 5 are connected to the control input unit C.
When a "H" signal is applied to the
When the signal of is given, it becomes inactive.

On the other hand, output data DO (i + 1) to DOn
The control input line 13 connected to the control input section C of the tri-state buffer 5 for outputting the signal is connected to the ground level via the NMOS transistor 9. Since the other configurations are the same as those of the conventional example shown in FIG. 4, the description thereof will be omitted.

In such a configuration, the multiport read operation of the third embodiment is executed as follows.

A signal obtained from the read bit line RBL connected to the transfer gate 3 in the ON state is amplified by each sense amplifier 4 through the same process as in the first and second embodiments, and the amplified signal S4 is obtained. Input to the tri-state buffer 5.

The output enable signal OE is "H".
And the output enable signal OE is controlled by the internal output enable signal oe through the buffer 6 only, i
The three tri-state buffers 5 are activated at the same time, and the output data DO1 is output from each tri-state buffer 5.
~ DOi is output at the same time.

At this moment, since the delayed internal output enable signal doe, which is the output signal of the delay circuit 12, is still "L", the CMOS transfer gate 10 is turned off and the NMO is turned on.
The S transistor 9 is turned on, and the internal input enable signal oe is not transmitted to the control input line 13 and the control input line 1
3 is fixed to the “L” level, and the output data DO (i +
The (ni) tristate buffers 5 that output 1) to DOn remain in the inactive state.

Thereafter, the delayed internal output enable signal doe changes to "H" with a delay of the signal propagation delay time ΔT3 of the delay circuit 12. As a result, the CMOS transfer gate 10 is turned on and the NMOS transistor 9 is turned off, so that the internal output enable signal oe of "H" is transmitted to the control input line 13 and "L" of the control input line 13 is transmitted.
When the level fixing is released, the control input line 13 becomes “H”, and the (n−i) tri-state buffers 5 that output the output data DO (i + 1) to DOn are activated at the same time. Output data DO (i + 1) to DOn are simultaneously output from the tri-state buffer 5. That is, when the internal output enable signal oe is “H”, the control signal line 13 is transferred via the transfer gate 10.
The internal output enable signal oe obtained at the same time is the internal output enable signal oe before passing through the transfer gate 10.
Is substantially delayed by ΔT3.

Thus, the output data DO (i + 1)-
The control input section C of the tri-state buffer 5 which outputs DOn has a CM whose ON / OFF is controlled by the delay circuit 12.
By configuring the OS transfer gate 10 to provide the internal output enable signal oe through the extra, signal propagation between the output timing of the output data DO1 to DOi and the output timing of the output data DO (i + 1) to DOn. It is possible to have a time difference of the delay time ΔT3.

As a result, the current peak value of the entire semiconductor memory device can be suppressed lower than before by dividing the generation timing of the current peak value during reading into two. Therefore, as in the first and second embodiments, the stress applied to the aluminum wiring or the like which is the power supply wiring is reduced,
The reliability of the device can be maintained at a high level.

<Others> In the first to third embodiments, as means for delaying the output enable signal OE (internal output enable signal oe), the CMOS controlled by the buffer 7, the resistor 8 and the delay circuit 12 is turned on and off. Although the transfer gates 10 are used, the present invention is not limited to this.

Further, in the first to third embodiments, the output timing of the plurality of output data DO is divided into two by providing one delay means. However, the output timing is divided into two by providing two or more delay means. Output timing of data DO is 3
It can be divided into the above. By increasing the number of divisions of the output timing of the output data DO, the peak current at the time of reading can be further reduced, which is effective for a RAM or the like having a large read bit length.

Further, the semiconductor memory devices taken up in the first to third embodiments are the multi-port memories of the write port 1 and the read port 1, but the present invention is not limited to this, and the multi-port memory having other port configurations. The memory may be a memory having a single port configuration. That is, the present invention can be applied to any semiconductor memory device as long as it has a plurality of data reading units corresponding to the tri-state buffer 5 and simultaneously reads a plurality of (bit) data. it can.

[0055]

As described above, according to the semiconductor memory device of the first to fourth aspects of the present invention, the control signal for instructing activation / inactivation of the n data read units is
a control signal giving means for giving a part of the n data reading sections, and a delay control signal obtained by delaying the control signal by a predetermined time when at least the control signal indicates an active state,
By providing the delay control signal giving means for outputting the data to the other part of the individual data reading units, when the control signal indicates the active state, it is possible to connect the part of the n data and the other part. The timing of transmitting the active state instruction of the control signal can be shifted by a predetermined time.

As a result, by dividing the peak value of the current at the time of reading, the current peak value of the entire semiconductor memory device can be suppressed to a lower value than before.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the periphery of a read circuit of a multiport memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing the periphery of a read circuit of a multiport memory which is a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing the periphery of a read circuit of a multiport memory which is a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a read circuit peripheral of a conventional multi-port memory.

[Description of Reference Signs] 1 memory cell array 4 sense amplifier 5 tri-state buffer 6 buffer 7 buffer 8 resistance 10 CMOS transfer gate 12 delay circuit OE output enable signal oe internal output enable signal doe delayed internal output enable signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G11C 11/34 353 E

Claims (4)

[Claims] 1. A semiconductor memory device having n (n ≧ 2) data read units each of which outputs output data in an active state, wherein a control signal for instructing activation / deactivation of the n data read units is provided. A control signal giving means for giving a part of the n data reading sections, and at least a delay control signal obtained by delaying the control signal by a predetermined time when the control signal indicates an active state. And a delay control signal giving means for outputting the data to another part of the data reading section. 2. The control signal applying means receives an external control signal for instructing activation / deactivation of the n data reading units from the outside, buffers the external control signal, and outputs the control signal. A second buffer, comprising: a first buffer, wherein the delay control signal giving means receives the control signal, buffers the control signal, delays the control signal for the predetermined time, and outputs the delay control control signal. The semiconductor memory device according to claim 1, further comprising: 3. The control signal applying means receives an external control signal for instructing activation / deactivation of the n data reading units from the outside, buffers the external control signal, and outputs the control signal. 2. The semiconductor memory device according to claim 1, further comprising a buffer, wherein the delay control signal applying unit includes a resistance component that receives the control signal, delays the control signal for the predetermined time, and outputs the delay control control signal. 4. The control signal giving means receives an external control signal for instructing activation / deactivation of the n data reading units from the outside, buffers the external control signal, and outputs the control signal. A delay circuit for receiving the control signal, delaying the control signal by the predetermined time, and outputting the delay control control signal; and a delay control signal activation / deactivation instruction. 2. The semiconductor memory device according to claim 1, further comprising switching means for transmitting / blocking the control signal to / from another part of the n number of data reading units.