JPH06324883A - Cpu simulator - Google Patents

Abstract

PURPOSE:To convert an instruction code into the instruction sequence of a host CPU for simulation correctly without being affected by the mixture of data unused as the instruction code in an address area referred as the instruction code by a target CPU even when it occurs and to simulate the operation of the target CPU on the host CPU without generating a trouble. CONSTITUTION:At a pre-stage to simulate the operation of the target CPU on the host CPU, a conversion means 2 interprets binary data 1 in an address area referred as the instruction code by the target CPU as the instruction code setting all the addresses 0, 1, 2,... as bases where the instruction code can be arranged, and converts an interpreted instruction code into simulation instruction sequences 3-1, 3-2, 3-3,... comprised of the instruction sequence of the host CPU which simulates the instruction code and the instruction sequence which transfers control to the instruction sequence of the host CPU which performs the simulation of the instruction code executed by the target CPU following the interpreted instruction code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for simulating the operation of a target CPU on a host CPU.

[0002]

2. Description of the Related Art A program developed for a target CPU (referred to as a target program) can be debugged or performance evaluated before completion of a target machine including a target CPU or before debugging and performance evaluation on the target machine. As a method of executing the target CPU, the target CP for the target program on the CPU simulator including the host CPU which is a CPU different from the target CPU
There is a method to simulate the behavior of U.
It is roughly divided into an interpreter method that sequentially interprets and executes the source program for the target CPU and an object simulation method that sequentially interprets and executes the machine language code for the target CPU (for example, edited by the Institute of Electronics, Information and Communication Engineers Handbook Committee, Ohmsha Co., Ltd., issued March 30, 1988, first edition "Electronic Information and Communication Handbook Second Volume", page 1857, 5.3 "Simulator").

Here, the interpreter method is a method for simulating a source program for a target CPU while directly interpreting it.
The object simulation method compiles or assembles a source program of a target program prior to simulation to convert it into a machine language level instruction code of the target CPU,
This instruction code is simulated.

The object simulation method takes time to generate machine language level instructions of the target CPU, but the simulation execution time is faster than that of the interpreter method, so that a short simulation time is required. Uses an object simulation method. Needless to say, if the target program already exists at the machine language level, no compilation or assembly is necessary.

In an object simulation type CPU simulator, for example, Japanese Unexamined Patent Publication No.
As disclosed in Japanese Patent No. 250122, the target CP
The U instruction code was interpreted on the host CPU one by one at the time of execution, and the simulation was advanced.

As described above, the object simulator type CPU simulator is superior to the interpreter type CPU in simulation speed. However, as in the conventional case, the instruction code of the target CPU is changed to the host CPU.
In the above configuration in which each instruction is interpreted at the time of execution, the time required for the interpretation becomes an overhead at the time of simulation.

Therefore, one of the inventors of the present invention is a novel CPU simulator (hereinafter referred to as a previously proposed CPU) that enables high-speed simulation by eliminating the need to interpret the instruction code of the target CPU when executing the simulation.
Patent application filed on December 29, 1992 (reference number N0002S, title of invention; CPU simulation method and CPU simulator), and patent application filed on February 26, 1993 (reference number N000).
4S, title of invention; CPU simulation method and CPU simulator).

In this already proposed CPU simulator, in a CPU simulator that simulates the operation of the target CPU on the host CPU, machine code level instruction codes of the target program are collectively interpreted in advance,
It is expressed by a combination of assembler language level or machine language level instruction codes of the host CPU that simulates each instruction code, or a set of simulation function calls that call a simulation function that can be executed by the host CPU that simulates each instruction code. A simulation program is generated, and the generated simulation program is executed by the host CPU. The target CP at the time of executing the simulation.
Since it is not necessary to interpret the U instruction code, high-speed simulation is possible accordingly.

[0009]

By the way, the address area on the target program referred to by the target CPU as an instruction code is, for example, an area starting from address 0 as shown by reference character M (storage of one address). If the size is 1 byte), the target CPU
Host CPU for simulation of instruction code
Is generally converted as follows.

First, it is checked whether or not the 1-byte instruction code of the target CPU is constituted only by the binary data stored in the address 0 with the address 0 as a starting point. Converted to the instruction sequence of
Address 1 is the next base point. If one binary code stored at address 0 does not constitute one instruction code, the same determination is made with 2 bytes including the binary data stored at the next address 1, and the binary data of this 2 bytes is used. If the 2-byte instruction code of the target CPU is configured, the instruction code is converted into the instruction string of the host CPU, and the address 3 is set as the next base point. Hereafter, similarly,
The binary data in the address area M is sequentially interpreted and converted in the order in which the instruction code of the target CPU appears.

According to the above method, when only the instruction code of the target CPU is stored in the address area M as shown in FIG. 5A, the instruction code (1 ), The instruction code (2), and the instruction code (3) can be correctly converted into the instruction sequence of the host CPU, but as shown in FIG. 5B, the target CPU is, for example, address 2 in the address area M. When the binary data X that is not used as an instruction code is mixed, the binary data stored in the address 2 and, for example, the next address 3 in the processing starting from the address 2 is a certain 2-byte instruction of the target CPU. If the code is constructed, the next base point will be the address 4, so the position of the instruction code to be interpreted after that will shift and the instruction code to be simulated will be converted. It is not, and can not be simulated on the host CPU.

The present invention solves such a problem, and its object is to include binary data which the target CPU does not use as an instruction code in the address area which the target CPU refers to as an instruction code. Even if it is not affected by it, each instruction code of the target CPU existing in the address area is transferred to the host CP.
It is intended that the operation of the target CPU can be simulated on the host CPU without any trouble by enabling the correct conversion into the U instruction sequence.

[0013]

In order to achieve the above-mentioned object, the present invention is a CPU simulator for simulating the operation of a target CPU to be simulated on a host CPU, and the operation of the target CPU on the host CPU. Before simulating
In a CPU simulator configured to collectively interpret machine language level instruction codes of a target CPU and generate a sequence of instructions to be executed on a host CPU in order to simulate the operation of the target CPU, the target CPU serves as an instruction code. The binary data of the address area to be referred to is interpreted as an instruction code with all addresses where instruction codes can be arranged as a base point, and the interpreted instruction code of the target CPU is interpreted as an instruction string of the host CPU simulating the instruction code. After the instruction code, a conversion means for converting the instruction code executed by the target CPU into a simulation instruction string composed of an instruction string for transferring control to the instruction string of the host CPU for simulating the instruction code is provided.

Further, the converting means, as one configuration example thereof, generates an address conversion table having each address of the simulation instruction sequence as a value using each address in which the instruction code can be arranged in the address area as an index. The target CPU executes next to the interpreted instruction code as an instruction sequence for transferring control to the instruction sequence of the host CPU that simulates the instruction code executed by the target CPU next to the interpreted instruction code in the simulation instruction sequence. The instruction sequence is branched to the instruction sequence of the host CPU at the address destination stored in the address conversion table corresponding to the address of the instruction code.

[0015]

In the CPU simulator of the present invention, before the simulation of the operation of the target CPU on the host CPU, the conversion means arranges the binary data in the address area referred to by the target CPU as the instruction code in the instruction code. A host CP that interprets an instruction code from all possible addresses and simulates the interpreted instruction code of the target CPU.
It is converted into a simulation instruction string composed of a U instruction string and an instruction string that transfers control to the instruction string of the host CPU that simulates the instruction code executed by the target CPU after the interpreted instruction code.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention. Binary data 1 of an address area in a target program referred to by a target CPU as an instruction code.
From the CPU simulator conversion means 2 to the host CP
The generation and output of the simulation code 3 including the U simulation instruction sequence and the address conversion table 4 indicating the correspondence between the address of the instruction code on the target CPU and the address of the simulation instruction sequence on the host CPU are shown. ing.

In the figure, each address 0, 1, 2, ..., N shown in the binary data 1 (the storage size of each address is, for example, 1 byte) is an address where the instruction code of the target CPU can be arranged. Is shown. In the example shown,
A 2-byte instruction code 1-1 is placed at address 0, a 2-byte instruction code 1-2 is placed at address 2, and a 1-byte instruction code 1-3 is placed at address n. However, for example, it is possible to arrange a 1-byte instruction code at the 0th address and a 2-byte instruction code at the 1st address. In this sense, each address 0,
Any of 1, 2, ..., N is an address where the instruction code of the target CPU can be arranged.

The conversion means 2 interprets the binary data 1 into an instruction code based on all addresses in which the instruction code can be arranged, and generates a simulation instruction string of the host CPU for each interpreted instruction code of the target CPU. To do. That is, the conversion means 2 interprets the instruction code starting from the address 0 of the binary data 1 to generate the simulation instruction sequence 3-1 and interprets the instruction code starting from the address 1 to generate the simulation instruction sequence 3-2. , The simulation instruction sequence 3-3 is generated by interpreting the instruction code starting from the address 2, and the same process is performed thereafter, and the instruction code starting from the address n is finally interpreted to generate the simulation instruction sequence 3-4. .

If there is a 2-byte instruction code 1-1 starting from address 0 of binary data 1 as in the illustrated example, the instruction code 1-1 itself is the instruction code starting from address 0. The instruction string of the host CPU that is interpreted and simulates the instruction code 1-1 and the instruction code (for example, instruction code 1-2) that the target CPU executes next to the interpreted instruction code 1-1 are simulated. Simulation instruction sequence 3-1 composed of an instruction sequence for transferring control to the instruction sequence of the host CPU
Is generated. Similarly, in the conversion process using the start addresses of the other instruction codes 1-2 and 1-3 actually existing in the binary data 1 as the base points, the actually existing instruction codes 1-2 and 1-3 themselves are interpreted. And the instruction code 1-
Control is transferred to the instruction sequence of the host CPU simulating 2, 1-3 and the instruction sequence of the host CPU simulating the instruction code executed by the target CPU next to the interpreted instruction code 1-2, 1-3. Simulation instruction sequences 3-3 and 3-4 composed of an instruction sequence are generated. In addition, it added to the simulation code 3.
Address 0 and the like indicate addresses on the host CPU where the simulation instruction strings 3-1 and the like are placed.

Here, the target C is next to the interpreted instruction code included in the simulation instruction sequence 3-1 or the like.
In the present embodiment, the instruction sequence for transferring control to the instruction sequence of the host CPU that simulates the instruction code executed by the PU is translated using the address of the instruction code executed by the target CPU next to the interpreted instruction code as an index. The instruction sequence branches to the simulation instruction sequence of the simulation code 3 indicated by the address obtained when the table 4 is searched.

On the other hand, in the conversion process which uses an address other than the start address of the actually existing instruction code as the base point, such as the 1st address and the 3rd address of the binary data 1, it is interpreted as the following two instruction codes.

One of them is a case where a certain instruction code defined by the target CPU is accidentally constructed by binary data after the base point address and is interpreted as such an instruction code. Even in this case,
The conversion means 2 is composed of an instruction sequence of the host CPU that simulates the instruction code and an instruction sequence that transfers control to the instruction sequence of the host CPU that simulates the instruction code executed by the target CPU next to the instruction code. Generate a simulation instruction sequence. this is,
This is to enable the operation of the target CPU when control is transferred to such an illegal address to be simulated.

The other one is a case where the binary data after the base address does not constitute an instruction code defined by the target CPU and is therefore interpreted as an undefined instruction code. In such a case, in the conversion means 2,
Corresponding to the interpreted undefined instruction code, for example, a simulation instruction sequence including an instruction sequence of the host CPU that outputs an error message indicating that the undefined instruction code has been executed is generated. Further, when an undefined instruction code is about to be executed, and if some sort of exception processing is to be executed on the target CPU, the exception processing is performed corresponding to the interpreted undefined instruction code. To generate a simulation instruction sequence including the instruction sequence of the host CPU simulating.

The conversion means 2 also generates the address conversion table 4 at the same time as generating the simulation code 3 composed of the above-mentioned simulation instruction sequence 3-1 and the like. The address conversion table 4 is a set of entries 4-1 and the like having each address of the binary data 1 of the target CPU as an index and each address of the simulation instruction sequence 3-1 and the like as a value. Therefore, in the illustrated case, the address 0 of the binary data 1 of the target CPU has the address Address0 of the simulation instruction sequence 3-1 and the entry 4-1 and the address Address1 of the simulation instruction sequence 3-2 for the address 1 of the target CPU. Entry 4-2, 2
Address of simulation instruction sequence 3-3 for address
The entry 4-4 having the address Address n of the simulation instruction sequence 3-4 is generated for the addresses 4-3, ..., N having the Address 2.

When the generation of the simulation code 3 and the address conversion table 4 as described above is completed, the actual simulation becomes possible. Execution of the simulation command sequence on the host CPU in this embodiment is performed by the patent application (reference number N0004S, filed on February 26, 1993).
Title of invention: CPU simulation method and CPU
(Simulator), the procedure is similar to that of the CPU simulator that employs the address conversion table.

That is, if the host CPU starts execution from the simulation instruction sequence 3-1 of the simulation code 3, for example, the instruction sequence of the host CPU simulating the instruction code 1-1 in the instruction sequence 3-1. To simulate the operation of the instruction code 1-1, and then in the instruction sequence 3-1
A host CPU that simulates the instruction code 1-2 executed by the target CPU after the instruction code 1-1
By executing the instruction sequence for transferring the control to the instruction sequence No. 2, the entry 4-3 is acquired from the address conversion table 4 using the address 2 of the instruction code 1-2 on the target CPU as an index, and the entry Address in Addres
The control is transferred to the simulation instruction sequence 3-3 indicated by s2. Similarly, the operation of each instruction code in the binary data 1 is simulated by executing each simulation instruction string, and the operation is repeatedly transferred to the simulation instruction string corresponding to the instruction code next to the simulated instruction code. , Simulate the operation of the target CPU on the host CPU.

FIG. 2 is a block diagram showing a more specific configuration example of the CPU simulator based on the above-mentioned principle.
The CPU simulator 5 of this embodiment converts a target program 6 into a simulation function call sequence 53 and generates an address conversion table 56, a simulation function call sequence 53, a simulation function group 54, a register simulator 55 and an address. Memory 51 for storing conversion table 56
And a host CPU 52 that executes the simulation function call sequence 53 and the like.

The target program 6 is the target C
A target CP that is a program developed for PU
The binary data 60 in the address area referred to by U as an instruction code includes instruction code 6-1 to 6-n at the machine language level of the target CPU. here,
The first instruction code 6-1 is a 2-byte instruction, and the 0th address is placed at the head on the target CPU, the next instruction code 6-2 is placed at the 2nd address, and the last instruction code 6
-N is located at address n.

The simulation function call sequence 53 is
The conversion means 50 processes and generates the target program 6, and corresponds to the simulation code 3 in FIG. The simulation function call sequence 53 is a simulation function call 53-expressed at the assembler language level or the machine language level of the host CPU 52.
1 to 53-n. Here, the simulation function call 53-1 at the head is the binary data 60.
Converted instruction code 6-1 starting from address 0 of
The next simulation function call 53-2 is an instruction code starting from the address 1 of the binary data 60 (a certain instruction code of the target CPU or an undefined instruction code).
Which is converted from the following simulation function call 5
3-3 is a conversion of the instruction code 6-2 starting from the address 2 of the binary data 60, and the last simulation function call 53-n is a conversion of the instruction code 6-n. In the address space of the host CPU 52, The addresses are stored in the memory 51 at positions starting from addresses A, B, C, ..., N, respectively.

The address conversion table 56 is composed of the conversion means 5
0 is generated by processing the target program 6. For example, as shown in FIG.
, N of each of the binary data 60 of the above is used as an index, and the simulation function calls 53-1 and 53-corresponding to the instruction codes starting from the respective addresses are made.
, 53-n on the memory 51 are held.

The simulation function group 54 is a set of simulation functions 54-0 to 54-m. Of these, the simulation functions 54-1 to 54-m have a one-to-one correspondence with each instruction code at the machine language level of the target CPU, and simulate the instruction code of the corresponding target CPU. The simulation function 54-0 is a function for simulating an instruction code interpreted as an undefined instruction code. These simulation functions 54-0 to 54-m are described in C language, for example.

The register simulator 55 is a collection of registers which are associated with the registers to be simulated on the target CPU in a one-to-one correspondence.
52 refers to and updates this register simulator 55 to simulate a register on the target CPU.

In the embodiment shown in FIG. 2, the CPU simulator 5 uses the target C for the target program 6.
When executing the simulation of the operation of the PU, the conversion means 50 is activated prior to the execution of the simulation.

As shown in FIG. 4, the converting means 50 is composed of an instruction code reading section 501, an instruction interpreting section 502, an instruction converting section 503, and output sections 504 and 505.

The instruction code reading unit 501 sequentially reads the binary data 60 in the target program 6 shown in FIG. 2 stored in a memory, a file, or the like (not shown), and uses all the addresses where the instruction codes can be arranged as base points for the instruction codes. The interpreted instruction code of the target CPU is transmitted to the instruction interpretation unit 502.

The instruction interpretation unit 502 interprets what kind of instruction the instruction code transmitted from the instruction code reading unit 501 is, and determines the type of instruction, the register used for the instruction, the memory address, the constant, and the like. The determination result is transmitted to the command conversion unit 503.

The instruction conversion unit 503 determines the target CPU based on the determination result transmitted from the instruction interpretation unit 502.
A simulation function call for calling a simulation function for simulating a machine language level instruction code is generated in the assembler language or machine language level of the host CPU 52.

For example, the target CPU is an Intel 16-bit processor 8086, and the host CPU 5
When 2 is a 32-bit processor R3000 manufactured by MIPS, the instruction conversion unit 503 generates a simulation function call that calls an instruction code of 8086 and calls a simulation function that can be executed by R3000.

The following is an example of the 8086 instruction, the R3000 simulation function call, and the simulation function. The 8086 instruction and the R3000 simulation function call are written in assembler notation R30.
The simulation function of 00 is shown in C language.

○ 8086 instruction MOV AX, 0x1000 / * 3-byte instruction * / ○ Simulation function call li a0, AX / * AX is a constant representing a register * / li a1, 0x1000 jal F_MOV / * Simulation function call * / nop / * nop for filling the branch delay slot * / j v0 nop / * nop for filling the branch delay slot * / ○ Simulation function F_MOV (reg, imm) int reg; short imm; {PC + = 3; Reg [ reg] = imm; / * Reg [] is a variable holding the register information * / return (AddrTbl [(Reg [CS] << 4) + PC]); / * AddrTbl [] is the address conversion table 56 * /}

Return (AddrTbl [(Reg [CS] << 4) + PC]) in the above simulation function is the address of the instruction to be executed at 8086 (Reg [C
S] << 4) + PC is used as an index to refer to the address conversion table 56 to obtain the address on the host CPU 52 corresponding to the index and return it as a return value. At the simulation function calling side, j v0 is executed. As a result, the process branches to the portion of the simulation function call sequence 53 corresponding to the instruction to be simulated next.

When the instruction source code to be converted is an instruction code whose branch destination address is unknown until execution such as register indirect branching or register indirect subroutine calling, the instruction converting unit 503 executes the simulation on the target CPU. The address in the simulation function call sequence 53 to be branched is obtained from the branch destination address and the contents of the address conversion table 56, and is converted into a simulation function call that calls a simulation function including an instruction sequence that transfers control to the address. Below, an example of the register indirect branch instruction of 8086, an example of the simulation function call of R3000 after the conversion, and an example of the simulation function of R3000 called by this are shown.

○ 8086 instruction JMP [BX] / * 2-byte instruction * / ○ Simulation function call lia0, BX / * BX is a constant representing a register * / jal F_JMP_R / * Simulation function call * / nop / * branch Nop * / j v0 / * v0 for filling the delay slot is the return value of F_JMP_R () * / nop / * nop * / for the purpose of filling the branch delay slot Simulation function F_JMP_R (reg) int reg; {PC = Reg [Reg]; return (AddrTbl [(Reg [CS] << 4) + PC]); / * AddrTbl [] is the address conversion table 56 * /}

That is, in the case of JMP [BX], the simulation function F is used with the constant representing the register BX as an argument.
Generate a simulation function call that calls _JMP_R. In the simulation function F_JMP_R, PC = Reg [reg]; is used to refer to the value (Reg [reg]) of the register holding the address of the branch destination on the 8086 from the register simulator 55 and PC in the register simulator 55. Update the value of return (AddrT
bl [(Reg [CS] << 4) + PC]); This is because the address of the instruction to be executed in 8086 is
Since it is specified by the segment register (CS in this case) and PC, (Reg [CS] << 4) + PC causes 808
The address on 6 is calculated, the address conversion table 56 is referenced using this as an index, and the obtained address is returned as a return value. On the simulation function call side, by executing j v0, the process branches to the part of the simulation function call sequence 53 corresponding to the instruction to be simulated next.

The instruction conversion unit 503 also converts a branch instruction code whose branch destination is fixed before execution. In this embodiment, the instruction conversion unit 503 corresponds to the address of the instruction code of the target CPU on the target CPU. Since the address of the simulation function call on the host CPU can be obtained by the address conversion table 56, the simulation is performed by the method exemplified below.

○ 8086 instruction JMP 0x2000 / * 2-byte instruction * / ○ Simulation function call lia0, 0x2000 jal F_JMP / * Simulation function call * / nop / * nop * / j v0 / to fill the branch delay slot * V0 is the return value of F_JMP () * / nop / * nop for filling the branch delay slot * / ○ Simulation function F_JMP (addr) unsigned short reg; {PC = addr; return (AddrTbl [(Reg [CS] < <4) + PC]); / * AddrTbl [] is the address conversion table 56 * /}

When the instruction conversion unit 503 generates the simulation function call, the instruction conversion unit 503 transmits the generated simulation function call to the output unit 504, and the output unit 50.
4 sequentially stores this in the memory 51 of FIG. 2 or an external storage device (not shown).

The instruction conversion unit 503 converts the instruction code from each address of the binary data 60 of the target program 6 as a base point, and outputs the address conversion table 56 to the memory 51 or an external storage device (not shown) through the output unit 505. 1 entry is output. This allows
When the conversion with all the addresses of the binary data 60 of the target program 6 as the base point is completed, each address of the binary data 60 of the target program 6, 0, 1, 2, ...
Simulation function call 53-1, 5 corresponding to the instruction code starting from each address with n as an index
Addresses A, B, C, ..., N on the memory 51 of 3-2, 53-3, ..., 53-n are stored in the memory 51 or an external storage device (not shown) as shown in FIG. Is generated. When the address conversion table 56 is generated in the external storage device, it is necessary to read the address conversion table 56 from the external storage device into the memory 51 before starting the simulation.

Next, the operation of the embodiment shown in FIG. 2 during the simulation will be described.

When the CPU simulator 5 receives an instruction to start the execution of the simulation from the input means (not shown), when the simulation function call sequence 53 is generated at the machine language level, the host CPU 52 calls the simulation function on the memory 51. Execute column 53.

The host CPU 52 first executes a simulation function call corresponding to the execution start address of the target program 6. Therefore, assuming that the simulation function call 53-1 is a simulation function call corresponding to the execution start address of the target program 6, the host CPU 52 first executes the simulation function call 53-1. Thereby, for example, the simulation function 54-1 is called and executed, and the instruction code 6-1 is simulated. In addition, in this function, the following processes are generally performed. (A) Update the PC value in the register simulator 55. (B) Refer to and update the contents of the register and memory specified by the argument and perform the necessary processing. (C) If necessary, change PSW. (D) In the case of a branch instruction, the branch destination address on the host CPU is obtained. (E) Return the return value.

When the execution of the simulation function 54-1 is completed, control returns to the calling simulation function call 53-1 once in this embodiment, and branches to the address indicated by the return value. As a result, control is transferred to the simulation function call 53-3 in the simulation function call sequence 53 corresponding to the instruction to be simulated next.

Hereinafter, by repeating the above-mentioned operation, the corresponding simulation functions 54-1 to 54-m in the simulation function group 54 are called to simulate the operation of the target CPU according to the target program 6 on the host CPU 52. To be done.

In executing the simulation,
Even if the control shifts to an address other than the start address of the original instruction code in the binary data 60 of the target program 6, for example, the control shifts to the first address, referring to the address conversion table 56, the simulation function call 53-2 is set there. Therefore, this simulation function call 53-2 is executed. Therefore,
If the instruction code interpreted from the first address is a certain instruction code defined in the target CPU, the simulation function call 53-2 is generated so as to call the simulation function that simulates the instruction code. Therefore, the operation of the instruction code is simulated. If it is an undefined instruction code, the simulation function call 53-2 is generated so as to call the simulation function 54-0 that performs the simulation processing at the time of execution of the undefined instruction. The behavior will be simulated. As described above, according to this embodiment, it is possible to simulate the operation of the target CPU when the target program 6 transfers control to an illegal address.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and various other additions and modifications can be made. For example, although the conversion means is provided separately from the host CPU in the above embodiment, the conversion means may be realized by the function of the host CPU. Further, it is possible to do the following.

Instead of converting the instruction code of the target CPU into a simulation function call, as in the patent application (reference number N0002S, title of invention; CPU simulation method and CPU simulator) filed on December 29, 1992, Each instruction code is converted into a code expressed by a combination of assembler language level or machine language level instruction codes of the host CPU.

The instruction code of the target CPU is
Similar to the patent application (reference number N0004S, title of invention; CPU simulation method and CPU simulator) filed on February 26, 2014, conversion to a simulation function call composed of a constant number of bytes of the instruction code. . In such a configuration, since the address of the instruction string of the host CPU that simulates the instruction code executed by the target CPU after a certain instruction code can be calculated, the address conversion table becomes unnecessary.

[0059]

As described above, according to the CPU simulator of the present invention, the following effects can be obtained.

Since the binary data in the address area referred to by the target CPU as an instruction code is converted into a simulation instruction sequence by interpreting the binary data in the address area as an instruction code based on all the addresses where instruction codes can be arranged, the target CPU is included in the address area. Even if there is a mixture of binary data that is not used as an instruction code, the instruction code to be simulated can be surely converted into a simulation instruction string regardless of such binary data. Then, as the simulation instruction sequence, there are an instruction sequence of the host CPU that simulates the interpreted instruction code of the target CPU and an instruction sequence of the host CPU that simulates the instruction code executed by the target CPU next to the interpreted instruction code. Since the simulation instruction sequence composed of the instruction sequence for transferring the control is generated, in the normal case, it is generated corresponding to the instruction code interpreted based on the binary data that the target CPU does not use as the instruction code. The control is not transferred to the simulation command sequence, and the operation of the target CPU can be simulated on the host CPU without any trouble.

When the target program to be simulated transfers control to an illegal address such as an address of binary data that is not used as an instruction or an address of a byte in the middle of an instruction code of several bytes, the present invention makes such an illegal address. Since the instruction code is also interpreted with respect to the address as the base point to generate the simulation instruction sequence, there is also an effect that the operation when the target CPU transfers control to an illegal address can be simulated.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of a CPU simulator of the present invention.

FIG. 3 is a diagram showing an example of contents of an address conversion table.

FIG. 4 is a block diagram showing a configuration example of a conversion unit.

FIG. 5 is an explanatory diagram of a problem that occurs when binary data that the target CPU does not use as an instruction code is mixed in binary data of an address area that the target CPU refers to as an instruction code.

[Explanation of symbols]

1 ... Binary data in address area referred to by target CPU as instruction code 1-1 to 1-3 ... Instruction code 2 ... Conversion means 3 ... Simulation code executed by host CPU 3-1 to 3-4 ... Simulation instruction string 4 ... Address conversion table 4-1 to 4-4 ... Entry

Claims (2)

[Claims] 1. A CPU simulator for simulating an operation of a target CPU to be simulated on a host CPU, which is a stage before simulating an operation of the target CPU on the host CPU.
In a CPU simulator configured to collectively interpret machine language level instruction codes of a target CPU and generate a sequence of instructions to be executed on a host CPU in order to simulate the operation of the target CPU, the target CPU serves as an instruction code. The binary data of the address area to be referred to is interpreted as an instruction code with all addresses where instruction codes can be arranged as a base point, and the interpreted instruction code of the target CPU is interpreted as an instruction string of the host CPU simulating the instruction code. And a conversion means for converting into a simulation instruction sequence composed of an instruction sequence for transferring control to the instruction sequence of the host CPU for simulating the instruction code executed by the target CPU Simulator. 2. The conversion means generates an address conversion table having, as an index, each address of a simulation instruction sequence with each address at which an instruction code can be arranged in the address area as an index, and in the simulation instruction sequence, Target CP next to the interpreted instruction code
U is stored in the address conversion table corresponding to the address of the instruction code executed by the target CPU next to the interpreted instruction code, as an instruction string for transferring control to the instruction string of the host CPU that simulates the instruction code executed by U 2. The CPU according to claim 1, having a configuration for generating an instruction sequence that branches to an instruction sequence of the host CPU at the specified address destination.
Simulator.