JPH06317811A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To improve the characteristic of a p channel TFT and to form a high-speed circuit by oxidizing a non-single crystal silicon thin film on an insulat ing substrate to form the channel region of the (p) channel and (n) channel thin-film transistors. CONSTITUTION:Non-single crystal silicon thin films 4P and 4N are heat-treated in an oxidizing atmosphere to reduce the defects in a polycrystal silicon thin film to form the channel region of a TFT. In this case, the (n) channel TFT has an optimum content of oxide, and the TFT characteristic is conversely deteriorated above that content. Meanwhile, the characteristic of the (p) channel TFT is further improved even if the (n) channel TFT is oxidized in the larger amt. than optimum. Further, the oxide content of the non-single crystal silicon thin film 4P constituting the (p) channel is made higher than that of the non- single crystal silicon thin film constituting the (p)channel TFT. Consequently, the defects of the non-single crystal silicon thin films 4N and 4P are reduced in the (p) channel TFT and (u)channel TFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a driver monolithic liquid crystal display panel, an image sensor, and a three-dimensional IC, which includes an n-channel thin film transistor and a p-channel thin film transistor.

[0002]

2. Description of the Related Art In order to improve the performance of a CMOS circuit comprising a semiconductor device having the above-mentioned p-channel thin film transistor (hereinafter referred to as TFT) and n-channel TFT, both the n-channel TFT and the p-channel TFT are moved. The degree (μ) is high and the threshold voltage (Vt
It is required that the absolute value of h) be small. However, in general, the p-channel TFT method has a lower mobility (μ) than the n-channel TFT, and the threshold voltage (Vt
The absolute value of h) is large. This means, for example, Processin
gand Device Performance of Low-Temperature CMOS Po
ly-TFTs on 18.4-in.-Diagonal Substrater for AMLCD
Application I.-W. Wu et.al., SID 92 DIGEST, p-615-p
-618.

FIG. 4 shows the CMOS disclosed in the above document.
The circuit structure is shown. This CMOS circuit has an insulating substrate 1
P-channel TFT and n-channel TF formed on top
It has T. The p-channel TFT includes a source region / drain region 7P and a channel region 4 on the insulating substrate 1.
A semiconductor layer 15P having P is formed, and the substrate 1 is formed thereon.
An insulating film is formed so as to cover almost the entire surface of the gate insulating film to form the gate insulating film 5. A gate electrode 6P is formed thereon so as to face the active region 4P, and an interlayer insulating film 9 is formed so as to cover the gate electrode 6P. Further, a source electrode / drain electrode 11 is formed and electrically connected to the source region / drain region 7P through a contact hole 10P formed in the gate insulating film 5 and the interlayer insulating film 9. Further, in the n-channel TFT, a semiconductor layer 15N having a source / drain region 7N and an active region 4N is formed on the insulating substrate 1. The gate insulating film 5 is formed so as to cover it. A gate electrode 6N is formed thereon so as to face the active region 4N, and the interlayer insulating film 9 is formed so as to cover the gate electrode 6N. Furthermore, the source electrode / drain electrode 1
1 is formed, and the contact hole 10N formed in the gate insulating film 5 and the interlayer insulating film 9 forms the source region.
It is electrically connected to the drain region 7N.

This CMOS circuit is manufactured as follows. First, LPCVD (Low
thickness 1 by pressure chemical vapor deposition)
000 angstrom amorphous silicon film with a thickness of 10
A polycrystal silicon film is obtained by depositing it to a thickness of 00 angstrom and subjecting it to heat treatment for solid-phase crystallization. Next, this polycrystalline silicon film is patterned so that the p-channel region TFT region and the n-channel TFT region are left to form semiconductor layers 15P and 15N, and a thickness of 1000 angstrom is formed on almost the entire surface of the substrate so as to cover the semiconductor layers 15P and 15N. A gate insulating film (oxide film) 5 is formed. Further thereon, gate electrodes 6P and 6N made of a polycrystalline silicon film are formed.
Is formed, and using the gate electrodes 6P and 6N as a mask,
The p-channel semiconductor layer 15P has boron (B) ions, n
Phosphorus (P) ions are implanted into the channel semiconductor layer 15N. As a result, a source region / drain region 7P in which boron ions are implanted and a source region / drain region 7N in which phosphorus ions are implanted are formed, and impurity ions are introduced into the semiconductor layers 6P and 6N below the gate electrodes 6P and 6N. The channel regions 4P and 4N are formed without being implanted. Then, an interlayer insulating film 9 made of SiO ₂ and having a thickness of 7,000 Å is deposited. The substrate in that state is subjected to heat treatment to activate the implanted impurities. Then, the gate insulating film 5 and a predetermined portion of the interlayer insulating film are removed, and the contact hole 1 is formed so as to reach the source regions 7P and 7N.
Source electrode / drain electrode 1 with openings 0P and 10N
1 are formed respectively.

The characteristics of the p-channel TFT and the n-channel TFT in the CMOS circuit manufactured as described above are shown in Table 1 below.

[0006]

[Table 1]

As can be seen from Table 1 above, the p-channel TFT has a lower mobility and a larger absolute value of the threshold voltage than the n-channel TFT.

In order to improve the characteristics of the TFT, it is necessary to improve the quality of the polycrystalline silicon thin film that becomes the channel region of the TFT, and it is essential to reduce the defects in the thin film. Conventionally, in order to reduce this defect, a method of heat-treating a non-single crystal silicon thin film in an oxidizing atmosphere to oxidize it is used. For the method, see, for example, A POLYSI
LICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRA
Ms S. Ikeda et. Al., IEDM 90, p.469-p.472.

FIG. 5 shows the structure of the TFT shown in the above document. This TFT is a p-channel TFT, a gate electrode 6P is formed on a part of the insulating substrate 1, and a gate insulating film 5 made of a silicon oxide film is formed so as to cover the gate electrode 6P. A polycrystalline silicon semiconductor layer 15P having a source / drain region 7P and a channel region 4P is formed thereon.

This p-channel TFT is manufactured as follows. First, a gate electrode 6P is formed on a part of the insulating substrate 1, and a gate insulating film 5 made of a silicon oxide film is formed by LPCVD to cover the gate electrode 6P.
Next, an amorphous silicon film is formed to a thickness of 400 angstroms on the gate insulating film 4 by LPCVD using monosilane (SiH ₄ ) as a source gas and at 520 ° C. This amorphous silicon film is polycrystallized by heat treatment at 800 ° C. for 10 minutes in an oxygen (O ₂ ) atmosphere to form a polycrystalline silicon film. The surface layer of this polycrystalline silicon film is oxidized to form a silicon oxide film, and
Boron (B) ions are implanted using an appropriate mask and p
^{A +} source region 7P and a drain region 7P are formed. The substrate in this state is heat-treated at 850 ° C. for 20 minutes in a nitrogen gas atmosphere to activate the impurities. By the heat treatment in the oxygen gas atmosphere, defects in the polycrystalline silicon film are reduced, and a p-channel TFT having good characteristics can be obtained.

[0011]

As described above, in the CMOS circuit including the p-channel TFT and the n-channel TFT, the p-channel TFT generally has a significantly worse TFT characteristic than the n-channel TFT. Therefore, C
The performance of the MOS circuit (response speed, leak current, etc.) depends on the characteristics of the p-channel TFT. Also, p
When the characteristics of the channel TFT are significantly worse than the characteristics of the n-channel TFT, the symmetry of the characteristics of the CMOS circuit (rise of the CMOS circuit, etc.) is impaired.

The present invention has been made to solve the above problems, and an object of the present invention is to improve the characteristics of a p-channel TFT in a semiconductor device having a p-channel TFT and an n-channel TFT to improve the characteristics of the CMOS circuit. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of achieving higher performance and higher speed.

[0013]

The semiconductor device of the present invention comprises:
An n-channel thin film transistor and p on an insulating substrate
A semiconductor device in which a channel thin film transistor is formed, wherein the channel region of the p-channel thin film transistor and the channel region of the n-channel thin film transistor are formed by oxidizing a non-single crystal silicon thin film formed on an insulating substrate. , The oxidation amount of the non-single-crystal silicon thin film forming the p-channel thin film transistor is
The amount of oxidation is larger than that of the non-single-crystal silicon thin film forming the n-channel thin film transistor, and thereby the above object is achieved.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which an n-channel thin film transistor and a p-channel thin film transistor are formed on an insulating substrate, and a p-channel thin film transistor is formed on the insulating substrate. A step of forming a first non-single-crystal silicon thin film on the portion, performing a first heat treatment on the first non-single-crystal silicon thin film in an oxidizing atmosphere, and performing the first heat treatment. A step of forming a second non-single-crystal silicon thin film on a portion where an n-channel thin film transistor is formed on a substrate, and subjecting the first and second non-single-crystal silicon thin films to a second heat treatment in an oxidizing atmosphere. The above object is achieved thereby.

[0015]

In order to reduce the defects in the polycrystalline silicon thin film which becomes the channel region of the TFT, the non-single crystal silicon thin film is heat-treated and oxidized in an oxidizing atmosphere. At this time, there is an optimum amount of oxidation in the n-channel TFT.
Conversely, the FT characteristic deteriorates. On the other hand, p-channel TFT
The characteristics are further improved even when oxidized in a larger amount than the optimum amount of oxidation of the n-channel TFT.

In the present invention, the amount of oxidation of the non-single crystal silicon thin film forming the p-channel TFT is determined by the n-channel T
The amount of oxidation is larger than that of the non-single-crystal silicon thin film forming the FT. Therefore, p-channel TFT and n-channel T
In FT, the defects of each non-single crystal silicon film can be reduced, and the characteristics of both TFTs can be optimized.

A first non-single-crystal silicon thin film is formed on a portion where the p-channel TFT is formed, and the first non-single-crystal silicon thin film is subjected to a first heat treatment in an oxidizing atmosphere,
After that, a second non-single-crystal silicon thin film is formed in a portion where the n-channel TFT is formed, and a second heat treatment is performed on the first and second non-single-crystal silicon thin films in an oxidizing atmosphere. As a result, the n-channel TFT is formed so as to have the optimum amount of oxidation in the second heat treatment step, and the p-channel TFT is further oxidized in the second step in addition to the first heat treatment step. Since the amount of oxidation is larger than that of the TFT, the characteristics of both TFTs can be maximally improved.

In the present invention, non-single-crystal silicon refers to silicon other than single-crystal silicon, and any of amorphous, polycrystal and microcrystal can be used.

[0019]

In the present invention, in order to improve the characteristics of a semiconductor device, a non-single crystal silicon thin film forming a channel region is heat-treated in an oxidizing atmosphere to be oxidized. At that time, the oxidation amount of the non-single-crystal silicon thin film forming the p-channel TFT (film thickness of the oxide film formed on the surface of the non-single-crystal silicon thin film) is determined by the oxidation amount of the non-single-crystal silicon thin film forming the n-channel TFT. The reason for making it larger than the amount is as follows.

FIG. 3 shows the characteristics (mobility and absolute value of threshold voltage) of an n-channel TFT and a p-channel TFT produced by changing the amount of oxidation.

From this figure, it can be seen that in the case of the n-channel TFT, there is an optimum amount of oxidation in the mobility. If the amount of oxidation exceeds the optimum value, the mobility of the n-channel TFT decreases and the characteristics deteriorate. On the other hand, in the case of a p-channel TFT, the larger the amount of oxidation, the better the characteristics. Therefore, the single crystal silicon thin film forming the n-channel TFT is oxidized by the optimum oxidation amount of the n-channel TFT, and the p-channel T
The non-single crystal silicon thin film that constitutes the FT is an n-channel TF.
By oxidizing more than T, the characteristics of both the n-channel TFT and the p-channel TFT can be maximized.

Embodiments of the present invention will be described below with reference to the drawings. In the following figures, those having the same function will be described using the same numbers as in the conventional example.

(Embodiment 1) FIG. 1K shows an embodiment of the semiconductor device of the present invention. This semiconductor device includes a p-channel TFT and an n-channel TFT formed on an insulating substrate 1. In the p-channel TFT, a semiconductor layer 15P having a source / drain region 7P and a channel region 4P is formed on an insulating substrate 1, and an oxide film is formed thereon so as to cover almost the entire surface of the substrate 1 and a gate is formed. It is the insulating film 5. A gate electrode 6P is formed thereon so as to face the channel region 4P, and an interlayer insulating film 9 is formed so as to cover the gate electrode 6P. Further, a source electrode / drain electrode 11 is formed and electrically connected to the source region / drain region 7P through a contact hole 10P formed in the gate insulating film 5 and the interlayer insulating film 9. In the n-channel TFT, the source / drain regions 7 are formed on the insulating substrate 1.
A semiconductor layer 15N having N and a channel region 4N is formed. The gate insulating film 5 is formed so as to cover it. A gate electrode 6N is formed thereon so as to face the channel region 4N, and the interlayer insulating film 9 is formed so as to cover the gate electrode 6N. Further, the source / drain electrodes 11 are formed, and the gate insulating film 5 is formed.
And contact hole 10 formed in the interlayer insulating film 9
It is electrically connected to the source / drain region 7N by N. Semiconductor layer 15 forming a p-channel TFT
P is oxidized in a larger amount than the semiconductor layer 15N forming the n-channel TFT.

A semiconductor device having such a configuration is, for example,
It can be manufactured by the manufacturing process as shown in FIGS.

First, as shown in FIG. 1A, an amorphous silicon film 2 having a thickness of 1100 angstroms is formed on an insulating substrate 1 covered with quartz or an oxide film by LPCVD.
Deposit P. At this time, the temperature was set to 450 ° C., the raw material gas was disilane (Si ₂ H ₆ ) 100 sccm and nitrogen gas 4
00 sccm is used and the pressure is 50 Pa.

Next, in a nitrogen gas atmosphere, at 24 ° C. at 24 ° C.
The amorphous silicon film 2P is solid-phase crystallized by performing heat treatment for a time to form the first polycrystalline silicon film 2P. A method of solid-phase crystallization of an amorphous silicon film to obtain a polycrystalline silicon film is generally used. The heat treatment may be performed in an electric furnace, or may be performed by lamp heating or laser light irradiation. Further, the deposition of the amorphous silicon film 2P is
Other than the PCVD method, it may be performed by a photo CVD method, a plasma CVD method, a sputtering method, or the like, or may be formed in a polycrystalline state from the beginning.

This polycrystalline silicon film 2P is a p-channel T
Patterning is performed leaving only the FT region to form a polycrystalline silicon film 4P (first non-single-crystal silicon film) as shown in FIG.

Then, in an oxygen atmosphere, the temperature is 1050 ° C.
Then, the polycrystalline silicon film 4P is oxidized to form an oxide film 31 on the surface of the polycrystalline silicon film 4P as shown in FIG.
To a thickness of about 1000 angstroms (first
Heat treatment step). At this time, the thickness of the polycrystalline silicon film 4P is about 600 Å.

Next, as shown in FIG. 1D, an amorphous silicon film 2N having a thickness of 1100 angstrom is deposited on the substrate 1 in that state by the LPCVD method. At this time, the temperature was set to 450 ° C., disilane (Si ₂ H ₆ ) 100 sccm and nitrogen gas 400 sccm were used as source gases,
The pressure is 50 Pa.

Then, the amorphous silicon film 2N is solid-phase crystallized in the same manner as described above to form the second polycrystalline silicon film 2N. The amorphous silicon film 2N is deposited by LPCVD.
Other than the above method, it may be performed by an optical CVD method, a plasma CVD method, a sputtering method, or the like, or may be formed in a polycrystalline state from the beginning.

This polycrystalline silicon film 2N is formed into an n-channel T
Patterning is performed leaving only the FT region to form a polycrystalline silicon film 4N (second non-single-crystal silicon film) as shown in FIG.

Then, in an oxygen atmosphere, the temperature is 1050 ° C.
Then, the polycrystalline silicon film 4N is oxidized to form an oxide film 32 on the surface of the polycrystalline silicon film 4N as shown in FIG. 1 (f).
To have a thickness of about 600 Å (second heat treatment step). At this time, the thickness of the polycrystalline silicon film 4N is about 800 Å. At this time, the polycrystalline silicon film 4P is simultaneously oxidized in the p-channel TFT region, and the oxide film 32 is formed on the surface of the polycrystalline silicon film 4P. Since the oxide film 31 has already been formed on the surface of the polycrystalline silicon film 4P, even if the oxide film 31 is oxidized under the same conditions, the oxide film 32 of 200 angstroms is only formed. As a result, a total of 1200 angstroms of oxide films 31 and 32 are formed on the surface of the polycrystalline silicon film 4P, and the thickness of the polycrystalline silicon film 4P becomes about 500 angstroms.

Next, as shown in FIG. 1G, all the oxide films 31 and 32 formed in the first and second heat treatment steps are removed.

After that, as shown in FIG.
A gate insulating film 5 made of SiO ₂ and having a thickness of 850 Å is formed on almost the entire surface of the substrate 1 by the VD method.

Next, as shown in FIG. 1 (i), a thickness of 45
Gate electrodes 6P and 6N made of a P-doped Si film of 00 angstrom are formed, respectively.

Thereafter, as shown in FIG. 1 (j), the gate electrode 6N is used as a mask in the source / drain region 7N of the n-channel TFT under conditions of an acceleration voltage of 80 keV and an impurity density of 1 × 10 ¹⁵ cm ^-2 . Phosphorus (P) is ion-implanted and the gate electrode 6P is used as a mask to p-channel TFT
In the source / drain region 7P of the
Boron (B) under the conditions of V and impurity density of 1 × 10 ¹⁵ cm ^-2
Is ion-implanted. At this time, due to the shielding effect of the gate electrodes 6N and 6P, impurities are not ion-implanted into the portions below the gate electrodes 6N and 6P, and the channel regions 4N and 4P of the TFT are formed. In this embodiment, the p-channel TFT has a gate length of 5 μm and a gate width of 20 μm, and the n-channel TFT has a gate length of 7 μm and a gate width of 20 μm. The order of implanting impurities into the p-channel TFT region and the n-channel TFT region may be exchanged.

Next, an interlayer insulating film 9 made of SiO ₂ and having a thickness of 5000 Å is formed by CVD so as to cover the gate electrodes 6P and 6N, and heat treatment is performed at 950 ° C. for 30 minutes in an N ₂ atmosphere. Then, the implanted impurities are inactivated.

Further, as shown in FIG. 1 (k), predetermined portions of the gate insulating film 5 and the interlayer insulating film 9 are removed, and contact holes 10P and 10N are formed so as to reach the source / drain regions 7P and 7N. Form each.
Next, using Al, the source / drain regions 7P,
The source electrode / drain electrode 11 reaching 7N is formed.

Through the above steps, a semiconductor device having a p-channel TFT and an n-channel TFT can be obtained.

The characteristics of the p-channel TFT and the n-channel TFT in the semiconductor device obtained as described above are shown in Table 2 below.

[0041]

[Table 2]

As a comparative example, p
The characteristics of a p-channel TFT in a semiconductor device in which a channel TFT and an n-channel TFT are simultaneously formed are shown. The semiconductor device of the comparative example was manufactured as follows. First, an amorphous silicon film is deposited on an insulating substrate covered with quartz or an oxide film in the same manner as in the embodiment, and a polycrystalline silicon film is formed in the same manner as in the embodiment.

This polycrystalline silicon film is patterned, leaving only the p-channel region and the n-channel region. Then, the polycrystalline silicon film is oxidized in an oxygen atmosphere at a temperature of 1050 ° C. to form an oxide film on the surface of the polycrystalline silicon film with a thickness of about 600 Å. At this time,
The oxide film has a thickness of about 600 Å in both the n-channel region and the p-channel region.

After that, all the oxide film formed is removed,
The subsequent steps are the same as those in the example to manufacture a semiconductor device.

As can be understood from Table 2 above, the p-channel TFT of the semiconductor device of the example has an oxide film with a thickness of 600.
The characteristics could be greatly improved as compared with the p-channel TFT of the semiconductor device of the comparative example formed in angstrom.

(Embodiment 2) FIG. 2 shows another embodiment of the semiconductor device of the present invention. This semiconductor device has an insulating substrate 1.
P-channel TFT and n-channel TF formed on top
It has T. In the p-channel TFT, the gate electrode 6P is formed on the insulating substrate 1, and the substrate 1 is formed thereon.
An oxide film is formed so as to cover almost the entire surface of the gate insulating film 5 to form the gate insulating film 5. A semiconductor layer 15P having a source / drain region 7P and a channel region 4P thereon
Is formed so as to face the gate electrode 6P, and the interlayer insulating film 9 is formed so as to cover the semiconductor layer 15P. Further, a source electrode / drain electrode 11 is formed and electrically connected to the source region / drain region 7P through a contact hole 10P formed in the gate insulating film 5 and the interlayer insulating film 9. In the n-channel TFT, the gate electrode 6N is formed on the insulating substrate 1, and an oxide film is formed thereon so as to cover almost the entire surface of the substrate 1 to form the gate insulating film 5. A semiconductor layer 15N having a source region / drain region 7N and a channel region 4N is formed thereon so as to face the gate electrode 6N, and an interlayer insulating film 9 is formed so as to cover the semiconductor layer 15N. Further, the source electrode / drain electrode 11 is formed, and the contact hole 10 formed in the interlayer insulating film 9 is formed.
It is electrically connected to the source / drain region 7N by N. Semiconductor layer 15 forming a p-channel TFT
P is oxidized in a larger amount than the semiconductor layer 15N forming the n-channel TFT.

The semiconductor device having such a structure can be manufactured as follows.

First, the gate electrodes 6P and 6N are formed on a part of the insulating substrate 1. Next, a gate insulating film 5 made of a silicon oxide film having a thickness of 850 angstrom is formed by LPCVD method so as to cover almost the entire surface of the substrate 1.

Next, in the same manner as in Example 1, a polycrystalline silicon film (first non-single-crystal silicon film) is formed in the P-channel TFT region and is oxidized in an oxygen atmosphere at a temperature of 1050 ° C. An oxide film with a thickness of 10 is formed on the surface of the polycrystalline silicon film.
It is formed to have a thickness of about 00 Å (first heat treatment step).

Thereafter, in the same manner as in Example 1, a polycrystalline silicon film (second non-single-crystal silicon film) is formed in the n-channel region and is oxidized at a temperature of 1050 ° C. in an oxygen atmosphere to give the polycrystalline film. An oxide film with a thickness of 600 is formed on the surface of the silicon film.
It is formed to have a thickness of about angstrom (second heat treatment step). At this time, the first non-single-crystal silicon film is also oxidized at the same time, and an oxide film with a thickness of 2 is formed on the surface of the polycrystalline silicon film.
It is formed to about 00 angstrom. As a result, the thickness of the oxide film formed on the surface of the first non-single-crystal silicon film (p-channel TFT region) becomes about 1200 Å in total, and the second non-single-crystal silicon film (n-channel TFT region) is formed. The thickness of the oxide film formed on the surface of the is about 600 Å.

Next, all the oxide film formed in the first and second heat treatment steps is removed.

After that, a photoresist film is formed in a predetermined pattern on the first and second polycrystalline silicon films 15P and 15N, and the photoresist film is used as a mask.
In the source / drain region 7N of the n-channel TFT,
Phosphorus (P) is ion-implanted under the conditions of an acceleration voltage of ¹⁵ keV and an impurity density of 1 × 10 ¹⁵ cm ^-2 , and a p-channel TF is used.
Acceleration voltage 15k applied to the source / drain region 7P of T
Boron (B) is ion-implanted under the conditions of eV and impurity density of 1 × 10 ¹⁵ cm ⁻² . At this time, the impurity ions are not implanted into the portion below the photoresist film, and the channel regions 4N and 4P of the TFT are formed.

Next, an interlayer insulating film 9 made of SiO ₂ and having a thickness of 5000 angstrom is formed by the CVD method so as to cover the polycrystalline silicon films 15P and 15N.
_{2 In} atmosphere, heat treatment at 950 ℃ for 30 minutes,
Deactivate implanted impurities.

Further, a predetermined portion of the interlayer insulating film 9 is removed, and contact holes 10P and 10N are formed so as to reach the source / drain regions 7P and 7N, respectively. Next, Al is used to form the source electrode / drain electrode 11 reaching the source / drain regions 7P and 7N, respectively.

Through the above steps, a semiconductor device having a p-channel TFT and an n-channel TFT can be obtained.

Also in the semiconductor device of this example, the characteristics of the p-channel TFT could be greatly improved.

In Examples 1 and 2, the amorphous silicon film was once polycrystallized and then oxidized to improve the characteristics. However, even if the amorphous silicon film is oxidized in the state. Good. As the oxidizing atmosphere, hydrogen chloride / oxygen (hydrochloric acid oxidation), water vapor, nitrous oxide, or the like can be used in addition to oxygen. Further, the high pressure oxidation may be performed at a pressure higher than the atmospheric pressure.

[0058]

As is apparent from the above description, according to the present invention, a high-performance semiconductor device including an n-channel TFT and a p-channel TET having high mobility and low threshold voltage can be obtained. Therefore, it is possible to realize a high-resolution liquid crystal display panel, a high-speed and high-resolution image sensor, a three-dimensional IC, and the like.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a p-channel TFT manufactured by changing the amount of oxidation.
5 is a graph showing characteristics of an n-channel TFT.

FIG. 4 is a sectional view showing a conventional semiconductor device.

FIG. 5 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 1 Insulating substrate 2P, 2N Amorphous silicon film 31, 32 Oxide film 4P, 4N Polycrystalline silicon film 5 Gate insulating film 6P, 6N Gate electrode 7P, 7N Source region / drain region 9 Interlayer insulating film 10P, 10N Contact hole 11 Source and drain electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 G

Claims (2)

[Claims] 1. A semiconductor device in which an n-channel thin film transistor and a p-channel thin film transistor are formed on an insulating substrate, wherein the channel region of the p-channel thin film transistor and the channel region of the n-channel thin film transistor are each an insulating substrate. The non-single-crystal silicon thin film formed above is oxidized, and the oxidation amount of the non-single-crystal silicon thin film forming the p-channel thin film transistor is larger than that of the non-single-crystal silicon thin film forming the n-channel thin film transistor. Many semiconductor devices. 2. A method of manufacturing a semiconductor device comprising an n-channel thin film transistor and a p-channel thin film transistor formed on an insulating substrate, wherein a first non-single film is formed on a portion of the insulating substrate where the p-channel thin film transistor is formed. Forming a crystalline silicon thin film, performing a first heat treatment on the first non-single-crystal silicon thin film in an oxidizing atmosphere, and forming an n-channel thin film transistor on the substrate subjected to the first heat treatment Forming a second non-single-crystal silicon thin film on a portion of the first non-single-crystal silicon thin film and subjecting the first and second non-single-crystal silicon thin films to a second heat treatment in an oxidizing atmosphere; Method.