JPH06317630A - Substrate for semiconductor thermostatic acceleration test device - Google Patents

Abstract

PURPOSE:To obtain a low-priced substrate for a semiconductor thermostatic acceleration test device. CONSTITUTION:A hook 19 for installing a semiconductor device mounting article 1 facing downward is provided on a substrate upper surface part 14a. Pogo pins 20, 21 are disposed in designated positions on the substrate upper surface part 14a in such a manner as to be pressed to a power supply and GND terminals 9a, 9b of the installed semiconductor device mounting article 1. Pattern wirings 17, 18 for supplying power to the pogo pins 20, 21 are disposed on the lower side of the substrate upper surface part 14a. Power can be supplied from the power supply and GND terminals 9a, 9b for installing a chip condenser for noise noise countermeasure to the semiconductor device mounting article 1 to a semiconductor device. Thus, the semiconductor device mounting article can be fixed in a simple structure comprising the pogo pins 20, 21 and the hook 19 without any expensive mounting tool such as a socket or the like to supply power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor constant temperature acceleration test, and more particularly to a semiconductor device packaged product having a power source and a GND terminal on the package surface for mounting a chip capacitor as a noise countermeasure, and a device requiring heat radiation. The present invention relates to a substrate for a semiconductor constant temperature acceleration test device used for a semiconductor device mounted product.

[0002]

2. Description of the Related Art FIG. 7 is a perspective view showing the structure of a conventional semiconductor constant temperature acceleration tester substrate (burn-in board).

In FIG. 7, reference numeral 1 is a semiconductor device package to be tested, 2 is a fin used to dissipate the semiconductor device package 1, and 3 is a semiconductor device package 1 for mounting the semiconductor device package 1. Sockets arranged side by side for the number of pieces,
Reference numeral 4 denotes a substrate, 4a denotes a substrate upper surface portion made of a glass epoxy material for fixing the socket 3, 4b denotes a metal support portion for preventing the warp of the substrate upper surface portion 4a, 4c denotes a substrate lower surface portion made of the glass epoxy material, 5 denotes A power supply terminal is supplied with a power supply voltage from the semiconductor constant temperature acceleration test apparatus, and 6 is a GND terminal supplied with a GND voltage (0 V) from the semiconductor constant temperature acceleration test apparatus. Power supply, GND terminals 5, 6 to semiconductor device mounted product 1
In order to supply power to the semiconductor device mounted product 1, pattern wiring is provided to the position of the hole of the socket 3 into which the power source and the GND pin are inserted. The substrate 4 is composed of a substrate upper surface portion 4a, a metal pillar portion 4b, and a substrate lower surface portion 4c.

FIGS. 8A and 8B are a plan view and a side view showing details of a semiconductor device mounted product to be tested. In FIG. 8, reference numeral 1 is a semiconductor device mounting product in which a semiconductor device is mounted on a ceramic pin grid array package.

Further, 7 is a plate to which a semiconductor device is die-bonded on the back surface thereof, and fins for cooling the semiconductor device by removing heat from the heat-generating semiconductor device are attached, 9a.
Is a power supply terminal for mounting a chip capacitor for noise suppression between the power supply and GND, 9b is a power supply and GND
A GND terminal for mounting a chip capacitor for noise suppression therebetween, 10 are pins for transmitting a power source and a signal, and particularly 10a and 10b are a power source and a power source pin for supplying a GND voltage to a semiconductor device. This is the GND pin.

FIG. 9 is a diagram showing the concept of the configuration of a semiconductor device mounted product to be tested. In FIG. 9, reference numeral 8 denotes a semiconductor device that is fixedly mounted on the plate 7, and the same reference numerals as those in FIG. 8 denote the same or corresponding portions as those in FIG.

The semiconductor device 8 has a power supply pin 10a and a GN.
The power supply voltage and the GND voltage are supplied from the D pin 10b. The power supply pin 10a and the power supply terminal 9a are connected, and the GND pin 10b and the GND terminal 9b are connected.

When conducting the constant temperature acceleration test, first, the substrate 4
The required number of the semiconductor device mounted products 1 are mounted in the sockets 3 of 1. However, the semiconductor device mounted product 1 mounted on the substrate 4
If heat dissipation (cooling) is required for the semiconductor mounted product 1 together with the fin 2 in the socket 3. Then, in this state,
The substrate 4 is inserted into the semiconductor constant temperature acceleration test device, and a voltage is applied from the semiconductor constant temperature acceleration test device to each semiconductor device mounting component 1 through the power supply terminal 5 and the GND terminal 6, and the temperature acceleration test is performed according to the temperature inside the device. To be done.

[0009]

Since the conventional substrate for semiconductor accelerating test apparatus is constructed as described above, the socket 3 and the fin 2 must be used for voltage application and heat radiation effect, and the whole substrate is required. There was a problem that it became expensive.

The present invention has been made to solve the above problems, and is an inexpensive semiconductor constant temperature acceleration test apparatus having the same voltage application and heat radiation effects as the conventional one without using a socket and fins. The purpose is to obtain a substrate.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor constant temperature acceleration test apparatus substrate, wherein a power source, a power source for an external component connected to a GND pin, and a constant temperature of a semiconductor device package having a GND terminal on a package surface. A semiconductor constant temperature acceleration test device substrate used for an acceleration test, comprising: an upper surface portion on which the semiconductor device mounted product is mounted; and a power supply provided on the upper surface portion, the semiconductor device mounted product, and a GND terminal. And a power supply means for supplying power.

A semiconductor constant temperature acceleration test apparatus substrate according to a second aspect of the present invention is the semiconductor constant temperature acceleration test apparatus substrate of the first aspect, wherein the power supply means is provided on the upper surface portion, and the semiconductor device is mounted. It is configured to include a power supply and a GND pin which are arranged so as to be in contact with the power supply and the GND terminal of the product, the power supply being arranged according to the shape of the semiconductor device mounted product.

A semiconductor constant temperature acceleration test apparatus substrate according to a third aspect of the present invention is the semiconductor constant temperature acceleration test apparatus substrate of the first aspect of the present invention, wherein the semiconductor device package includes a semiconductor device package having a heat dissipation surface. The upper surface portion is further provided with a heat radiating means provided on the upper surface portion so as to be in close contact with the heat radiating surface in a state where the semiconductor device mounted product is placed on the upper surface portion.

[0014]

The power supply means according to the first aspect of the present invention can supply power to the semiconductor device-mounted product mounted on the upper surface and to the GND terminal. Power can be supplied to the semiconductor device without using pins.

The power supply pin and the GND pin of the power supply means in the second invention are the power supply of the semiconductor device mounted product, G
By contacting the ND terminal, the power supply terminal and the GND
Power can be supplied to the semiconductor device by being electrically connected to the terminal.

The heat radiating means in the third aspect of the invention is in close contact with the heat radiating surface of the semiconductor device package, and can conduct the heat generated by the semiconductor device to radiate it to the atmosphere.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing the structure of a substrate for semiconductor constant temperature acceleration test equipment according to a first embodiment of the present invention. In FIG. 1, 1 is mounted on a substrate for semiconductor constant temperature acceleration test equipment,
A semiconductor device mounted product to be evaluated, 14 is a substrate for a semiconductor constant temperature acceleration test device, 14a is a substrate upper surface portion made of a glass epoxy material which constitutes the substrate 14, 14b constitutes the substrate 14, and warps of the substrate upper surface portion 14a. Metal props to prevent, 1
Reference numeral 4c denotes a substrate lower surface portion made of a glass epoxy material forming the substrate 14, 14d denotes a connector portion provided on the substrate upper surface portion 14a, and 15 denotes a connector portion 14a.
When 4 is mounted on the semiconductor constant temperature acceleration test apparatus, a power supply terminal to which a voltage is supplied from the semiconductor constant temperature acceleration test apparatus, 16 is provided in the connector portion 14d, and when the substrate 14 is mounted on the semiconductor constant temperature acceleration test apparatus, the semiconductor constant temperature acceleration test Device to G
A GND terminal supplied with an ND voltage, 20 is a pogo pin for power supply, and 21 is a pogo pin for GND supply.

When the semiconductor device-mounted product 1 is mounted on the substrate 14, these pogo pins 20 and 21 are mounted on the substrate 14.
Of the power source and the GND for mounting a chip capacitor for noise countermeasures, the power source GND terminals 9a and 9b are in contact with each other, and the pattern wiring formed on the upper surface 4a of the substrate causes the power source and the GND terminals 15 and 16 to be connected. Is connected. Reference numeral 12 denotes a hook for fixing the semiconductor device mounted product 1 on the board upper surface portion 14a while keeping the pogo pins 20 and 21 in contact with the semiconductor device mounted product 1 in a state of being turned over as shown in the figure.

FIG. 2 is a sectional view taken along the line II of FIG. In FIG. 2, 9a and 9b are power supply terminals and GND terminals provided on the package surface of the semiconductor device mounted product 1,
Reference numerals 20 and 21 denote a power supply pogo pin and a GND supply pogo pin that are in contact with the power supply terminal 9a and the GND terminal 9b, respectively, and 17 is formed on the substrate upper surface portion 14a. Power supply wiring for supplying a power supply voltage, 18 is a substrate upper surface portion 14
1 is a GND supply wiring for supplying a power supply voltage from the power supply terminal 16 shown in FIG. 1 to the GND supply pogo pin 21, and the same reference numerals as those in FIG. 1 denote the same parts as those in FIG.

As shown in FIG. 2, the hooks 19 are thinner near the substrate upper surface 44a and thicker toward the top. Therefore, the distance between the hooks 19 is closer to the semiconductor near the substrate upper surface 44a. Although it is longer than the width of the device-mounted product 1, the distance between the hooks 19 is smaller than the width of the semiconductor device-mounted product 1 at a position apart from the board upper surface portion 44a. Therefore, the semiconductor device package 1 is slightly tilted, and the hooks 1 are pushed while pushing down the pogo pins 20 and 21.
The semiconductor device mounted product 1 is fitted between 9 and then the semiconductor device mounted product 1 is made horizontal. Then, as shown in the figure, the repulsive force of the pogo pins 20 and 21 and the hook 19 cause the pogo pin 2 to move.
It is possible to mount the semiconductor device package 1 from 0, 21 in a state in which power can be supplied.

FIG. 3 is a diagram showing the structure of pogo pins. In FIG. 3, 30 is a shaft, 31 is a contact portion fixed to one end of the shaft 30, and 32 is formed on the other end of the shaft 30.
The end of which the diameter is larger than the base of the
Is a spring that supports the shaft 30 in a vertically movable manner, and 34 is a cylindrical body that houses the end portion 32 of the shaft 30 and the spring 33 in a state where the shaft 30 and the spring 33 can move up and down.

The shaft 30, the contact portion 31, the spring 33, and the cylindrical body 34 are made of a conductive material such as metal.
A predetermined current can be supplied from a power source connected to the cylindrical body 34 to a portion where the upper portion of the contact portion 31 contacts. Also,
When a force is applied to the contact portion 31 and the spring 33 contracts in the vertical direction, a repulsive force is generated.

The substrate 14 is used for testing the semiconductor device package 1 which does not require heat dissipation. The board 14 turns over the semiconductor device package 1 having the power supply and the GND terminals 9a and 9b on the package surface, and supplies the power supply and the GND terminals 9a and 9b on the package surface to the power supply pogo pins 20 and GND on the board upper surface portion 4a. By making contact with the pogo pin 21 for electrical connection, it is electrically connected, and fixed by the fixing hook 19 and mounted. The semiconductor mounted products 1 are mounted on the board 14 in the number corresponding to the number of mounted boards, and the boards 14 are inserted into the semiconductor constant temperature acceleration test apparatus.

A voltage is supplied from the power supply of the semiconductor constant temperature acceleration tester to the power supply terminal 15 and the GND terminal 16 of the substrate upper surface portion 14a, and to each semiconductor device package 1 through each power supply pogo pin 20 and each GND supply pogo pin 21. It is applied and a constant temperature acceleration test is performed. According to such a configuration, the pogo pin 20,
With the inexpensive and simple structure of 21 and hook 19, the same effect as that of the conventional semiconductor constant temperature acceleration test apparatus substrate can be obtained.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a perspective view showing the structure of a semiconductor constant temperature acceleration test apparatus substrate according to the second embodiment of the present invention. Figure 2
In the above, 1 is a semiconductor device mounted product which is mounted and evaluated on a semiconductor constant temperature acceleration test device substrate, 44 is a substrate, and 44a
Is a substrate upper surface portion made of a glass epoxy material, 44b is a metal column portion for preventing the warp of the substrate upper surface portion 44a, and 44c is a substrate lower surface portion made of a glass epoxy material. The substrate 44 includes a substrate upper surface portion 44a, a metal support portion 44b, and a substrate lower surface portion 4
4c.

Further, 44d is a connector portion provided on the substrate upper surface portion 44a, 45 is a connector portion 44a,
When the substrate 44 is mounted on the semiconductor constant temperature acceleration test apparatus, power supply terminals to which voltage is supplied from the semiconductor constant temperature acceleration test apparatus, 4
6 is provided in the connector portion 44d and is a GND terminal to which a GND voltage is supplied from the semiconductor constant temperature acceleration test device when the substrate 44 is mounted on the semiconductor constant temperature acceleration test device, 50 is a pogo pin for power supply, and 51 is a pogo pin for GND supply. is there.

When the semiconductor device mounted product 1 is mounted on the substrate 44, these pogo pins 50 and 51 are attached to the semiconductor device mounted product 1.
In order to mount a chip capacitor for noise suppression between the power source and the GND, the power source GND terminals 9a and 9b are in contact with each other. And the pogo pin 50 for power supply
Also, the pond pins 51 for GND supply are connected to the power supply and the GND terminal 4 by the pattern wiring formed on the upper surface 44a of the substrate.
It is connected to 5,46. Reference numeral 49 is a hook for fixing the semiconductor device mounted product 1 to the upper surface 44a of the substrate while keeping the pogo pins 50, 51 and the semiconductor device mounted product 1 in contact with each other as shown in the figure.

Reference numeral 43a denotes a heat radiating plate provided below the upper surface 44a of the substrate, and 43b denotes a heat radiating plate contact surface corresponding to an upper surface of a convex portion formed on one main surface of the heat radiating plate 43a. The convex portion formed on the one main surface of the heat dissipation plate 43a has the semiconductor device package 1 when the semiconductor device package 1 is fixed by the hook 49.
So as to contact the heat dissipation plate 7 of
It is fitted in a square hole provided in the.

FIG. 5 is a sectional view taken along the line II-II in FIG. In the figure, 9a and 9b are a power supply terminal and a GND terminal provided on the package surface of the semiconductor device mounted product 1, and 5
0 and 51 are pogo pins that are in contact with the power supply terminal 9a and the GND terminal 9b, respectively, and 48 is formed on the upper surface 44a of the substrate to supply the power supply voltage from the power supply terminal 45 to the power supply pogo pin 50 shown in FIG. The pattern wiring 47 is formed on the upper surface 44a of the substrate, and the power supply terminal 4 shown in FIG.
6 is a pattern wiring for supplying a power supply voltage to the GND supply pogo pin 51, and the same reference numerals as those in FIG. 4 denote the same parts as those in FIG. When the heat dissipation plate 43a is made of a conductive material, the pattern wiring 48 and the pogo pins 50 and the heat dissipation plate 43a of the board upper surface portion 44a or the pattern wiring 47 of the board upper surface portion 44a are usually at least used.
The pogo pin 51 and the heat dissipation plate 43a are electrically insulated from each other, and the power supply and the GND wiring are not short-circuited through the heat dissipation plate 43a.

The substrate 44 is used for testing the semiconductor device package 1 which requires heat dissipation. The board 44 has the power supply and GND terminals 9a, 9b on the package surface turned upside down, and the power supply terminals 9a and the GND terminals 9b on the package surface are supplied with the pogo pins 50 and GND for power supply on the board upper surface portion 4a. By making contact with the pogo pin 51 for electrical connection, the heat dissipation plate 7
The heat radiating plate contact surface 43b is brought into contact with to be thermally connected, and the elasticity of the springs of the pogo pins 50 and 51 is utilized to fix and attach the hook 49 as in the first embodiment. Mount the same number of semiconductor mounted products 1 on the board 44 as
Is inserted into the semiconductor constant temperature acceleration tester. The heat dissipation plate 43a is provided so as to have the same heat dissipation effect as the conventional fin 2 shown in FIG.

A voltage is supplied from the power supply of the semiconductor constant temperature acceleration tester to the power supply terminal 45 and the GND terminal 46 of the substrate upper surface portion 44a, and to each semiconductor device package 1 through each power supply pogo pin 50 and each GND supply pogo pin 51. Semiconductor device mounted product 1 according to the applied voltage and further applied voltage
The heat generated by the semiconductor device 8 therein is conducted to the heat radiating plate 43a through the heat radiating plate 7 and is radiated, and the constant temperature acceleration test is performed. According to this structure, the same effect as that of the conventional semiconductor constant temperature acceleration test device substrate can be obtained by using the pogo pins 50, 51, the hook 49, and the heat dissipation plate 43a, which are inexpensive and simple, without using expensive sockets and fins. Is obtained.

In order to improve the adhesion between the heat dissipation plate 7 and the heat dissipation plate 43a, a silicon rubber 52 having good heat conductivity may be placed on the heat dissipation plate contact surface 43b as shown in FIG. By utilizing the elastic deformation of the silicon rubber, the heat dissipation plate 7 and the heat dissipation plate 43a can be firmly brought into close contact with each other. Therefore, any material other than silicone rubber may be used as long as it has desired thermal conductivity and is elastically deformable.

[0033]

As described above, according to the substrate for semiconductor constant temperature acceleration test apparatus of the invention described in claim 1, the power source is provided on the upper surface and is used for supplying power to the semiconductor device mounted product and the GND terminal. Since it is configured with a supply means,
There is an effect that a semiconductor device mounted without using a socket as in the past can be supplied with power by using a power supply means, and an inexpensive semiconductor constant temperature accelerated test apparatus substrate can be obtained.

According to the substrate for semiconductor constant temperature accelerating device of the second aspect of the present invention, the power supply means is provided on the upper surface portion, and the semiconductor device packaged product is brought into contact with the power source of the semiconductor device packaged product and the GND terminal. Since it is configured to include a power supply arranged according to the shape of and a GND pin, it is possible to supply power to a semiconductor device mounted by using a power supply for a power supply means that is cheaper than a socket and a GND pin. Therefore, there is an effect that an inexpensive semiconductor constant temperature acceleration test device substrate can be obtained.

According to the substrate for semiconductor constant temperature acceleration test apparatus of the third aspect of the present invention, the upper surface of the substrate is mounted on the upper surface so that the semiconductor device mounted product is placed on the upper surface so as to be in close contact with the heat radiation surface. Since it is configured with the heat dissipation means provided,
It is possible to obtain the same heat radiation effect as in the case of using a fin without using a fin as in the conventional case, and to obtain an inexpensive semiconductor constant temperature acceleration test apparatus substrate.

[Brief description of drawings]

FIG. 1 is a perspective view showing the structure of a substrate for semiconductor constant temperature acceleration test equipment according to a first embodiment of the present invention.

FIG. 2 is an I-of a substrate for a semiconductor acceleration test apparatus in FIG.
It is a sectional view taken along the arrow I.

FIG. 3 is a diagram showing a configuration of pogo pins used for the substrate for semiconductor constant temperature acceleration test equipment of the present invention.

FIG. 4 is a perspective view showing the structure of a semiconductor constant temperature acceleration test apparatus substrate according to a second embodiment of the present invention.

[FIG. 5] II- of the substrate for semiconductor acceleration test equipment in FIG.
FIG. 2 is a sectional view taken along line II.

FIG. 6 is a sectional view showing another embodiment of the substrate for semiconductor constant temperature acceleration test equipment according to the second embodiment of the present invention.

FIG. 7 is a perspective view showing the configuration of a conventional semiconductor constant temperature acceleration test device substrate.

8A and 8B are a plan view and a side view showing an external appearance of a semiconductor device mounted product which is a target of a test in a semiconductor constant temperature acceleration test device.

FIG. 9 is a diagram for explaining a configuration of a semiconductor device mounted product which is a target of a test in a semiconductor constant temperature acceleration test device.

[Explanation of symbols]

 1 semiconductor device mounted product 2 fins 3 sockets 4, 14, 44 substrates 4a, 14a, 44a substrate upper surface portions 4b, 14b, 44b metal pillar portions 4c, 14c, 44c substrate lower surface portion 5, 15, 45 power supply terminals 6, 16, 46 GND Terminal 7 Heat Dissipation Plate 8 Semiconductor Device 9a Power Terminal 9b GND Terminal 10 Pin 17 Power Supply Wiring 18 GND Supply Wiring 20,50 Power Supply Pogo Pin 21,51 GND Supply Pogo Pin 19 Hook

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[Procedure amendment]

[Submission date] August 26, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

A third substrate for a semiconductor thermostatic accelerated test apparatus according to the present invention is a semiconductor constant temperature acceleration test device substrate of the first aspect, the semiconductor instrumentation 置実 Sohin is a semiconductor device mounting articles having heat radiating surface In addition, the upper surface portion is configured to further include a heat radiating unit provided on the upper surface portion so as to be in close contact with the heat radiating surface in a state where the semiconductor device mounted product is placed on the upper surface portion.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing the structure of a substrate for semiconductor constant temperature acceleration test equipment according to a first embodiment of the present invention. In FIG. 1, 1 is mounted on a substrate for semiconductor constant temperature acceleration test equipment,
A semiconductor device mounted product to be evaluated, 14 is a substrate for a semiconductor constant temperature acceleration test device, 14a is a substrate upper surface portion made of a glass epoxy material which constitutes the substrate 14, 14b constitutes the substrate 14, and warps of the substrate upper surface portion 14a. Metal props to prevent, 1
Reference numeral 4c denotes a substrate lower surface portion made of a glass epoxy material that constitutes the substrate 14, 14d denotes a connector portion provided on the substrate upper surface portion 14a, and 15 denotes a connector portion 14d.
When 4 is mounted on the semiconductor constant temperature acceleration test apparatus, a power supply terminal to which a voltage is supplied from the semiconductor constant temperature acceleration test apparatus, 16 is provided in the connector portion 14d, and when the substrate 14 is mounted on the semiconductor constant temperature acceleration test apparatus, the semiconductor constant temperature acceleration test Device to G
A GND terminal supplied with an ND voltage, 20 is a pogo pin for power supply, and 21 is a pogo pin for GND supply.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

When the semiconductor device-mounted product 1 is mounted on the substrate 14, these pogo pins 20 and 21 are mounted on the substrate 14.
Of the power source and the GND for mounting a chip capacitor for noise countermeasures, the power source GND terminals 9a and 9b are in contact with each other, and the pattern wiring formed on the upper surface 4a of the substrate causes the power source and the GND terminals 15 and 16 to be connected. Is connected. Reference numeral 19 is a hook for fixing the semiconductor device mounted product 1 on the substrate upper surface portion 14a while keeping the pogo pins 20, 21 and the semiconductor device mounted product 1 in contact with each other in a state of being turned over as shown in the figure.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

As shown in FIG. 2, the hook 19 is the upper surface of the substrate.
14a and it is narrowed near, since the thickened toward the top, but in a place close to the upper surface of the substrate portion 14a the distance between the hooks 19 is longer than the width of the semiconductor device mounting article 1, the substrate The distance between the hooks 19 is smaller than the width of the semiconductor device package 1 at a position away from the upper surface portion 14a . Therefore, the semiconductor device package 1 is slightly tilted, and the hooks 1 are pushed while pushing down the pogo pins 20 and 21.
The semiconductor device mounted product 1 is fitted between 9 and then the semiconductor device mounted product 1 is made horizontal. Then, as shown in the figure, the repulsive force of the pogo pins 20 and 21 and the hook 19 cause the pogo pin 2 to move.
It is possible to mount the semiconductor device package 1 from 0, 21 in a state in which power can be supplied.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Explanation of reference numerals] 1 semiconductor device mounted product 2 fins 3 sockets 4, 14, 44 substrate 4a, 14a, 44a substrate upper surface portion 4b, 14b, 44b metal support portion 4c, 14c, 44c substrate lower surface portion 5, 15, 45 power supply Terminals 6, 16, 46 GND terminal 7 Heat dissipation plate 8 Semiconductor device 9a Power supply terminal 9b GND terminal 10 Pin 10a Power supply pin 10b GND pin 17 , 47 Power supply wiring 18 , 48 GND supply wiring 20, 50 Power supply pogo pin 21 , 51 GND supply pogo pin 19 , 49 Hook 43a Heat dissipation plate 43b Heat dissipation plate contact figure 52 Silicon rubber 30 Pogo pin shaft 31 Pogo pin contact part 32 Pogo pin end part 33 Pogo pin spring 34 Pogo pin cylinder

[Procedure correction 6]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

Claims (3)

[Claims] 1. A semiconductor constant temperature acceleration test apparatus substrate used for a constant temperature acceleration test of a semiconductor device mounted article having a power source, a power source for an external component connected to a GND pin, and a GND terminal on a package surface. A substrate for a semiconductor constant temperature acceleration test apparatus, comprising: an upper surface part on which the semiconductor device is mounted; and a power supply means provided on the upper surface part for supplying power to the power supply and the GND terminal of the semiconductor device mounted product. 2. The power supply means is provided on the upper surface portion, and is arranged according to the shape of the semiconductor device package so as to come into contact with the power source of the semiconductor device package and the GND terminal. The semiconductor thermostatic acceleration test apparatus substrate according to claim 1, comprising a GND pin. 3. The semiconductor device packaged article includes a semiconductor device packaged article having a heat radiation surface, and the upper surface portion is in close contact with the heat radiation surface when the semiconductor device packaged article is placed on the upper surface portion. The semiconductor constant temperature acceleration test apparatus substrate according to claim 1, further comprising a heat dissipation means provided on the upper surface portion.