JPH06314702A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to form a thick-film gate electrode of low sheet resistance using the material having high specific resistance and large thermal stress. CONSTITUTION:This field-effect transistor has a gate electrode 7 consisting of a plurality of layers (four layers in this case) formed by the same material, and on the layers 7a to 7d which constitute the plural layers, layers having different residual stress (stress direction and stress magnitude) with each other are contained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor (MESFET) having a gate of a Schottky contact made of a metal and a semiconductor, and a manufacturing method thereof.

[0002]

2. Description of the Related Art The following requirements are known to be required for Schottky contacts used as gate electrodes of MESFETs ("Ultra-high speed compound semiconductor device", supervised by Takuo Sugano, Masamichi Omori). Edition, publisher; Baifukan, p.202). First, it is required that the height φ _{B of the} barrier viewed from the metal side is large. Second, n
The value (ideality factor) is required to be close to 1, and the third
Requires that the interface structure be thermally stable and highly reliable. Further, in selecting the electrode material, in addition to the above conditions, (1) low resistance, (2) fine workability,
(3) Adhesion with the substrate, (4) Heat resistance, (5) Low thermal stress with the semiconductor substrate, etc. are required as important conditions.
Specifically, for GaAs substrates, Al, Ti-Pt-Au,
There are TiW, WSix, WAl, WN and the like.

Further, as a method of manufacturing MESFET,
Among these, there is a heat-resistant gate n ⁺ self-alignment technique using a heat-resistant metal.

[0004]

However, the heat-resistant gate n
⁺ Some MESFET gate materials manufactured by the self-alignment technology have the following drawbacks. That is,
Since the specific resistance is high and the thermal stress is large, the film thickness of the gate electrode cannot be increased so much, so that the sheet resistance of the gate electrode becomes high.

Since the resistance of the gate electrode increases with such a high sheet resistance, the performance of the MESFET cannot be improved.

On the other hand, in order to reduce the gate resistance, it is possible to form a gate electrode composed of two or more layers in which two or more kinds of low resistance metals are laminated.
In this case, there is a problem that processing becomes difficult because the type of metal is different.

Therefore, it is an object of the present invention to provide a gate electrode of a field effect transistor which solves the above problems.

[0008]

In order to solve the above problems, an FET according to the present invention has a gate electrode composed of a plurality of layers made of the same material, and each layer constituting the plurality of layers. Is characterized by including layers in which different residual stresses (stress direction and magnitude of stress) are generated.

In order to solve the above-mentioned problems, the method of manufacturing an FET according to the present invention uses the same material to form a thin film composed of a plurality of layers by adjusting the gas pressure of the surroundings. , And a second step of forming a gate electrode by patterning a thin film, in which different residual stresses are caused in mutually overlapping layers.

[0010]

According to the above construction, the gate electrode of the FET according to the present invention is composed of a plurality of layers each made of the same material. Different residual stresses are generated in the respective layers, and the sum of the stresses of the gate electrode as a whole is 0 or a value close to 0. As a result, even with a material that cannot be made thick due to high specific resistance and large thermal stress, the thickness of the gate electrode can be made thick by forming such a layer, so that the sheet resistance is increased. Can be lowered.

According to the above method, when the thin film used as the gate electrode after patterning is formed, the gas pressure around the thin film is adjusted so that the parts of the thin film which are in contact with each other overlap each other. Since different residual stresses can be generated, the stress of the entire thin film can be brought close to zero. By doing so, the gate electrode can be made thick even with a material having a high specific resistance and a large thermal stress, so that a FET having a reduced sheet resistance can be manufactured.

Further, since this thin film is made of the same material, it is not necessary to change the etching conditions when the thin film is etched to form the gate electrode. Therefore, a thin film composed of a plurality of layers having different properties can be easily formed. It can be formed on the gate electrode.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

A method of manufacturing the MESFET according to the embodiment of the present invention will be described.

First, as shown in FIG. 1A, a resist film 2 is formed on a GaAs substrate 1, and the resist film 2 is patterned by an exposure device or the like. Using the patterned resist film 2 as a mask, 30 KeV of Si is applied to the GaAs substrate 1.
Ion implantation with acceleration energy of.

Next, as shown in FIG. 1B, SiON is deposited on the entire surface of the GaAs substrate 1 by chemical vapor deposition or the like to form a protective film 3 for annealing. Annealing treatment of the GaAs substrate 1 is performed under the temperature condition of 1 to form the conductive layer 4.

Next, after removing the annealing protection film 3 by etching, as shown in FIG. 1C, W (tungsten) is alternately deposited by a sputtering method, and a plurality of stresses applied to the respective layers are different. W consisting of W (tungsten) layer
The thin film 5 is formed. The stress applied to each layer is adjusted by controlling the pressure of Ar (argon) gas used during sputtering. The high frequency power at this time was 200 W. Specifically, the W thin film 5 is formed as follows. First, the pressure of Ar gas in the sputtering chamber is adjusted to 1.5 to 2.5 mtorr, and W is deposited by the sputtering method to form the W layer 5a. Then, the pressure of Ar gas in the sputtering chamber is changed to 4.0 to 5.0 mtorr, and W is deposited by the sputtering method to form the W layer 5b. Then, the pressure of Ar gas is again 1.5 to 2.5 m.
After returning to torr and depositing W by the sputtering method,
After forming the layer 5c, the pressure of Ar gas is further increased to 4.0 to
The W layer is changed to 5.0 mtorr and W is deposited by a sputtering method to form a W layer 5d, thereby forming a W thin film 5 consisting of four layers having a thickness of about 200 nm as a whole.

Next, the Ga thin film on which the W thin film 5 as described above is formed
A resist film is formed on the As substrate 1, and the resist film is patterned by an exposure device or the like. Using the patterned resist film as a mask, the W thin film 5 is processed into a gate shape by reactive ion etching (RIE).
The gate electrode 7 is as shown in (d).

Next, as shown in FIG. 2A, a resist film 8 is formed and patterned, and then Si ⁺ is formed in a desired region.
N ⁺ layer 9 is formed by ion implantation. After that, SiON is deposited again by the chemical vapor deposition method or the like to form the protective film 10 for annealing.
High concentration impurity layer 9 by annealing under the temperature conditions
(Source region and drain region) are formed. The annealing protection film 10 will be used as an insulating film of the MESFET after being formed into a pattern in the next step.

Next, GaAs other than the source and drain regions
A resist film having a predetermined pattern is formed on the substrate 1 and Au is formed.
After vapor deposition of Ge / Ni metal, lift-off is performed,
The alloying process is performed to form the ohmic electrode 11, the predetermined metal wiring 12 is formed, and the manufacturing process of the MESFET is completed.

According to the above-described manufacturing method, since the metal constituting each layer of the W thin film is formed of W, which is the same material, when the W thin film is formed on the gate electrode 7, the same etching is performed. It can be performed under conditions. Therefore, the gate electrode 7 can be easily formed.

According to the above manufacturing method, a MESFET having the following features can be manufactured.

That is, as shown in FIG. 3, the gate electrode 7 is formed of a plurality of layers (four layers in this embodiment), and the stress applied to each adjacent layer is different. . Specifically, the W layer 7a formed in the lowermost stage
Is applied with compressive stress, and tensile stress is applied to the W layer 7b formed in the next layer. Further, compressive stress is applied to the W layer 7d formed thereon, and tensile stress is applied to the W layer 7d formed on the uppermost stage.

In this way, if the W layers having different stress directions are alternately deposited while adjusting the stress applied to each layer,
The stress of the entire W thin film can be brought close to zero. Since a plurality of W layers can be formed, it is possible to thicken a material having high specific resistance and large thermal stress. For this reason,
The sheet resistance can be reduced. Therefore, the resistance of the gate electrode 7 is lowered, and the performance of the MESFET is improved.

Further, it goes without saying that a metal other than W may be used as the metal used for the gate electrode 7. Needless to say, the metal forming the ohmic electrode is not limited to the alloy shown in the present embodiment.

Further, a material different from the W thin film thus formed may be deposited to form a gate electrode.

[0027]

As described above in detail, according to the present invention, the gate electrode of the FET is composed of a plurality of layers each made of the same material. Different residual stresses are generated in the respective layers, and the sum of the stresses of the gate electrode as a whole is 0 or a value close to 0. As a result, even with a material that cannot be made thick due to high specific resistance and large thermal stress, the thickness of the gate electrode can be made thick by forming such a layer, so that the sheet resistance is increased. Can be lowered.

Further, according to the present invention, when forming a thin film used as a gate electrode after patterning in manufacturing an FET, the gas pressure around the thin film is adjusted so that the layers constituting the thin film are mutually Since residual stresses different from each other can be generated in the overlapping portions in contact with, the stress of the whole thin film can be brought close to zero. By doing so, the gate electrode can be made thick even with a material having a high specific resistance and a large thermal stress, so that a FET having a reduced sheet resistance can be manufactured.

When the thin film for forming the gate electrode is made of another kind of material as in the prior art, the etching condition must be changed for each material. Since the thin films for forming the gate electrodes are made of the same material, the thin films can be easily etched under the same etching conditions to form the gate electrodes.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a manufacturing process of a MESFET according to an embodiment of the present invention.

FIG. 2 is an explanatory view showing a manufacturing process of the MESFET according to the embodiment of the invention.

FIG. 3 is an enlarged view of a gate electrode portion of a MESFET according to an exemplary embodiment of the present invention.

[Explanation of symbols]

1 ... GaAs substrate, 5 ... W thin film, 7 ... Gate electrode, 9 ... High concentration impurity layer

Claims (2)

[Claims] 1. A gate electrode comprising a plurality of layers formed of the same material, wherein each layer constituting the plurality of layers includes layers in which residual stress different from each other is generated, The field effect transistor, wherein the sum of stresses in the entire gate electrode is 0 or a value close to 0. 2. A method for manufacturing a field effect transistor, wherein when forming a thin film composed of a plurality of layers using the same material, by adjusting the gas pressure of the surroundings, different layers are brought into contact with each other and overlap each other. Causing residual stress,
A first step of setting the sum of stresses of the entire thin film to 0 or a value close to 0; and a second step of patterning the thin film to form a gate electrode
And a method of manufacturing a field-effect transistor.