JPH06309884A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain such a semiconductor nonvolatile storage device that the fluctuation of the thresholds of its cells becomes smaller after electrons are injected into a charge storage section. CONSTITUTION:This storage device is provided with a memory array 14 in which a plurality of memory cells 12 which store data based on the amount of electrons stored in a charge storage section are arranged in a matrix-like state and a data erasing circuit 24 which erases data stored in the cells 12. The circuit 24 is constituted of an F-N tunnel injection control circuit 26 which is used for injecting the electrons into the charge storage section and an avalanche hot carrier injection control circuit 28 which is used for injecting electrons or holes into the electron storage section in the from of avalanche hot carriers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an EEPROM cell capable of electrically writing data and erasing the data collectively or in block units.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional general batch erase type EE.
PROM (hereinafter abbreviated as flash EEPROM)
3 is a sectional view of the cell of FIG. As shown in FIG. 9, in the semiconductor substrate 131 of p-type silicon, the n-type source diffusion layer 1 is formed.
32 and an n-type drain diffusion layer 133 are formed respectively. A first gate insulating film 135 is formed on the channel region 134 connecting the source diffusion layer 132 and the drain diffusion layer 133. First
The gate insulating film 135 has a film thickness of, for example, about 100 Å. A floating gate 136 is formed on the first gate insulating film 135. Floating gate 13
A second gate insulating film 137 is formed on the substrate 6.
A control gate 138 is formed on the second gate insulating film 137.

Next, the operation of the conventional cell having the above structure will be described in the order of data writing, erasing, and reading. For writing data, a program voltage, for example, -10 V is applied to the control gate 138, and the drain diffusion layer 1
By applying a power supply voltage, for example, 5 V to 33, the electrons accumulated in the floating gate 136 are transferred to the drain diffusion layer 1
It is pulled out to the 33 side by Power-Nordheim tunneling (hereinafter abbreviated as F-N tunneling) and poured out. This operation is performed in 1-bit units.

To erase data, for example, the drain diffusion layer 133 and the source diffusion layer 132 are opened, the semiconductor substrate 131 is grounded, and the control gate 138 is +2, for example.
By applying 0 V, electrons are injected from the semiconductor substrate 131 to the floating gate 136 by FN tunneling,
Erase. At this time, a method called batch or block erasing is usually used to divide the memory on the chip into batches or large blocks to perform high-speed erasing. Further, the normal erasing is completed within 1 second. When erasing at a higher speed, data is not written to all cells before erasing. Therefore, when the erase unit is large, over-erased cells and under-erased cells coexist, and the erase distribution width is also large. It will be big.

Data is read by applying, for example, 5 V to the control gate 138, applying a read voltage, for example, 1 V to the drain diffusion layer 133, and checking the presence or absence of a channel current.

However, if the cells are in an insufficiently erased state, a read malfunction occurs. That is, if the non-selected cell is in the over-erased state, a current flows through the bit line through the cell, so that correct information of the selected cell cannot be read. Further, in the case of a NAND type array in which cells are connected in series, if an overerased cell exists, a read current does not flow, and correct information of the selected cell cannot be read.

As described above, there has been a problem of cell over-erasure in the past. As a countermeasure to solve this problem, a method called intelligent erasing, which repeats "erase-read", has been conventionally used. However, intelligent erase only prevents over-erasing of cells. Therefore, in the case of intelligent erasing, even the variation in the threshold value of the cell after erasing is not taken into consideration. Each cell has variations in the electron injection characteristics due to variations in the film quality of the gate insulating film, etc., but for this reason, the variation in the electron injection characteristics with the injection of electrons results in the cell characteristics after erasing. The threshold value is still varying. Currently, the typical variation in the threshold value of the cell after erasing is about 3 V at the maximum, but in the future, as the ratio of the processing variation to the design value will increase with the progress of miniaturization, the threshold value after erasing will increase. It is expected that the variation of will increase further.

In order to suppress such variations, it is presumed that it is most effective to devise a process and eliminate variations in the film quality of the gate insulating film, for example. No definitive way to prevent this has yet to be established.

[0009]

As described above, in the conventional nonvolatile semiconductor memory device, since the electron injection operation is terminated as it is after the electrons are injected into the floating gate, the threshold voltage of the cell after the electron injection is completed. There was a problem that the variation remained in place.

In order to solve the above-mentioned problems, it is an object of the present invention to provide a non-volatile semiconductor memory device which suppresses the threshold variation of cells after injecting electrons into a charge storage section.

[0011]

In order to solve the above-mentioned object, the present invention has a memory cell having a charge storage portion and storing data by the amount of electrons stored in the charge storage portion, and this memory. A memory cell array in which a plurality of cells are arranged in a matrix, a first means for injecting electrons into the charge storage section, and an electron or a plurality of cells are injected into the charge storage section after electrons are injected by the first injection section. There is provided a non-volatile semiconductor memory device comprising: a second means for injecting holes into avalanche hot carriers; and an erasing means for erasing data stored in the memory cell.

Charges formed on the source region diffusion layer and the drain region diffusion layer formed in the semiconductor substrate and a channel region connecting the source region diffusion layer and the drain region diffusion layer through an insulating film. A storage section, a memory cell formed of a control gate formed on the charge storage section, a memory cell array in which a plurality of the memory cells are arranged in a matrix, and electrons to the charge storage section through the insulating film. A first injecting means for injecting, and a second injecting means for injecting electrons by the first injecting means and then injecting electrons or holes into the charge storage portion via the insulating film by avalanche hot carriers. And a erasing unit for erasing data stored in the memory cell.

[0013]

According to the nonvolatile semiconductor memory device provided by the present invention, for example, after injecting electrons into the charge storage portion, electrons or holes are stored by avalanche hot carrier injection depending on the charge state of the charge storage portion. Injected into the department. There is an equilibrium potential in which the injection of electrons and holes is balanced in the potential state of the charge storage portion. For example, if the charge accumulating portion is charged so as to be higher than the equilibrium potential, electrons are injected, and the charged state changes to the equilibrium potential state. On the contrary, if the charge storage portion is charged so as to be lower than the equilibrium potential, holes are injected, and similarly, the charged state changes to the equilibrium potential state. In either case, the cells converge to a specific equilibrium potential state, and as a result, the threshold value of the cell after electron injection converges to a specific value. Although the convergence value varies due to the variation of the capacitive coupling ratio due to the variation in the processing such as the gate length, in the case of the FN tunneling injection, the value is also influenced by the variation in the quality of the tunnel oxide film. By using the nonvolatile semiconductor memory device having the configuration, it becomes possible to reduce the variation in the threshold value of the cell after electron injection, as compared with the case where only the FN tunneling injection is performed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In this description, common reference numerals are used for common parts throughout the drawings to avoid redundant description.

FIG. 1 is a block diagram showing the overall structure of a flash EEPROM according to an embodiment of the present invention. As shown in FIG. 1, on the chip 10, for example, FIG.
The memory cell 12 (12
_{1 to} 12 _n ) are formed in a matrix.
A portion in which a plurality of memory cells 12 (12 _{1 to} 12 _n ) are integrated and formed in a matrix is referred to as a memory cell array 14. Around the memory cell array 14, a column decoder 16 that selects the bit line BL and a row decoder 18 that selects the word line WL in the memory cell array 14.
Are provided respectively. Further, a mode select circuit 20 for selecting each mode of data writing, data erasing, and data reading is provided. This mode select circuit 20 is used for writing / writing data.
It is connected to the reading circuit 22 and the data erasing circuit 24. The mode select circuit 20 outputs a signal for activating the data write / read circuit 22 when writing / reading data. When erasing data, a signal for activating the data erasing circuit 24 is output. Further, the data erasing circuit 24 uses the Fowler-nordh
It is composed of an eim (hereinafter abbreviated as FN) tunnel injection control circuit 26 and an avalanche hot carrier injection control circuit 28.

Next, with reference to FIGS. 2 and 3, an example of a method of erasing the data of the flash EEPROM by the above-mentioned data erasing circuit 24 will be described. FIG. 2 is a block diagram showing a specific configuration example of the data erasing circuit 24. 3 shows an operation flow of the erase operation control unit 30 included in the configuration example of the data erase circuit 24 shown in FIG.

In the erase operation, first, as shown in FIG. 2, the signal S1 instructing the execution of the erase operation is supplied from the mode select circuit 20 to the data erase circuit 24. Receiving this signal S1, the erase operation control unit 30 is activated and the operation shown in the flow of FIG. 3 is performed.

First, step (hereinafter referred to as ST.) 1
Then, the signal S2 is supplied to the F-N tunnel injection control circuit 26. Upon receiving this signal S2, the FN tunnel injection control circuit 26 is activated. The FN tunnel injection control circuit 26 supplies the erase signal S3 to the memory cell array 14. The erase signal S3 is a signal for setting the gate, source, and drain potentials of the cells integrated in the memory cell array 14 to predetermined potentials so that F-N tunnel injection can be performed. As a result, electrons are injected into the charge storage portion of the cell, for example, the floating gate by FN tunneling.

Next, ST. In step 2, the set time for FN tunnel injection is measured. When the predetermined set time has elapsed, S
T. At 3, the supply of the signal S2 is stopped. Then, ST. At 4, the signal signal S4 is supplied to the avalanche hot carrier injection control circuit 28. Upon receiving this signal S4, the avalanche hot carrier injection control circuit 28 is activated. The avalanche hot carrier injection control circuit 28 supplies the injection signal S5 to the memory cell array 14. The injection signal S5 indicates the gate, source, and drain potentials of the cells integrated in the memory cell array 14, respectively.
This is a signal for setting a predetermined potential so that avalanche hot carriers can be injected. As a result, electrons or holes are injected into the charge storage portion of the cell, for example, the floating gate by avalanche hot carrier injection.
This implantation tunes the threshold of the cell 12 after erasing. By this tuning operation,
The threshold value of the cell which has been varied after the electron injection by F-N tunneling is a certain threshold value (hereinafter, the equilibrium threshold voltage Vth
⁽ Marked as ^* )). As a result, variations in cell threshold value during electron injection are reduced.

Next, ST. At 5, the set time for avalanche hot carrier injection is measured. When a predetermined set time has elapsed, ST. At 6, the supply of the signal S5 is stopped. Through the steps described above, the erase operation of the flash EEPROM according to the present invention is completed.

Next, two specific examples of the erasing operation will be described with reference to their timings with reference to FIGS. 4A to 4C and 5A to 5C. Figure 4 (a)
(C) is a diagram for explaining a first erase operation example. FIG. 4A shows a voltage Vs applied to the source diffusion layer,
A diagram showing the supply timing of the voltage Vg applied to the control gate and the voltage Vd applied to the drain diffusion layer,
FIG. 4B is a diagram showing a state of electron injection by FN tunneling, and FIG. 4C is a diagram showing a state of electron injection by avalanche hot carrier injection. First,
As shown in FIGS. 4A and 4B, the control gate 11
For example, a state of applying +15 V to 5, 5 V to the source diffusion layer 103, 0 V (or open) to the drain diffusion layer 105, and 0 V to the substrate 101 is provided for 100 μsec.
As a result, the electrons e in the channel 107 are transferred to the floating gate 1
Injection into 11 by FN tunneling. Following this operation, as shown in FIGS. 4A and 4C, 8V is applied to the control gate 115 and 0V is applied to the source diffusion layer 103.
A state in which 5 V is applied to the drain diffusion layer 103 is provided for 1 second, for example. As a result, avalanche hot carrier injection occurs from the drain diffusion layer 105 side into the floating gate 111, and electrons e or holes h are injected into the floating gate 111. As a result, the threshold distribution of cells having variations immediately after the injection of electrons by F-N tunneling is re-distributed so as to converge to the equilibrium threshold voltage Vth ^* , and the variations are reduced.

FIGS. 5A to 5C are views for explaining the second erase operation example. FIG. 5A shows a voltage Vs applied to the source diffusion layer and a voltage V applied to the control gate.
g, and the timing of supplying the applied voltage Vd to the drain diffusion layer, FIG. 5B is a diagram showing a state of electron injection by FN tunneling, and FIG. 5C is an avalanche hot It is a figure which shows the state of the injection | pouring of the electron by carrier injection. First, FIGS. 5A and 5B
As shown in, a state in which + 15V is applied to the control gate 115, 0V (or open) is applied to the source diffusion layer 103, the drain diffusion layer 105, and 0V is applied to the substrate 101, respectively,
For example, it is provided for 100 μs. This allows the channel 10
The electrons e in 7 are injected into the floating gate 111 by FN tunneling. Thereafter, as shown in FIGS. 5A and 5C, a state in which 8 V is applied to the control gate 115, 5 V to the source diffusion layer 103, and +0 V to the drain diffusion layer 105 is provided for 1 second, for example. As a result, electrons a or holes h may be injected from the source diffusion layer 103 side to the floating gate 111 by avalanche hot carrier injection. Thus, even if the electrons e or holes h are injected from the source diffusion layer 103 side by avalanche hot carrier injection, redistribution of the threshold value of the cell occurs as in the first operation example.
The variation is also small.

In the above embodiment, the FN tunnel injection control circuit 26 and the avalanche hot carrier injection control circuit 28 are controlled by the erase operation control section 30 provided in the data erase circuit 24. F-N
The tunnel injection control circuit 26 and the avalanche hot carrier injection control circuit 28 can be controlled by the CPU, for example.

The data erasing circuit 24 does not necessarily have to be provided on the same substrate as the memory cell array 14. For example, a program writer is provided with a data erasing function, and data erasing by this function is performed by injecting electrons into the charge storage section as described in the above embodiment, and then by avalanche hot carrier injection into the charge storage section. Alternatively, it may be configured to inject holes.

The flash EEPROM having the above structure has an advantage that variations in threshold voltage of cells after erasing are reduced. In the conventional erasing method, since the implantation is performed only by FN tunneling, the threshold value of the cell after the implantation and erasing varies. In particular, the threshold value after erasing is sensitive to the film quality of the gate insulating film. Further, when the floating gate is made of polysilicon, whether or not the crystal grain boundary is in the tunnel region also causes a variation in the threshold value after implantation, but according to the present invention, F -After N tunneling, tuning operation by avalanche hot carrier injection is performed.
The threshold value varied by F-N tunneling is reduced as much as the threshold value after hot electron injection (normally used in EPROM, in which electrons are injected into a floating gate). This is the equilibrium threshold voltage V
This is because th ^* reflects only the capacitive coupling variation caused by the processing variation like the threshold Vth after the hot electron injection.

In the method of erasing data by selecting the semiconductor substrate and the control gate (word line) as described in the first erase operation example, some cells sharing the control gate are used. Data can be erased in block units by grouping each row into blocks. In such a case, if avalanche hot carrier injection is performed from the drain diffusion layer side, stress is applied only to the selected block diagram. Further, in the case where each block is independent of the source diffusion layer, the non-selected block becomes completely stress-free by performing the avalanche implantation from the source, and the reliability is further improved.

Next, physical phenomena in the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 6 is a diagram for explaining the physical phenomenon described above. FIG. 6A is a diagram showing the gate current of the MOSFET plotted against the gate voltage, and FIG. 6B was used for the test. It is sectional drawing of MOSFET. Figure 6
In (b), reference numeral 108 indicates a gate insulating film, and reference numeral 110 indicates a gate. Figure 6
As shown in (a) and (b), when the source diffusion layer 103 of the MOSFET is grounded and a potential of 6 V, for example, is applied to the drain diffusion layer 105, the drain diffusion layer 105 is formed.
In the vicinity, hot carriers of electrons e and holes h are generated by the avalanche. Both the electron e and the hole h are injected into the gate, but the injection efficiency depends on the gate voltage. The gate voltage has an equilibrium voltage Vg ^{* at} which electron injection and hole injection are balanced. When the gate voltage Vg is lower than the equilibrium voltage Vg ^* , the holes h are predominantly applied to the gate 11
It is injected into 0 and the gate current Ig flows out. On the contrary, when the gate voltage Vg is higher than the equilibrium voltage Vg ^* , the electrons e are predominantly injected into the gate 110, and the gate current Ig similarly flows. When the gate voltage Vg is much higher than the equilibrium voltage Vg ^* , channel hot carriers (electrons because this example is an n-channel MOSFET) are injected into the gate 110, and a gate current Ig flows.

Here, consider such a phenomenon by replacing it with a memory cell. If a floating gate potential seen from the substrate is higher than the equilibrium voltage when a certain control gate voltage is applied to the FN-implanted cell, the above M
Similar to OSFET, avalanche hot
Among the carriers, the electrons e are predominantly injected into the floating gate. As a result, the potential of the floating gate drops, and the potential of the floating gate gradually approaches the equilibrium voltage Vg ^* from the positive direction. On the contrary, when the floating gate of the FN-implanted cell is charged to a voltage lower than the equilibrium voltage when a certain control gate voltage is applied, holes h are predominantly injected into the floating gate. Become so. Therefore, the potential of the floating gate rises, and the potential of the floating gate gradually approaches the equilibrium voltage Vg ^* from the negative direction. Eventually, the cell threshold value also approaches the certain threshold value Vth ^* . That is, the cell threshold voltage at which the floating gate becomes the equilibrium voltage Vg ^{* due} to avalanche hot carrier injection is Vth ^*.
Is. For this reason, Vth ^* is called the equilibrium threshold voltage. Specifically, the equilibrium threshold of the cell viewed from the control gate is Vth c ^* , and the equilibrium threshold when the control gate voltage is 0 V is Vth c ^* _0. If the potential present is Vp, Vth c ^* = Vp +
Vth c ^* ₀ holds. This relationship is shown in FIG.

FIG. 7 is a diagram for explaining the variation of the threshold voltage of the cell according to the present invention. FIG. 7A is a diagram showing the relation between the drain stress time and the threshold value of the cell. FIG. 7B is a sectional view of the memory cell used for the test. As shown in FIGS. 7A and 7B, the cell 12
The source diffusion layer 103 of the
A potential of 6 V, for example, is applied to the V and drain diffusion layers 105. If stress is applied to the drain diffusion layer 105 in this way, the cell 1 is
The threshold value of 2 changes. For example, when stress is applied with the initial threshold voltage Vth int of the cell being about 1.5 V, the voltage drops to about 0.7 V after 1000 msec. Also, the initial threshold value Vth int of the cell is −0.5.
When stress is applied at about V, it rises to about 0.7 V after 1000 msec. That is, it is shown that the cell 12 used in this test has a balanced threshold voltage Vth ^* of about 0.7V.

Thus, for example, the drain diffusion layer 10
5 is stressed, holes h are injected into the floating gate 111 when the initial threshold Vth int is higher than 0.7 V, and when the initial threshold Vth int is low, the holes h are floated. Electrons e are injected into the gate 111, and the cell threshold shifts as the stress application time elapses. The threshold value of the cell is the equilibrium threshold voltage V
converge to th ^* .

Next, consider the case where this cell is erased by FN implantation and the threshold voltage after erase control is distributed from 6.8V to 4.8V. Control gate voltage at the time of reading is 5
At V, cells with a threshold of 4.8 V are defective. However, if stress is applied under the conditions of drain voltage 5V and control gate voltage 5V after F-N implantation, the threshold value is 6.8.
It can be seen that the voltage converges from V to 5.7V and from 4.8V to 5.7V, respectively, and there is no defect at the time of reading 5V.
Further, since the Vth of the overerased cell drops from 6.8V to 5.7V, the shortage of cell current is eliminated in the case of the NAND structure.

FIG. 8 shows a flash EE according to the present invention.
It is a figure which shows the Endurance characteristic of PROM. The horizontal axis represents the number of writing / erasing, and the horizontal axis represents the cell threshold value. In FIG. 8, graph (1) is a graph showing the threshold value after writing, and graph (2) is a graph showing the threshold value after erasing. In this Endurance test, the threshold after erasing the FN tunnel is about 0.
7V, which is the balanced threshold voltage Vth ^* after tuning
A cell having a voltage of about 1.7 V was used.

The erase and write conditions of the Endurance test will be described. First, the erasing condition is that the control gate is +17 V, the substrate is grounded (0 V), and the drain diffusion layer and the source diffusion layer are open for 100 msec. After that, as a tuning operation, the state in which the control gate is 5.5 V, the drain is 6 V, and the source is 0 V is maintained for 0.5 seconds. Further, the write condition is to keep the control gate at −10 V, the drain diffusion layer at 5 V, and the source diffusion layer open for 100 msec. Writing / erasing under these conditions was repeated.

As a result of the Endurance test, as shown in FIG.
Even after reaching ⁵ times, the result was about 0.2 V, which was not a problem in actual use. Therefore, the present invention is directed to the Endu of a cell.
There is little influence on reliability such as rance.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, in carrying out the present invention, the shape of the memory cell does not matter. As an example, in addition to the cell shown in the above embodiment, an erase gate partially overlapping with the floating gate via an insulating film is provided, and by applying a voltage to the erase gate, the insulating film F The present invention can also be applied to a cell in which electrons are injected into a floating gate by -N tunneling. That is, if electrons are injected into the floating gate and then a voltage is applied to the source or drain diffusion layer to inject electrons or holes into the floating gate, avalanche hot carriers are obtained. Obtainable.

In addition to the floating gate, a stacked film of a silicon oxide film and a silicon nitride film is used as a gate insulating film as a charge storage part for storing data, and the interface between these films and the nitride film side are used. Injecting electrons into the spread traps for writing, the so-called “MNOS (Metal Nitri)
de Oxide Semiconductor) ”type.

Further, the initial threshold value Vth int immediately after the F-N tunnel injection is obtained from the balanced threshold voltage Vth ^* obtained when the read voltage is applied to the control gate, as described in the above embodiment. It may be either positive or negative. However, since the electron injection efficiency is better than the hole injection efficiency, in order to speed up the tuning operation, the initial threshold value Vth int is set to a negative direction from this equilibrium threshold voltage Vth ^* so that electron injection occurs. You may set it.

If the voltage to be applied to the source / drain diffusion layer is applied in a pulsed manner, the hole injection efficiency can be improved. Further, in the above embodiment, the injection by F-N tunneling is performed by one operation, but this injection may be performed by using the intelligent erase method. That is, "erase-verify" is repeated until all cells are turned off by the intelligent injection method, and after it is judged that all the cells have exceeded the desired threshold value, tuning using the avalanche hot carrier injection is performed. You may take action.

Further, according to the present invention, ultimately, it is possible to prevent insufficient cell erasing without using the intelligent injection method. This is because even if the cell is in an insufficiently erased state after the FN tunnel injection, electrons are injected into the insufficiently erased cell by avalanche hot carrier injection, and the threshold value can be increased. .

Furthermore, the operation of writing data to the cell before the injection need not necessarily be performed. This operation is performed for a cell in the erased state (state in which electrons are present in the floating gate), when the cell is further erased, the cell is brought into an over-erased state. However, according to the present invention, holes are injected by avalanche hot carrier injection even in a cell in the over-erased state, and the cell can be returned to the non-over-erased state, so that it is not always necessary to write data.

The following erasing method is also within the scope of the present invention. That is, if it is determined that there is no cell that is not sufficiently erased by performing verification after erasing by F-N tunneling, it is determined that there is a cell that is not sufficiently erased without performing the tuning operation using avalanche hot carrier injection. Only in this case, the bit line is detected, a potential is applied to the bit line, and the tuning operation is performed by, for example, avalanche hot carrier injection from the drain diffusion layer side. When such a method is used, the operating current can be reduced.

[0042]

As described above, according to the present invention,
It is possible to provide a non-volatile semiconductor memory device having a small threshold variation of cells after injecting electrons into the charge storage section.

[Brief description of drawings]

FIG. 1 is a flash EEPR according to an embodiment of the present invention.
Block diagram showing the overall configuration of the OM,

FIG. 2 is a flash EEPR according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration example of a data erasing circuit included in the OM;

FIG. 3 is a flowchart for explaining the operation of an erase operation control unit according to an embodiment of the present invention,

FIG. 4 is a diagram for explaining a first erase operation example according to the present invention, in which (a) shows a voltage Vs applied to a source diffusion layer, a voltage Vg applied to a control gate, and a drain portion diffusion layer. The figure which shows the supply timing of the applied voltage Vd, (b) is F
A diagram showing a state of electron injection by N-tunneling,
(C) is a diagram showing a state of injection of electrons or holes by avalanche hot carrier injection,

FIG. 5 is a diagram for explaining a second erase operation example according to the present invention, in which (a) shows a voltage Vg applied to the control gate, a voltage Vs applied to the source diffusion layer, and a voltage applied to the drain diffusion layer. The figure which shows the supply timing of the applied voltage Vd, (b) is F
A diagram showing an electron injection state by N tunneling,
(C) is a diagram showing a state of injection of electrons or holes by avalanche hot carrier injection,

6A and 6B are diagrams for explaining a physical phenomenon according to the present invention, FIG. 6A is a diagram showing a gate current of a MOSFET plotted against a gate voltage, and FIG. 6B is a MOSFET used for the test. And (c) is a control gate voltage Vp at the time of stress in the cell and the equilibrium threshold V of the cell.
a diagram showing the relationship of th c ^* ,

7A and 7B are diagrams for explaining the variation of the threshold voltage of the cell according to the present invention, where FIG. 7A shows the relationship between the drain stress time and the threshold value of the cell, and FIG. 7B shows the test. Cross-sectional view of the memory cell used in

FIG. 8 is a diagram showing Endurance characteristics in the flash EEPROM according to the present invention;

FIG. 9 is a sectional view of a cell of a flash EEPROM in a conventional example.

[Explanation of symbols]

 Reference Signs List 10 chip 12 memory cell 14 memory cell array 24 data erasing circuit 26 F-N tunnel injection control circuit 28 avalanche hot carrier injection control circuit 30 erasing operation control unit 101 semiconductor substrate 103 source diffusion layer 105 drain diffusion layer 107 channel region 109 First gate insulating film 111 Floating gate 113 Second gate insulating film 115 Control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/792 H01L 29/78 371

Claims (10)

[Claims] 1. A memory cell having a charge storage section for storing data according to the amount of electrons stored in the charge storage section, a memory cell array in which a plurality of the memory cells are arranged in a matrix, and the charge First injection means for injecting electrons into the storage section, and second injection means for injecting electrons or holes into the charge storage section after avalanche hot carriers are injected into the charge storage section. And a erasing means for erasing the data stored in the memory cell. 2. The charge storage part is provided on an insulating film formed on a semiconductor substrate, and the first injection means utilizes a tunneling phenomenon to transfer electrons to the charge via the insulating film. An avalanche hot carrier for injecting electrons or holes into the charge storage unit through the insulating film after the second injection unit injects electrons by the first injection unit. Inject and
2. The non-volatile semiconductor memory device according to claim 1, wherein the threshold values of the plurality of memory cells are each made to converge to a specific value. 3. The charge storage section is formed by a floating gate provided on a tunnel insulating film formed on a semiconductor substrate, and the first injection means is provided with Fowlo via the insulating film.
An electron is injected into the charge storage unit by utilizing an r-Nordheim tunnel phenomenon, and the second injection unit injects the electron by the first injection unit and then tunnels into the charge storage unit. 2. An avalanche hot carrier injection of electrons or holes through an insulating film to converge the threshold values of the plurality of memory cells to specific values.
The nonvolatile semiconductor memory device described. 4. The charge storage section is formed by a floating gate provided on an insulating film formed on a semiconductor substrate, and the first injection means excites electrons to cause a barrier of the insulating film. And injecting electrons into the charge storage portion by means of the second injection means, after injecting electrons by the first injection means, electrons or positive electrons are injected into the charge storage portion through the insulating film. Avalanche hot carrier injection into the hole,
2. The non-volatile semiconductor memory device according to claim 1, wherein the threshold values of the plurality of memory cells are each made to converge to a specific value. 5. An erasing circuit comprising a first injection means control circuit for controlling the first injection means and a second injection means control circuit for controlling the second injection means is provided in the memory cell array. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is provided on the same semiconductor substrate. 6. A charge formed through an insulating film on a source region diffusion layer and a drain region diffusion layer formed in a semiconductor substrate, and a channel region connecting the source region diffusion layer and the drain region diffusion layer. A storage section, a memory cell including a control gate formed on the charge storage section, a memory cell array in which a plurality of the memory cells are arranged in a matrix, and electrons to the charge storage section through the insulating film. A first injecting means for injecting, and a second injecting means for injecting electrons by the first injecting means and then injecting electrons or holes into the charge storage portion via the insulating film by avalanche hot carriers. And a erasing means for erasing the data stored in the memory cell. 7. The first injecting means lowers a potential of the source diffusion layer or a potential of the drain diffusion layer lower than a potential of the control gate to allow electrons to pass through the insulating film and the charge storage portion. To the source part diffusion layer or the drain part diffusion layer, and the second injection means causes a potential difference between the source part diffusion layer and the drain part diffusion layer. A control gate potential is generated, and avalanche hot carriers are injected into the charge storage part, in which the electrons are injected, through the insulating film to converge the threshold values of the plurality of memory cells to specific values. 7. The non-volatile semiconductor memory device according to claim 6, wherein 8. The first injecting means makes the electric potential of the control gate higher than the electric potential of the substrate, and injects electrons from the substrate to the charge storage section through the insulating film, The second injecting means causes a potential difference between the source diffusion layer and the drain diffusion layer and a second control gate potential to insulate the charge storage portion into which the electrons are injected. 7. The non-volatile semiconductor memory device according to claim 6, wherein avalanche hot carrier injection is performed through the film to converge the threshold values of the plurality of memory cells to specific values. 9. A first injection means control circuit for controlling the first injection means for setting the potential of the source part diffusion layer or the potential of the drain part diffusion layer lower than the potential of the control gate, and the first injection part control circuit. Second injection for controlling the second injection means for generating a potential difference between the source diffusion layer and the drain diffusion layer and generating a second control gate potential higher than the control gate potential at the time of data reading. 8. The non-volatile semiconductor memory device according to claim 7, wherein an erasing circuit including a means control circuit is provided on the same semiconductor substrate as the memory cell array. 10. A first injection means control circuit for controlling the first injection means for setting the potential of the control gate higher than the potential of the substrate, and the source part diffusion layer and the drain part diffusion layer. An erasing circuit comprising a second injection means control circuit for controlling the second injection means for generating a second control gate potential higher than the control gate potential at the time of data reading, 9. The non-volatile semiconductor memory device according to claim 8, which is provided on the same semiconductor substrate as the cell array.