JPH06309280A - Keyboard system - Google Patents

Abstract

PURPOSE:To provide a keyboard system in which a power uselessly spent during the time not in use can be sharply reduced without affecting an operation during the time in use. CONSTITUTION:This system is equipped with a key matrix 102 in which plural key switches are arranged like a matrix, microprocessor 101 exclusively used for detecting inputs to the key switches of the matrix, and circuit 105 for supplying a driving clock signal to the processor. Also, the system is equipped with a means which measures a time since the last key input is performed, and a circuit 103 which always detects the presence or absence of the key input. The key input detecting operation is continuously operated during a normal time, and when the key input is not performed in a fixed time, the microprocessor 101 is changed to a low power consumption state, and when the key input is performed in the pertinent state, the microprocessor 101 is restored to the normal state, and the key input detecting operation is resumed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a keyboard system.

[0002]

2. Description of the Related Art Keyboards are now indispensable as input devices for computer systems.
Electrical means is generally used as a key input detection means, and when there are many keys for computer systems, both lines are connected to the intersections of the scanning lines and detection lines arranged in a matrix. There are many methods of arranging key switches so that they can be used.

The key input detection method will be described with reference to FIG. In FIG. 14, 1401, 1402, 1403,
Reference numeral 1404 denotes scan lines, 1405, 1406, 140.
Reference numerals 7 and 1408 denote detection lines pulled up. The scanning line is normally kept at the H level, and only one of these lines is sequentially set at the L level. When the key switch 1409 on the scan line 1402 set to the L level is pressed, the scan line 1402 and the detection line 1407 are conducted via the key switch 1409, and the detection line 1409 changes from the H level to the L level. Transition. By detecting this change, it is detected that the key switch 1409 at the intersection of the scanning line 1402 which is at the L level at that time and the changed detection line 1407 is pressed.

In most general-purpose computer systems, since the main CPU performs the key input detection processing, it affects the original processing execution, and therefore is equipped with a keyboard-dedicated microprocessor. The microprocessor has one CPU, RAM, ROM, etc.
A one-chip microcomputer contained in the C chip is often used to perform key input detection operation, key code acquisition and communication operation with the main system.

[0005]

In the case of a desktop type general-purpose computer which uses an AC power source, which has been widely used in the past, power consumption did not cause a big problem. However, with the recent spread of portable personal computer systems, low power consumption technology for computer systems has become important for the purpose of extending battery life.

Considering the frequency of use of a keyboard in a general-purpose computer system, it cannot be said to be high except for special applications such as games. For example, there are many cases where the keyboard is not used for a long period of time, such as the time when thinking about sentences when inputting a word processor, and the time when waiting for a result at the time of technical calculation. However, in the conventional system, the keyboard always continues the key input detection operation even when these are not used, and the power for that purpose is continuously consumed.

It is an object of the present invention to provide a keyboard system which does not affect the operation during use and which reduces the electric power wasted conventionally when not in use.

[0008]

In order to solve the above-mentioned problems, the keyboard system of the present invention has means for continuously performing a key input detection operation in a normal time and measuring a time from the last key input. Provided, when the value reaches a specified value, the microprocessor is moved to a low power consumption state, a means for detecting the presence or absence of a key input in the low power consumption state is provided, and if a key input is made, It is characterized by having a structure for returning to the normal state and restarting the key input detection operation.

[0009]

[Embodiment 1] FIG. 1 shows the basic configuration of a keyboard system of the present invention. In terms of hardware, a microprocessor 101, a key matrix 102, and an oscillation circuit 105 are provided as in the conventional keyboard system. In addition, N of all detection line arrays 107 is a characteristic of the system of the present invention.
A NOR circuit 103 that takes an OR is provided. In FIG. 1, φclk0 indicates a clock signal, φkb indicates an interrupt signal by keyboard input, and φrst indicates a reset signal from the main system.

During normal operation, the microprocessor 101 sequentially sets one of the scanning line arrays 106 to the L level to perform a key input detection operation, and constantly measures the time since the key was last pressed. When the time reaches the specified value, the keyboard system shifts to a low power consumption state (hereinafter abbreviated as sleep mode).

FIG. 2 shows a flowchart of a part mainly related to the sleep mode in the software programmed in the microprocessor 101. In the software shown in FIG. 2, the time since the key was last pressed is measured using a parameter called a sleep counter. This is a method in which the parameter is decremented by 1 for each cycle from the specified initial value, and when the value becomes 0, the mode switches to sleep mode. If there is a key input during the operation, the counter is reset to the original value. To be done. As another measuring means, a method of using a timer interrupt or the like possessed by the one-chip microcomputer can be considered.

At the time of transition to the sleep mode, the microprocessor 101 sets all the scan line columns 106 to the L level. This is a means for detecting the presence or absence of a key input in the sleep mode. That is, as a result, no matter which key is pressed next time, the input becomes an interrupt signal to the microprocessor, and the sleep mode is restored.

Subsequently, the microprocessor issues an interrupt wait instruction, and the microprocessor itself enters an interrupt wait state. Interrupt waiting instructions are represented by mnemonics such as HLT and STOP, and recently, most microprocessors have come to support this type of instruction. When the instruction is issued, the processor stops executing the instruction and shifts to a loop state waiting for an interrupt. During this time, no access to the memory or external I / O is performed and the power consumption of the processor is reduced. As the name implies, the return from the interrupt standby state is performed by inputting an interrupt signal to the NMI or RST terminal. When an interrupt signal is input to the RST terminal, the processor returns from the interrupt standby state and at the same time enters the reset state to start the programmed initialization process.

When using a microprocessor that does not support interrupt wait instructions, programming the processor in an infinite loop state consumes the least power in sleep mode. However, since the general infinite loop always accesses the memory for program execution, it consumes much more power than the interrupt wait loop by the interrupt wait instruction.
It is recommended to use a microprocessor that supports the interrupt wait instruction because the effect of power saving in the sleep mode is weakened.

Next, returning from the sleep mode will be described. As described above, all the scan lines are set to the L level in the sleep mode. Therefore, if any key is pressed in this state, the output of the NAND circuit 103 is inverted from the L level to the H level. It becomes an interrupt signal to the microprocessor.

When a return from sleep mode is made by a key input, the microprocessor immediately restarts the key detection operation and specifies the pressed key. If a lot of time is spent on this operation, key input may not be performed smoothly, which may make the user uncomfortable, or may cause trouble such as short key presses causing no key input. .

In the keyboard system of the present invention, as shown in the flow chart of FIG. 2, the process after returning to the normal key detection operation is only to reset the counter, which consumes an extra time of at most several microseconds. Only.

Since the time for which a person presses a key switch with one key input is generally on the order of several tens of milliseconds, the time spent for returning from the sleep mode does not matter at all. It can be seen that the key input is the same as in normal operation.

[0019]

Second Embodiment Most microprocessors are currently composed of completely static CMOS, and their power consumption is proportional to the driving frequency. In the keyboard system of the first embodiment, in the sleep mode, the microprocessor is in an interrupt wait loop state, and does not perform any operation to the outside in this state, so the driving frequency of the processor may be reduced. . Further reduce power consumption by reducing the frequency of the clock signal supplied to the processor in the sleep mode.

The basic configuration of the keyboard system in this embodiment is shown in FIG. In FIG. 3, 301 is a microprocessor, 304 is a frequency control circuit, φclk0 is an original clock signal, φclk1 is a drive clock signal supplied to the processor, and φfrq is a frequency control signal.

A software flow chart for the sleep mode is shown in FIG. Microprocessor 301
After setting all the scan line columns 306 to the L level,
A frequency reduction command is transmitted to the frequency control circuit 304, an interrupt wait command is issued, and the device itself enters the interrupt wait state. Frequency control circuit 304 that has received the frequency reduction command
Immediately reduces the frequency of the drive clock signal φclk1 supplied to the microprocessor.

When any key is pressed in the sleep mode, the NAND circuit 30 is activated as described in the first embodiment.
The output of 3 is inverted from the L level to the H level and becomes the keyboard interrupt signal φkb for returning from the sleep mode. The interrupt signal φkb is transferred to the clock signal control circuit together with the microprocessor. .

As shown in the flow chart of FIG. 4, this interrupt causes the microprocessor 301 to be programmed to start the key detection operation again. However, in order to perform this operation normally, the clock that has been reduced during sleep is used. The frequency of the signal φclk1 must be immediately returned to its original value by an interrupt.

A circuit example of the frequency control circuit 302 is shown in FIG. In FIG. 5, reference numeral 501 is a frequency dividing circuit, and 502 and 503.
Is a rising edge operation D-type flip-flop, 504 and 508 are OR circuits, and 505, 506 and 5
Reference numeral 07 represents an AND circuit, and 509 represents an inverter circuit. A timing chart of the circuit of FIG. 5 is shown in FIG. From FIG. 6, the numbers are used to indicate each state. It is assumed that the frequency dividing circuit in the circuit of FIG. 5 is 1/4 frequency dividing.

The operation of the circuit of FIG. 5 will be described with reference to the timing chart of FIG. Normally, .phi.frq is fixed to the L level, .phi.2, .phi.3 and .phi.4 are also at the L level regardless of the presence or absence of the key input, and the output clock signal .phi.clk1 is equal to the original clock signal .phi.clk0.

When shifting to the sleep mode, the frequency reduction command from the microprocessor is the frequency control signal φfrq.
Is set to H level. Control signal φ
When frq becomes H level, the φ2 signal becomes H level, and at the same time, the set state of the flip-flop 502 is released, and the preparation for waiting for the interrupt input of the key input signal φkb and the reset signal φrst is completed (state in FIG. 6). Since the flip-flop 503 outputs the value of the φ2 signal as the φ3 signal in synchronization with the falling edge of the divided clock signal φ1, the output clock is output at the next falling edge of the φ1 signal where the frequency reduction command is issued. Signal φc
The frequency of lk1 is reduced (state in FIG. 6).

When a key input is made in the sleep mode, the frequency of the clock signal φclk1 supplied to the microprocessor must be immediately returned to the original value. For this purpose, the frequency is restored by the control signal φfr.
Instead of being done by software by q, keyboard interrupt signal φkb or reset signal φrs
It must be done in hardware instantaneously by t interrupt.

In the circuit of FIG. 5, a keyboard input signal φ
When the kb or the reset signal φrst is inverted from the L level to the H level, the φ2 signal becomes the L level regardless of the value of the control signal φfrq (FIG. 6-), and the clock signal φ
Clock signal φ synchronized with the next falling edge of 1
clk1 returns to the original frequency (FIG. 6-). The frequency control signal φfrq is reset in preparation for the next shift to the sleep mode after returning from the sleep mode as shown in the flowchart of FIG. 4 (FIG. 6-).

When switching the frequency of the clock signal, it is necessary to pay attention to the phase of the clock signal. If the clock signal is switched at any phase, the clock signal waveform may switch during the level transition, or the width of the output clock signal may become extremely short or long. sell. Due to this, there is a risk that the operation of the microprocessor becomes unstable and a data error occurs or a large current flows.

In order to avoid these situations and to switch the clock signals safely, the present invention synchronizes the signal φ2 for switching control with the clock signal φ1 in the flip-flop 503 when switching the clock signals. It has a structure for switching the frequency according to the resulting signal. As a result, the switching of the clock signal frequency in the frequency control circuit is always performed with the clock signal width guaranteed at a constant phase.

In the keyboard system of this embodiment, since the clock signal frequency is completely restored by hardware, the time required from key input to clock re-output is divided by the maximum frequency required for synchronization. It is only one clock cycle of the clock signal, and the processing by software after returning to the normal key detection operation is only resetting the frequency control signal and the counter as shown in the flowchart of FIG. Therefore, the key input in the sleep mode is almost as fast as in the normal state, and the usability similar to that of the conventional keyboard can be realized.

[0032]

Third Embodiment In the keyboard system described in the second embodiment, the lower the frequency of the clock signal supplied to the microprocessor in the sleep mode is, the lower the power consumption is. However, in practice, when an extremely low frequency is used, the scale of the frequency dividing circuit becomes very large and it takes time to return from the sleep mode. As a method of solving these problems and further reducing the power consumption, there is a method of completely reducing the frequency of the clock supplied to the microprocessor in the sleep mode.

The basic configuration of the keyboard system in this embodiment is shown in FIG. The frequency control circuit 304 shown in FIG. 3, which is the basic configuration of the second embodiment, is replaced with a clock signal control circuit 704. At the time of transition to the sleep mode, the microprocessor 701 uses the clock signal control circuit 704.
To the clock signal φc
The supply of lk1 to the microprocessor 701 is stopped.

A software flow chart for the sleep mode is shown in FIG. The software is the same except that the frequency reduction command in the flowchart of FIG. 4 of the second embodiment is changed to the clock signal stop command. In the second embodiment, the microprocessor 3 is controlled by the frequency reduction command.
The frequency of the clock signal φclk1 supplied to 01 is reduced, and the processor 301 has a structure to execute the next interrupt waiting instruction at the reduced driving frequency.

On the other hand, in the flow chart of FIG. 8, when the supply of the clock signal is immediately stopped by the clock signal stop instruction, the operation of the microprocessor 701 is stopped in that state, and the next interrupt wait instruction is executed. I can't.

The microprocessor reads the software from the memory and executes it in the CPU. However, if the clock signal is stopped while the processor is accessing the memory, the chip select terminal of the memory is fixed to the active state. Therefore, the memory is kept in the operating state, and a large current flows. The clock signal must be stopped without access to the processor memory or external I / O.

It is effective to use the above-described interrupt wait instruction to create this state. After executing the interrupt wait instruction, the memory of the processor is not accessed at all until the next interrupt, so stopping the clock signal in this state can safely reduce the power consumption of the microprocessor. Is.

As shown in the flow chart of FIG. 8, the clock signal stop command from the microprocessor 701 is issued before the interrupt wait command. Clock signal φc
Since the stop of lk1 must be performed after the interrupt wait instruction, the clock signal control circuit 704 provides a certain waiting time after receiving the clock signal stop instruction,
It is necessary to have a structure for stopping the clock signal φclk1.

The longer this waiting time is, the safer it is,
Therefore, it takes time until the supply of the clock signal is stopped, and power is wasted. In the keyboard system of the present invention, the minimum required waiting time is measured,
The microprocessor 701 has a structure for stopping the supply of the clock signal φclk1 without a redundant waiting time after shifting to the interrupt waiting state.

FIG. 9 shows a circuit example of the clock signal control circuit 704 in the keyboard system of this embodiment. Figure 9
Numeral 901 indicates a rising edge operation counter having a reset function, and numerals 902, 903 and 904 indicate rising edge operation flip-flops having a set function. A counter 901 is used to measure the waiting time in the circuit of FIG.

How long it takes from the issuance of the clock signal stop command until the processor finishes shifting to the interrupt standby state depends on the software configuration.
FIG. 11 shows an example of actual mnemonics from the clock stop command to the interrupt wait command. In FIG. 11, the number of cycles after; indicates the number of clock signal cycles required for executing each instruction in the microprocessor. In the example of FIG. 11, the maximum number of clock signal cycles required for the processor to enter the interrupt standby state after the clock stop command is issued is 6 cycles at maximum. Therefore, in order to stop the clock safely without redundant waiting time, the clock signal control circuit may stop the clock after receiving the clock stop command and delaying the clock signal by 7 cycles.

The operation of the circuit of FIG. 9 will be described with reference to the timing chart of FIG. From FIG. 10, numbers are used to indicate each state. Normally, the clock control signal φstop is fixed to the L level, and the counter 90
1 is in a stopped state, φ2 is L level, φ3 and φ4
Is at the H level, and the output clock signal φclk1 continues to be continuously output.

When shifting to the sleep mode, the clock stop command from the microprocessor is the clock control signal φsto.
This is transmitted by setting p to H level. When the control signal φstop goes high, the counter 901 is released from reset and starts counting operation (FIG. 10-).
Now, the counter 901 operates on the rising edge and outputs a clock signal of 1 pulse for every 7 pulses of the input clock signal. Such an integer measuring counter can be easily constructed by using, for example, a standard CMOS IC 74HC161 or the like.

After measuring the specified pulse, the φ1 signal rises, and the rising edge causes the φ3 signal to become L level (FIG. 10-). The flip-flop 904 is provided as a synchronizing circuit for stopping and re-outputting the clock signal in synchronization with the original clock signal. As in the second embodiment, by stopping and re-outputting the clock signal in synchronization with the original clock signal, these operations are guaranteed to be performed safely. The value of the φ3 signal appears as the φ4 signal in synchronization with the falling signal of the original clock, and when the φ4 signal becomes the L level, the supply of the clock signal to the microprocessor is stopped. (FIG. 10-).

In the example described above, as can be seen from the timing chart of FIG. 10, a delay of exactly 7 pulses of the clock signal occurs from the time the microprocessor issues a clock signal stop command until the clock signal stops. Therefore, it can be seen that the ideal power reduction is achieved in which the supply of the clock signal is stopped immediately after the microprocessor enters the interrupt waiting state.

The return from the sleep mode is caused by a keyboard input or a reset signal as described in the second embodiment, and is instantaneously performed by hardware by these interrupts. The maximum time required from key input and reset signal to clock re-output is the original clock signal 1
Since the clock control signal and the counter are reset as shown in the flow chart of FIG. 8, the key input operation is performed in the same manner as the normal operation.

[0047]

[Embodiment 4] Currently, most of the one-chip microcomputers can operate even at a low voltage of about 2V, and the power consumption at that time is much lower than that during normal 5V operation. However, if only the keyboard system is driven at low voltage,
To reduce the power supply voltage of the normal keyboard system because a level conversion circuit is required for communication with the main system, and the drive frequency is limited when driving at low voltage, and a sufficient operating speed cannot be expected. Has a problem.

However, since communication with the main system is not performed in the sleep mode and it is not necessary to operate at a high clock frequency, it is effective to reduce the power supply voltage to reduce power consumption.

The basic configuration of the keyboard system in this embodiment is shown in FIG. In FIG. 12, 1204 is a voltage control circuit, φvcc is a voltage control signal, and Vout is a power supply voltage supplied to the entire keyboard system such as the microprocessor and the oscillation circuit.

The mechanism for lowering the power supply voltage when shifting to the sleep mode is almost the same as the method for reducing the clock frequency described in claim 2. Upon entering the sleep mode, the microprocessor 1201 sets all the scanning line columns 1206 to the L level, then transmits a power supply voltage reduction command to the voltage control circuit 1204, issues an interrupt standby command, and enters the interrupt standby state itself.

FIG. 13 shows a circuit example of the voltage control circuit 1204. In FIG. 13, reference numeral 1301 denotes a step-down circuit 1302.
And 1303 are diodes for backflow prevention, 1304 is an analog switch, 1305 is a capacitor, and Vhigh is
h indicates a power supply voltage in a steady state, and Vlow indicates a low voltage. The voltage drop command from the microprocessor at the time of transition to the sleep mode is transmitted by setting the voltage control signal φvcc to the H level. At the same time that φvcc becomes H level, the output of 1306 also becomes H level, and the analog switch 1304 switches.

The step-down circuit 1301 produces a low voltage from Vcc, and a DC-DC converter or a three-terminal regulator can be used. The capacitor 1305 is provided to prevent a decrease in Vout at the time of switching, and the larger the value, the more stable the slow switching. On the other hand, the time constant of the change in Vout when the switch is switched is determined by the product of this capacitor 1305 and the input resistance on the keyboard system side. Regardless of the transition to the sleep mode, it is required to return to the steady voltage before the communication with the main system is resumed at the time of restoration. Therefore, the smaller the value of the capacitor 1305, the better. It is necessary to select the value of the capacitor 1305 in consideration of these matters. .

The return from the sleep mode is similar to the method described in the second embodiment, and the return of the power supply voltage to the original value is performed by hardware by the keyboard input φkb or the reset signal φrst, and then the φvcc The value is reset in preparation for the next sleep mode transition.

By reducing the power supply voltage, the operable frequency of the microprocessor is lowered and the original clock signal φ
At 0, a situation in which driving cannot be performed may occur. In this case, it is possible to deal with the problem by reducing the frequency of the clock signal supplied to the microprocessor by combining the present embodiment with the second or third embodiment.

EFFECTS OF THE INVENTION By using the keyboard system of the present invention, it is possible to realize a feeling of use that is completely the same as the conventional one and to suppress the power consumption when not in use to an extremely low level.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a flowchart of software in the first embodiment.

FIG. 3 is a block diagram of a second embodiment.

FIG. 4 is a flowchart of software according to the second embodiment.

FIG. 5 is an example of a circuit diagram of a frequency control circuit.

FIG. 6 is a timing chart of the circuit of FIG.

FIG. 7 is a block diagram of a third embodiment.

FIG. 8 is a flowchart of software according to the third embodiment.

FIG. 9 is an example of a circuit diagram of a clock signal control circuit.

10 is a timing chart of the circuit of FIG.

FIG. 11 is an example of a software mnemonic when shifting to a sleep mode.

FIG. 12 is a block diagram of a fourth embodiment.

FIG. 13 is an example of a circuit diagram of a voltage control circuit.

FIG. 14 is an explanatory diagram of a key input detection method.

[Explanation of symbols]

 101 Microprocessor 102 Key matrix 105 Oscillation circuit 304 Frequency control circuit 704 Clock signal control circuit 1204 Voltage control circuit φclk0 Original clock signal φclk1 Drive clock signal supplied to the processor φkb Keyboard interrupt signal φrst Reset signal φfrq Frequency control signal φstop Clock control signal φvcc voltage control signal

Claims (4)

[Claims] 1. A plurality of key switches arranged so that both lines can be conducted at each intersection of a scanning line and a detection line arranged in a matrix, and an input to the key switch is detected. Therefore, in a keyboard system including a dedicated microprocessor and a circuit for supplying a drive clock signal to the processor, a means for measuring the time after the last key input is made, and the presence or absence of constant key input is detected. Means for continuously performing a key input detection operation in a normal time, when the key input is not made for a certain period of time, the microprocessor shifts to a low power consumption state, and when the key input is made in the state, A keyboard system having a structure for returning to a state and restarting a key input detection operation. 2. The keyboard system according to claim 1, further comprising a circuit for controlling a frequency of a clock signal for driving the microprocessor, wherein the frequency of the drive clock signal is lowered at the time of transition to a low power consumption state, and key input is performed in the state. A keyboard system characterized by having a structure for immediately returning the frequency to the original value and restarting the key input detection operation when made. 3. The keyboard system according to claim 1, further comprising a circuit for controlling the supply of a clock signal for driving the microprocessor, which is driven after the microprocessor has made no access to a memory or the like when transitioning to a low power consumption state. A keyboard system comprising a structure for stopping the supply of a clock signal, and when a key input is made in this state, immediately restarts the supply of the clock signal and restarts the key input detection operation. 4. The keyboard system according to claim 1, further comprising a circuit for controlling a power supply voltage supplied to a microprocessor and a clock supply circuit, wherein the value of the power supply voltage is lowered at the time of transition to a low power consumption state, and key input is performed in that state. A keyboard system having a structure for returning the power supply voltage to the original value and restarting the key input detection operation when the operation is performed.