JPH07295694A - Power saving method for arithmetic processor - Google Patents

Abstract

PURPOSE:To extend a battery actuation time by reducing the power consumption when a multitask OS is used. CONSTITUTION:A conventional method executes an idle task when there is no task to be run, and this idle task becomes an endless loop of NOP instructions, but this method replaces the endless loop of NOP instructions with an instruction (e.g. HALT instruction) for placing a CPU 19 in power- saving mode, thereby reducing the power consumption. In the power-saving mode, the CPU 19 stops operating and the power source of a device except a part which is required to reset the mode is stopped by the CPU itself. The CPU exits from the power-saving mode by external interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving method for an arithmetic processing unit.

[0002]

2. Description of the Related Art When a multitasking OS is used as an OS for operating an arithmetic processing unit (hereinafter referred to as CPU),
If there is no task to move (idle state), normally O
S starts an idle task. This is generally shown in FIG.
As shown in (4), it is composed of an infinite loop of instructions that do not process anything (for example, NOP instruction).

The execution of the idle task is not continuously executed until the scheduling at the next periodic interrupt. That is, the idle task is a task scheduled only in the idle state.

Generally, not only idle tasks but ordinary tasks are running in an interrupt enabled state. Therefore, if an interrupt (other than a periodic interrupt) occurs during task activation, the interrupt processing program corresponding to the interrupt factor is executed, and the task returns to the original task after completion.

[0005]

As described above, in the conventional multi-task OS, the idle task is activated in the idle state, and power is wasted.

It is an object of the present invention to provide a power saving method for an arithmetic processing unit that enables power saving under a multitasking OS.

[0007]

In order to solve the above-mentioned problems, the present invention has a CPU having a power saving mode, an interval timer section for periodically interrupting the CPU, and whether to follow instructions from the CPU or to itself. A peripheral I / O circuit that controls input / output with peripheral devices and collects data and interrupts the CPU, and an interrupt controller that controls interrupts from the interval timer unit and peripheral I / O circuit according to their priority. When the multi-tasking is realized in the device that has it according to the interruption by the interval timer unit, the CPU is set to the power saving mode when there is no task to run.

[0008]

With the above structure, the present invention can realize power saving by setting the CPU in the power saving mode in the idle state under the multitasking OS.

[0009]

EXAMPLE An example of the present invention will be described below. FIG. 2 is a minimum hardware configuration diagram for realizing an internal configuration of a CPU (arithmetic processing unit) and a multitasking OS using the CPU. Reference numeral 19 is a CPU. The configuration of the CPU 19 will be described below. Reference numeral 20 is an ALU for performing numerical operations and logical operations, 22 is an address bus, and 21 is an address bus control circuit for controlling the address bus. Again 24
Is a data bus, and 23 is a data bus control circuit for controlling the data bus. The instruction read from the data bus 24 is input to the instruction decoder 26 via the instruction register 25, and according to the analyzed result, the control signal generator 27
Various internal controls are performed by issuing a command to. 28 is an external interrupt control circuit for external interrupt,
Reference numeral 29 is a control bus control circuit for controlling WR and RD signals, and 30 is a power supply control circuit. The above is the CPU 19
It is the structure of.

Reference numeral 31 is a ROM, 32 is a RAM, and 33 is an external power source. Reference numeral 40 is an interval timer for periodically (T in FIG. 1) interrupt. Reference numeral 41 is a peripheral input / output circuit including an input / output circuit 42 and a power supply control circuit 43. The peripheral input / output circuit 41 will be described below.

The peripheral input / output circuit 41 is connected to the CPU 19 via an address bus and a data bus, and the peripheral circuits are controlled via these buses. In addition, peripheral input / output circuit 4
1 can generate interrupts such as reception interrupts,
The interrupt output terminal is input to the interrupt controller 44 together with the interval timer 40. Interrupt controller 44
Interrupts the CPU 19 according to the priority order of various interrupts. The interrupt factor is that when the interrupt occurs, the data bus 24
Is put on.

When the OS detects an interrupt, it checks the interrupt factor and, if the interrupt is a periodic interrupt, performs a task switching process (scheduling). The data referred to in the scheduling process is a memory that stores the activation order of pre-registered tasks (this is called a queue). This scheduling processing is performed not only for periodic interrupts but also when the task itself gives up the execution right.

FIG. 1 is an explanatory diagram showing task scheduling of the power saving method in this embodiment. Hereinafter, a specific description will be given based on the drawings.

First, the OS schedules the task by abandoning the execution right of the task itself or by periodically interrupting the task. As an example, three tasks A, B, under the control of the OS
Suppose there is C. T is the cycle of the cycle interrupt from the interval timer. Further, in this example, it is assumed that the idle state was not entered in the first cycle 1.

It is now assumed that task A is running (1).
Here, when the task A makes a monitor call of the OS in order to abandon the execution right, control is transferred to the OS (2) and the next task B to be activated is activated (3). This is called scheduling. That is, the scheduling is a process of searching a task that moves after the task A from the queue and activating the task.

Similarly, when task B gives up the execution right,
Scheduling is performed by the OS (4), and task C is activated (5).

Even if the task C does not relinquish the execution right by the cycle T of the cycle interrupt, if the cycle interrupt occurs, the OS
Control is transferred to (6) and scheduling is performed.
In this case, since it is a periodic interrupt during execution of task C, task C is continuously executed in the next period 2 (7).

In cycle 2, after the execution right of task C is abandoned, task A is activated in the same procedure as the previous timing.
Here, it is assumed that there is no task running after the execution right of the task A is abandoned (that is, the idle state).

In the conventional method, the idle task is executed thereafter, and this idle task becomes an infinite loop of NOP instructions as shown in FIG. 6, but in the embodiment of the present invention, the NOP instruction is infinite as shown in FIG. Low power consumption is realized by replacing the loop with an instruction (for example, a HALT instruction) that puts the CPU 19 in the power saving mode (8). In the power saving mode, the CPU 19 stops its operation,
The CPU itself has stopped the power supply of the device other than the part necessary for releasing the mode. Exit from the power saving mode is performed by an external interrupt. The response to the interrupt in the power saving mode and the response to the interrupt in the non-power saving mode may be slightly different, but they can be almost ignored.

The peripheral input / output circuit 41 shown in FIG.
Is connected to the CPU 19 via an address bus and a data bus, and the power supply to the peripheral circuits can be turned off by issuing an instruction via these buses. If the CPU 19 does not have a power saving mode,
The NOP instruction cannot be replaced with the HALT instruction, but instead, low power consumption is realized by turning off unnecessary peripheral input / output circuits before entering the infinite loop as shown in FIG.

Further, as shown in FIG. 5, the CPU 19 is set in the power saving mode and the peripheral circuits are powered off, so that the power consumption can be further reduced.

During the power saving mode of the CPU 19, since interrupts are generally permitted, it is possible to execute the interrupt processing program as indicated by reference numeral 4, and there is no omission of processing. When an interrupt occurs during the power saving mode, the power saving mode is exited and the OS performs scheduling.

[0023]

As described above, according to the present invention, when multitask is realized according to the interruption by the interval timer unit, the multitask OS is used by setting the CPU to the power saving mode when there is no task to run. This is an invention that can realize power saving in the above device, and is particularly useful in a battery-driven device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing task scheduling of a power saving method according to an embodiment of the present invention.

FIG. 2 is a minimum hardware configuration diagram for realizing a multitasking OS using an arithmetic processing unit according to an embodiment of the present invention.

FIG. 3 is a flowchart of a power saving method according to an embodiment of the present invention.

FIG. 4 is a flowchart of a power saving method according to an embodiment of the present invention.

FIG. 5 is a flowchart of a power saving method according to an embodiment of the present invention.

FIG. 6 is a flowchart of an idle state of a device using a conventional multitasking OS.

[Explanation of symbols]

 8 Execution of power saving mode 9 Activation of interrupt handler in power saving mode 19 CPU 20 ALU 21 Address bus control circuit 22 Address bus 23 Data bus control circuit 24 Data bus 25 Instruction register 26 Instruction decoder 27 Control signal generator 28 External percent Embedded control circuit 29 Control bus control circuit 30 Power supply control circuit 31 ROM 32 RAM 33 External power supply 40 Interval timer 41 Peripheral input / output circuit 42 Input / output circuit 43 Power supply control 44 Interrupt controller

Claims (3)

[Claims] 1. An arithmetic processing unit having a power saving mode, an interval timer section for periodically interrupting the arithmetic processing unit, and an input / output of a peripheral unit by following instructions from the arithmetic processing unit. In a device having a peripheral input / output circuit which controls and interrupts the data processing and arithmetic processing device, and an interrupt controller unit which controls the interrupts from the interval timer unit and the peripheral input / output circuit according to their priority order, etc. A power-saving method for an arithmetic processing unit, characterized in that, when multitasking is realized according to an interrupt by the interval timer unit, the arithmetic processing unit is put into a power-saving mode when there is no task to run. 2. An arithmetic processing unit that does not have a power saving mode, an interval timer unit that periodically interrupts the arithmetic processing unit, and an instruction input from the arithmetic processing unit, or an input of a peripheral device by itself. It has a peripheral input / output circuit that controls output and interrupts data collection and arithmetic processing devices, and an interrupt controller that controls the interrupts from the interval timer and the peripheral input / output circuits according to their priority order. In the device, when multitasking is realized according to the interruption by the interval timer unit, unnecessary power supply to the peripheral input / output circuit is turned off when there is no task to be run, and a power saving method for the arithmetic processing device. . 3. An arithmetic processing unit having a power saving mode, wherein the arithmetic processing unit is set to a low power consumption mode and the power supply to the peripheral input / output device is turned off. Power saving method for processing equipment.