JPH06303527A - Charge coupled device - Google Patents

Abstract

PURPOSE:To avoid signal destruction of all picture elements in the case of overflow in a part of horizontal transfer registers in the CCD solid-state image pickup element which has linear sensors arranged in plural lines and is provided with a vertical transfer register in the end in the electric charge transfer direction of the horizontal transfer register of each linear sensor. CONSTITUTION:The CCD solid-state image pickup element has linear sensors 26 arranged in plural lines and is provided with a vertical transfer register 27 in the end in the electric charge transfer direction of a horizontal transfer register 24 of each linear sensor 26. A limit area 30 is formed which is used to limit the electric charge to a prescribed quantity before transfer from the horizontal transfer register 24 to the vertical transfer register 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device such as a CCD solid state image pickup device.

[0002]

CCDs such as area sensors and linear sensors
In the solid-state image sensor, when a large amount of light is emitted, electric charge overflows in the sensor unit. As a countermeasure, an overflow drain structure for sweeping away the overflow charge is provided so that an excessive charge can be discarded. As an actual example, a vertical overflow drain structure or a horizontal overflow drain structure has been put into practical use.

FIG. 5 shows a CCD solid-state image pickup device 1 having a structure in which a plurality of lines of linear sensors are arranged and a vertical transfer register is further added.

The CCD solid-state image pickup device 1 includes a sensor array 3 in which a plurality of sensor parts (light receiving parts) 2 are arranged in a horizontal direction and a horizontal transfer register of CCD structure arranged on one side of the sensor array 3. 4 and a linear sensor 6 composed of a read gate unit 5 provided between the sensor array 3 and the horizontal transfer register 4 are arranged in a plurality of lines in the vertical direction, three lines in this example, and the horizontal transfer register 4 [4A , 4B, 4
A vertical transfer register 7 having a CCD structure is provided at the end in the charge transfer direction of C], and a charge-voltage converter that converts the signal charge transferred in the vertical transfer register 7 into a voltage at the final stage of the vertical transfer register 7. The output unit 8 including is connected and configured.

Although not shown, this CCD solid-state image pickup device 1
Then, for example, a vertical overflow function or a horizontal overflow function is provided, and when the sensor unit 2 is irradiated with a large amount of light, excess charges are swept to the vertical overflow mechanism or the horizontal overflow mechanism.

The horizontal transfer register 4 [4A, 4 for each line
B, 4C], a common drive pulse, that is, a two-phase clock pulse φH ₁ and φH _2, is applied, a common read gate pulse φROG is applied to the read gate unit 5, and a drive pulse, that is, Two-phase clock pulses φV ₁ and φV ₂ are applied.

FIG. 6 is an enlarged view of a transfer unit from the horizontal transfer register 4 to the vertical transfer register 7. In the horizontal transfer register 4, a storage portion 12S having a storage gate electrode 11S made of first-layer polycrystalline silicon,
The transfer section 13 is composed of the transfer section 12T having the transfer gate electrode 11T made of the second layer polycrystalline silicon, and the transfer section 13 is formed in a plurality of stages. The storage gate electrode 11S and the transfer gate electrode 11T of each transfer unit 13 are commonly connected, and the two-phase clock pulses φH ₁ and φH ₂ are alternately applied.

In the vertical transfer register 7, a storage portion 15S having a storage gate electrode 14S made of first-layer polycrystalline silicon and a transfer portion 15T having a transfer gate electrode 14T made of second-layer polycrystalline silicon are provided. The transfer unit 16 is configured, and the transfer unit 16 is formed in a plurality of stages. Storage gate electrode 14S and transfer gate electrode 14T of each transfer unit 16
Are commonly connected, and alternately, a two-phase clock pulse φV ₁
And φV ₂ are applied.

The transfer unit 13 at the final stage of the horizontal transfer register 4
The storage unit 12S is connected to the transfer unit 15T of the predetermined transfer unit 16 of the vertical transfer register 7.

The gate electrode 17 of the read gate section 5 between the sensor section 2 and the horizontal transfer register 4 is formed of the first-layer polycrystalline silicon, and this read gate section 5 is connected to the transfer section 12T of the horizontal transfer register 4. To be done. The broken line 18 is the transfer channel region.

In this CCD solid-state image pickup device 1, each clock pulse φH ₁ , φH ₂ , φV ₁ , φV ₂ , φROG is applied at the timing shown in FIG.
The signal charges of [3A, 3B, 3C] are read out by the gate unit 5.
It is read out to the corresponding horizontal transfer registers 4 [4A, 4B, 4C] via [5A, 5B, 5C], transferred in the horizontal direction, and sequentially transferred to the horizontal transfer registers simultaneously for each signal charge of one pixel in each line. 4 to the vertical transfer register 7. The signal charges of each line transferred to the vertical transfer register 7 are transferred in the vertical direction and sequentially output through the output unit 8.

As the output, as shown in FIG. 7, the output signal of the left end sensor unit 2 (D1-1) on the first line, the output signal of the left end sensor unit 2 (D2-1) on the second line, and the third line The output signals of the left edge sensor unit 2 (D3-1) of the eye are sequentially obtained, and subsequently output similarly.

[0013]

In the conventional CCD solid-state image pickup device, excess charges in the sensor portion when a large amount of light is received are swept away to the vertical overflow mechanism or the horizontal overflow mechanism. If the photoelectrically converted charges are excessively sent to the transfer register or light leaks into the transfer register (so-called smear) when reading from the sensor section, the charge will overflow in the transfer register and Even the signal is destroyed.

For example, in the case of the CCD solid-state image pickup device 1 shown in FIGS. 5 and 6, when the electric charge overflows in an arbitrary transfer section 13 of the horizontal transfer register 4 of a certain line, first, before and after the arbitrary transfer section 13 is generated. The charge overflows into the transfer unit 13, and the signal on that line is destroyed. Further, when the degree of overflow increases, the vertical transfer register 7 also overflows and the signals of all pixels are destroyed.

Therefore, even if a part of the signal is irradiated with an excessive amount of light, the signals of all pixels may be destroyed. Even if an overflow mechanism (so-called vertical overflow, horizontal overflow, etc.) is provided to suppress overflow in a simple sensor unit, a large amount of smear occurs in the horizontal transfer register 4 and a large amount of signal is read out when the read gate is open. The same applies if the photoelectrically converted charges are transferred to the horizontal transfer register.

In view of the above points, the present invention provides a charge-coupled device such as a solid-state image sensor capable of avoiding destruction of signals on all lines even if a charge overflow occurs in a transfer register of a certain line. Is.

[0017]

A charge-coupled device according to the present invention has a plurality of first transfer registers 24 arranged in one direction.
[24A, 24B, 24C] and a second transfer register 27 for transferring in one direction, which is arranged at an end of each first transfer register 24 [24A, 24B, 24C] in the charge transfer direction, The charge is transferred to the first transfer register 24 [24A,
24B, 24C] to the second transfer register 27 before being transferred to the second transfer register 27, a limit region 30 for limiting the charge to a predetermined charge amount is provided.

The limit region 30 is composed of a gate portion 41 and a drain region 42.

The gate portion 41 of the limit region 30 can be formed by extending the transfer electrode 31T of the first transfer register 24.

The potential of the gate part 41 of the limit region 30 can be set deeper than the potential of the transfer gate part 32T of the first transfer register 24.

[0021]

In the present invention, by providing the limit region 30, the excess charge of the charges transferred in the first transfer register 24 is swept to the limit region 30 and transferred to the second transfer register 27. Before the transfer, the electric charge is limited to a predetermined electric charge amount, and the second transfer register 27 transfers only the electric charge amount less than the limited electric charge amount. Therefore, even if a charge overflow occurs in the first transfer register 24 of a certain line, only the signal destruction of that line will occur, and the signal destruction of other lines can be avoided.

Since the limit region 30 is composed of the gate portion 41 and the drain region 42, the charges exceeding the potential of the gate portion 41 flow into the drain region 42, and the amount of charges in the first transfer register 24 is limited. .

When the transfer electrode 31T of the first transfer register 24 is extended to form the gate portion 41 of the limit region 30, it is structurally simplified.

Further, when the potential of the gate portion 41 of the limit region 30 is set deeper than the potential of the transfer portion 32T of the first transfer register 24, the charge amount is more reliably limited.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 show a case where the linear sensor is applied to a CCD solid-state image pickup device having a structure in which a plurality of lines are arranged and a vertical transfer register is added. The CCD solid-state image pickup device 21 of the present embodiment has a sensor array 23 in which a plurality of sensor parts (light receiving parts) 22 each of which is a pixel are arranged one-dimensionally in the horizontal direction as in FIG. A linear sensor 26 including a horizontal transfer register 24 having a CCD structure and a readout gate portion 25 provided between the sensor row 23 and the horizontal transfer register 24 is arranged in a plurality of lines in the vertical direction. In this example, red (R) and green are provided. (G) and blue (B) are arranged in three lines, and the horizontal transfer registers 24 [24A, 24 of each line are arranged.
B, 24C] is provided with a vertical transfer register 27 having a CCD structure at the end in the charge transfer direction.

Further, at the final stage of the vertical transfer register 27, an output section including a charge-voltage conversion section for converting the signal charges transferred in the vertical transfer register 27 into a voltage and a reset mechanism for resetting the charge-voltage conversion section. 28 is connected.

Although not shown, for example, a vertical overflow function or a horizontal overflow function is provided, and when each sensor portion 4 is irradiated with a large amount of light, excess charges are swept away from the sensor portion 4 to the overflow mechanism. ing.

The horizontal transfer register 24 [24 for each line
A, 24B, 24C] are applied with a common drive pulse, that is, a two-phase clock pulse φH ₁ and φH ₂ , and a read gate section 25 [25A, 25B, 25C] is applied with a common read gate pulse φROG. A drive pulse, that is, a two-phase clock pulse φV ₁ is applied to the vertical transfer register 27.
And φV ₂ are applied. CCD solid-state image sensor 2 of this example
Reference numeral 1 corresponds to a so-called R, G, B three-line color linear sensor.

However, in this example, in particular, in the horizontal transfer register 24 [24A, 24B, 24C] of each line, the charge to the vertical transfer register 27 is adjacent to the transfer portion before the charge is transferred to the vertical transfer register 27. Limit region 30 [30A, 30B, 30 for limiting the amount to a predetermined amount
C] is provided. This limit area 31 [31A, 3
1B, 31C] includes a limit gate portion and an overflow drain region, as described later.

That is, an enlarged view of FIG. 2 (horizontal transfer register 2
4 is an enlarged view of a transfer unit from the vertical transfer register 27 to the vertical transfer register 27).
Storage gate electrode 31 made of polycrystalline silicon
The transfer unit 33 is configured by the storage unit 32S having S and the transfer unit 32T having the transfer gate electrode 31T made of the second-layer polycrystalline silicon,
This transfer unit 33 is formed in a plurality of stages. Storage gate electrode 31S and transfer gate electrode 3 of each transfer unit 33
1T is commonly connected, and two-phase clock pulse φ
H ₁ and φH ₂ are applied.

In the vertical transfer register 27, the transfer is performed by the storage portion 35S having the storage gate electrode 34S made of the first layer polycrystalline silicon and the transfer portion 35T having the transfer gate electrode 34T made of the second layer polycrystalline silicon. The unit 36 is configured, and the transfer unit 36 is formed in a plurality of stages. The storage gate electrode 34S and the transfer gate electrode 34T of each transfer unit 36 are commonly connected, and the two-layer clock pulses φV ₁ and φV ₂ are alternately applied.

The transfer unit 3 at the final stage of the horizontal transfer register 24
The storage unit 32 of No. 3 is connected to the transfer unit 35T of the predetermined transfer unit 36 of the vertical transfer register 27. The gate electrode 37 of the read gate section 25 between the sensor section 22 and the horizontal transfer register 24 is formed of the first-layer polycrystalline silicon, and the read gate section 35 is connected to the transfer section 32T of the horizontal transfer register 24. .

In this example, the vertical transfer register 27
Final transfer unit 3 of the horizontal transfer register 24 before being transferred to
Limit gate unit 4 adjacent to storage unit 32S of 3
1 and the overflow drain region 4 formed of, for example, an N ⁺ diffusion layer adjacent to the limit gate portion 41.
2 is provided to configure the limit area 30.

Here, the limit gate unit 41 extends the transfer gate electrode 32T of the final stage transfer unit 33 of the horizontal transfer register 24 into a hook shape, and the extended portion serves as the limit gate electrode 43, and below the limit gate electrode 43. The impurity profile of the corresponding transfer channel region is the same as that of the corresponding transfer channel region below the transfer gate electrode 31T. As shown in FIG. 2, it is easy to set the potential of the limit gate unit 41 that determines the limited charge amount to the same potential as the transfer unit 32T.

A broken line 38 is a transfer channel region, and this transfer channel region 38 partially extends from the final stage transfer unit 33 of the horizontal transfer register 24 below the limit gate unit 41 to the overflow drain region 42. On the other hand, the vertical transfer register 27 is configured such that the maximum amount of charge handled by the transfer unit 36 is equal to or more than the amount of charge handled by the final stage transfer unit 33 of the horizontal transfer register limited by the limit region 30.

FIG. 3A shows a cross section taken along the line HH of FIG. 2, and FIG. 4A shows a cross section taken along the line VV of FIG. 3A and 4A, the N-type transfer channel region 38 is formed in the P-type well region 45, and the transfer channel region below the storage gate electrode 31S of the horizontal transfer register 24 is the N layer 38S.
Consists of _1, the transfer channel region under the transfer gate electrode 31T is N ^- is formed by a layer 38T _1.

The transfer channel region below the storage gate electrode 34S of the vertical transfer register 27 is an N layer 38S ₂
And the transfer channel below the transfer gate electrode 34T is composed of the N ⁻ layer 38T ₂ .

Further, the transfer channel region under the limit gate electrode 41 is composed of the N ⁻ layer 38T ₁ , and the overflow drain region 42 is composed of the N ⁺ layer.

In the above CCD solid-state image pickup device, each clock pulse φH ₁ , φH ₂ , φV ₁ , φV ₂ and φ.
ROG is applied at the same timing as shown in FIG. The signal charge of the sensor section 22 of each sensor row 23 [23A, 23B, 23C] is read out by the gate section 25 [2].
5A, 25B, 25C] to the corresponding horizontal transfer register 24 [24A, 24B, 24C] and horizontally transferred in the horizontal transfer register 24 [24A, 24B, 24C], and then sequentially for each line. The horizontal transfer register 24 [24A, 24B, 24 is provided for each signal charge of one pixel.
C] to the vertical transfer register 27. The signal charge of each line transferred to the vertical transfer register 27 is transferred in the vertical direction, converted into a charge voltage by the output unit 28, and output.

Next, smear in the horizontal transfer register 24 and a large amount of charges photoelectrically converted at the time of signal reading are transferred to the horizontal transfer register 24, and the horizontal transfer register 24 is transferred.
When a charge overflows at a certain portion (transfer portion 33) of the above, the operation is performed as shown in FIGS. 3B and C and FIGS. 4B and 4C.

FIGS. 3B and 4B show time points t ₁ (φH in FIG. 7).
₁ and .phi.V ₂ is high, potential diagram at the time of charge transfer from the horizontal transfer register .phi.H ₂ is at low level) to the vertical transfer register, 3C and 4C are time t ₂ (phi
FIG. 7 is a potential diagram at the time of limit work due to accumulation of the final stage of the horizontal transfer register when H ₁ and φV ₂ are low level and φH ₂ is high level, that is, overflow.

Time point t₁3B and 4B at the
As shown in FIG.
It is assumed that a large amount of charge e has been transferred to the transfer unit 33. Next time
Point t ₂At this stage, a large amount of charge e is transferred to the transfer unit 33 at the final stage.
When delivered, as shown in FIGS. 3C and 4C, excess
The charge has the same potential as the transfer part 32T
Overflow dray over the limit gate section 41
Storage area in the final stage transfer section
The charge limited to a predetermined amount is transferred to the portion 32S.
Each horizontal transfer register 24 [24A, 24B, 24C]
The limited charge amount to the vertical transfer register 27.
Will be transferred.

Therefore, according to the CCD solid-state image pickup device 21, even if a charge overflow occurs in the horizontal transfer register 24 for one line, the overflow is not affected by the vertical transfer register 27. For this reason, the pixel signals of one line in the overflowed horizontal transfer register 24 are destroyed (erased), but the pixel signals of other lines are not destroyed, and the signal destruction of all pixels can be avoided.

Further, when the limit gate portion 41 is formed by extending the transfer gate electrode 31T of the horizontal transfer register 24, the limit region 30 can be structurally easily realized.

In the above example, the limit gate section 41 has a potential below the gate section (so-called channel potential) of the transfer section 32T of the horizontal transfer register 24.
Although it is configured to be equal to the lower potential (so-called channel potential), it is also possible to configure the potential under the limit gate section 41 to be deeper than the potential under the transfer section 32T in addition to the above, so that the margin is further increased. It is realistic to adopt such a method to obtain

That is, for example, the limit gate unit 41 shown in FIG.
By shortening the channel length a, the potential under the limit gate portion 41 can be set deeper than the potential under the transfer portion 32T by modulation from the potential of the overflow drain region 42 or the storage portion 32S.

Alternatively, the impurity concentration profile of the transfer channel region under the limit gate electrode 43 is made different from that of the transfer channel region under the transfer gate electrode 31T, that is, the impurity concentration under the redimido electrode 43 is lower than the impurity concentration under the transfer gate electrode 31T. By making it large, the potential under the limit gate portion 41 can be set deeper than the potential under the transfer portion 32T.

Although the limit gate electrode 43 is formed by extending the transfer gate electrode 31T in the above example, the limit gate electrode 43 can be formed separately from the transfer gate electrode 31T.

Further, in the above example, the horizontal transfer register 24
Although the limit area 30 is provided in the transfer unit 33 at the final stage of
In addition, it is also possible to provide the limit region 30 over the final pre-stage transfer unit or a plurality of stages of transfer units.

The present invention can be applied to area sensors and linear sensors, and can also be applied to charge coupled devices other than CCD solid state image pickup devices.

[0052]

According to the present invention, even if a charge overflow occurs in a part of the first transfer register, it does not overflow in the second transfer register, and therefore, the signal in the first transfer register of the line. Signal destruction in the first transfer registers of the other lines can be avoided. In addition, the structure of the limit region can be simplified, and the charge amount can be more reliably limited in the limit region.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a CCD solid-state imaging device according to the present invention.

FIG. 2 is an enlarged view of a transfer unit from a horizontal transfer register to a vertical transfer register in FIG.

3A and 3B are a cross-sectional view and a potential diagram on line HH in FIG.

4 is a cross-sectional view and a potential diagram on the line VV in FIG.

FIG. 5 is a configuration diagram of a conventional CCD solid-state imaging device.

FIG. 6 is an enlarged view of a transfer unit from the horizontal transfer register to the vertical transfer register in FIG.

FIG. 7 is a clock timing chart of the CCD solid-state image sensor.

[Explanation of symbols]

1, 21 CCD solid-state image sensor 2, 22 Sensor section 3 [3A, 3B, 3C], 23 [23A, 23B, 23
C] Sensor array 4 [4A, 4B, 4C], 24 [24A, 24B, 24
C] Horizontal transfer register 5 [5A, 5B, 5C], 25 [25A, 25B, 25
C] Read-out gate section 6,26 Linear sensor 7,27 Vertical transfer register 8,28 Output section 30 Limit area 11S, 31S Storage gate electrode 11T, 31T Transfer gate electrode 12S, 32S Storage section 12T, 32T Transfer section 13, 33 Transfer Section 14S, 34S storage gate electrode 14T, 34T transfer gate electrode 15S, 35S storage section 15T, 35T transfer section 16, 36 transfer section 37 read gate electrode 18, 38 transfer channel area 41 limit gate section 42 overflow drain area 43 limit gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 29/796

Claims (4)

[Claims] 1. A plurality of first transfer registers arranged in one direction, and a second transfer register arranged at an end of each of the first transfer registers in the charge transfer direction for transferring in the one direction. A charge-coupled device, comprising: a limit region for limiting the charge to a predetermined amount before the charge is transferred from the first transfer register to the second transfer register. 2. The charge coupled device according to claim 1, wherein the limit region is composed of a gate portion and a drain region. 3. The charge coupled device according to claim 2, wherein the gate portion of the limit region is formed by extending the transfer electrode of the first transfer register. 4. The charge coupled device according to claim 2, wherein the potential of the gate portion of the limit region is set deeper than the potential of the transfer gate portion of the first transfer register.