JPH06303260A - Offset correcting circuit - Google Patents

Abstract

PURPOSE:To remove an offset from a multilevel input demodulation base band signal. CONSTITUTION:A judging circuit 102 judges whether a symbol is the effective one for detecting average amplitude from the identification result of an identifying equipment 101. First and second averaging circuits 103 and 105 obtain the average amplitude of the symbols with the different amplitudes when they are inputted from the judgement result of the judging circuit 102 and obtain the average amplitude without using the symbols when the symbol with specified amplitudes are continuously inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset correction circuit used in a demodulator for demodulating a digital modulated wave.

[0002]

2. Description of the Related Art QPSK (Quadrature Ph)
In a demodulator such as the case-shift keying), an offset occurs in the demodulated baseband signal due to variations in the characteristics of components, temperature changes, aging, and the like. Due to this offset, the bit error rate increases when the digital signal is restored from the demodulated baseband signal, and an error occurs when the carrier wave is reproduced. Therefore, a correction circuit for removing the offset included in the demodulated baseband signal is required. A correction circuit for removing this offset is required. As a conventional example of this offset correction circuit, there is Japanese Unexamined Patent Publication No. 4-68941 "Offset control method".

FIG. 8 is a block diagram showing a conventional offset correction circuit. The demodulator baseband signal sampled at the symbol timing that is the center phase of the eye pattern is input to the discriminator 801 through the subtractor 810. The identifier 801 identifies the polarity of the input demodulated baseband signal. When the input symbol polarity is positive,
The discriminator 801 receives the first signal through the inverter circuit 802.
The switch circuit 803 is turned on. As a result, the input demodulated baseband signal passes through the first switch circuit 803 and is added to the next-stage first hold circuit 804.
The first hold circuit 804 holds the amplitude of the input positive demodulation baseband signal. The first low-pass filter 805 at the next stage averages the amplitudes held by the first hold circuit 804 to obtain a positive average amplitude. When the polarity of the input symbol is negative, the identification circuit 801 causes the second
The switch circuit 806 is turned on. As a result, the input demodulated baseband signal passes through the second switch circuit 806 and is added to the second hold circuit 807 at the next stage.
The second hold circuit 807 holds the amplitude of the input negative demodulation baseband signal. The second low-pass filter 808 at the next stage averages the amplitudes held by the second hold circuit 807 to obtain a negative average amplitude. Adder 8
09 adds the positive and negative average amplitudes to obtain the offset of the input demodulation baseband signal. Subtractor 810
Removes the offset included in the input demodulation baseband signal by superimposing the output of the adder 809 on the input demodulation baseband signal.

The conventional offset correction circuit shown in FIG.
When a demodulated baseband signal having a binary amplitude such as an SK signal is input, the offset can be correctly detected. However, 16QAM (Quadratur)
When a demodulated baseband signal having a multi-valued amplitude such as an eAmplitude Modulation signal is input, the offset may not be detected correctly. This will be described below with reference to FIGS. 8 and 9.

FIG. 9 is a signal waveform diagram for explaining the operation of the offset correction circuit of FIG. 9, the input demodulated baseband signal _{V 2, V 1, -V 1} , takes 4 values of -V _2, it is assumed that no offset. Discriminator 80
In the demodulated baseband signal input to 1, the four symbols do not always occur with the same probability when viewed in a certain period, and there is a possibility that many specific symbols occur. For example, assume that the demodulated baseband signal shown in FIG. 9A is input. At this time, on the positive side, the symbols of the specific V ₂ are continuous from time 5, so the output of the first hold circuit 804 is shown in FIG. 9 (16). Therefore,
The output of the first low-pass filter 805 is shown in FIG.
The positive average amplitude approaches V ₂ . On the other hand, the output of the second hold circuit 807 is as shown in FIG. And
The output of the second low-pass filter 808, FIG. 9 (19), and the negative mean amplitude is between -V ₁ and -V _2. Therefore, the combined output of the positive and negative average amplitudes is as shown in FIG. 9 (20), and the positive component remains. Therefore, the specific V on the positive side
_{Since the two} symbols are continuous, the offset is erroneously detected even though the input demodulated baseband signal has no offset.

[0006]

As described above, in the conventional offset correction circuit, the offset is correctly detected when the input demodulated baseband signal having a multivalued amplitude has a specific symbol continuous. I can't.

According to the present invention, in the case of an input demodulated baseband signal having a multi-valued amplitude, an offset is correctly detected even when a specific symbol continues, and an offset correction for removing an offset included in the input demodulated baseband signal. The purpose is to provide a circuit.

[0008]

An offset correction signal is detected from an average amplitude of an input demodulation base hand signal sampled at a symbol timing which is a center phase of an eye pattern, and the detected offset correction signal is detected as the input demodulation base band. In a correction circuit that removes an offset included in the input demodulation baseband signal by superimposing it on a signal, an identification unit that identifies the amplitude of the input demodulation baseband signal, and an average amplitude is detected from the identification result of the identification unit. Determining means for determining whether or not the input symbols having different amplitudes are effective for determining the average amplitude of the input symbols having different amplitudes effective for detecting the average amplitude according to the determination result of the determining means. And an amplitude generating means.

[0009]

When the determining means determines the continuity of a specific symbol, the means for determining the average amplitude determines the average amplitude without using the symbol. Therefore, it is possible to correctly detect the offset from the input demodulation baseband signal having multi-valued amplitude and remove the offset included in the input demodulation baseband signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a first offset correction circuit according to the present invention.
It is a block diagram which shows an Example. The demodulator baseband signal sampled at the symbol timing, which is the center phase of the eye pattern, is input to the discriminator 101 through the subtractor 109. The discriminator 101 discriminates by comparing the input demodulated baseband signal with a predetermined level, and outputs to the determination circuit 102 which amplitude symbol has been input. The determination circuit 102 applies a first input control signal for controlling the input to the first averaging circuit 103 to the control terminal of the first averaging circuit 103 according to the output of the discriminator 101. Further, the determination circuit 102 applies a first reset signal indicating that all the symbols for obtaining the average amplitude in the first averaging circuit 103 have been input to the control terminal of the first averaging circuit 103. Further, the determination circuit 102 includes a discriminator 101.
A second input control signal for controlling the input to the second averaging circuit 105 is applied to the control terminal of the second averaging circuit 105 according to the output of The determination circuit 102 also outputs a second reset signal indicating that all the symbols for obtaining the average amplitude in the second averaging circuit 105 have been input.
5 control terminal. First or second averaging circuit 1
03 and 105 respectively add the amplitudes of the input symbols according to the first or second input control signal of the determination circuit 102. When all the inputs for obtaining the average amplitude are completed, the added value is output as the average amplitude. First
The outputs of the second averaging circuits 103 and 105 are smoothed by the first and second low pass filters 104 and 106, respectively. The adder 107 adds the outputs of the first and second low-pass filters 104 and 106 to obtain the average amplitude of the input demodulated baseband signal. Here, the average amplitude of the input demodulated baseband signal is zero when there is no offset, so the average amplitude obtained by the adder 107 is the offset. The coefficient unit 108 multiplies the offset detected by the adder 107 by a coefficient that determines the gain of the loop. The adder 109 superimposes the output of the coefficient multiplier 108 on the input demodulation baseband signal and outputs the demodulation baseband signal from which the offset included in the input demodulation baseband signal has been removed.

Next, taking the case where the demodulated baseband signal has four-valued amplitude as an example, the discriminator 101 and the judgment circuit 1
The operation of 02 will be described. FIG. 2 is a block diagram showing the discriminator 101 and the determination circuit 102. In this example,
The average amplitude of two positive input symbols among the four values is obtained by the first averaging circuit 103, and the average amplitude of two negative input symbols is obtained by the second averaging circuit 105. In FIG. 2, first to fourth comparison circuits 201, 201
02, 203 and 204 are predetermined levels l ₁ , zero,
l ₂ and the amplitude L of the input demodulated baseband signal are compared,
Amplitude L is l ₁ ≦ L, zero ≦ L <l ₁ , l ₂ ≦ L
1 is output when <zero and L <l ₂ . 1st to 4th
Input state storage circuits 205, 206, 207, 208
Are the first to fourth comparison circuits 201, 202, 203,
When 1 is input from 204, 1 is held until the reset signal is input. First and second input state storage circuit 2
The outputs of 05 and 206 are supplied to the first and second control signal generation circuits 209 and 210 and the first AND circuit 215. The first AND circuit 215 outputs the first reset signal to the first and second input state storage circuits 205, 205 when the outputs of the first and second input state storage circuits 205, 206 both become 1. 206 and the first averaging circuit 103
Supply to. At this time, the first and second input state storage circuits 205 and 206 change from 1 to 0. First averaging circuit 1
The operation of 03 will be described later.

On the other hand, the first and second control signal generation circuits 2
09 and 210 are the first and second input state storage circuits 20.
When the output of each of 5,206 changes from 0 to 1, 1 is output. The first OR circuit 213 has first and second
Of the control signal generation circuits 209 and 210 of the first averaging circuit 10 is used as a first input control signal.
Supply to 3. The outputs of the third and fourth input state storage circuits 207 and 208 are supplied to the third and fourth control signal generation circuits 211 and 212 and the second AND circuit 216. The second AND circuit 216 outputs the second reset signal to the third and fourth input state storage circuits 207, 207 when the outputs of the third and fourth input state storage circuits 207, 208 both become 1. 208 and the second averaging circuit 105
Supply to. At this time, the third and fourth input state storage circuits 207 and 208 change from 1 to zero. The operation of the second averaging circuit 105 will be described later.

On the other hand, the third and fourth control signal generating circuits 2
Reference numerals 11 and 212 denote third and fourth input state storage circuits 20.
When the outputs of 7 and 208 respectively change from zero to 1, 1 is output. The second OR circuit 214 takes the logical sum of the third and fourth control signal generation circuits 211 and 212,
The result is used as a second input control signal for the second averaging circuit 1.
Supply to 05. The classifier 101 and the determination circuit 10 described above
2 will be described in detail with reference to FIG.

FIG. 3 is a signal waveform diagram for explaining the operation of the discriminator 101 and the judgment circuit 102 shown in FIG. Figure 3
, The amplitude of the input demodulated baseband signal is V ₂ ,
It is assumed that four values of V ₁ , -V ₁ and -V ₂ are taken, and the discriminator 101 discriminates at predetermined levels l ₁ , zero and l ₂ . The operation of the discriminator 101 and the decision circuit 102 for a positive input symbol when the demodulated baseband signal shown in FIG. 3A is input will be described below. First, FIG.
At time 1 of (1), since the symbol having the amplitude of V ₂ is input, the output of the first comparison circuit 201 becomes 1 as shown in FIG. 3 (2). Then, the first input state storage circuit 2
The output of 05 changes from zero to 1 as shown in FIG. At this time, since the output of the first control signal generation circuit 209 becomes 1, the output of the first OR circuit 213 becomes 1. That is, the first input control signal becomes 1 as shown in FIG.

At time 3 in FIG. 3 (1), since the symbol having the amplitude V ₁ is input, the output of the second comparison circuit 202 becomes 1 as shown in FIG. 3 (3). Then, the output of the second input state storage circuit 206 changes from zero to 1 as shown in FIG. At this time, since the output of the second control signal generation circuit 210 becomes 1, the first OR circuit 213
Has an output of 1. That is, the first input control signal is
Similar to time 1, it becomes 1 as shown in FIG. Then, at time 3, the first and second input state storage circuits 20
Since the outputs of 5, 206 are both 1, the output of the first AND circuit 215 is 1, and the first reset signal is
It becomes 1 as shown in (11). That is, V ₁ and V ₂
When both positive symbols of are input,
The first reset signal becomes 1. At this time, the first and second input state storage circuits 205 and 206 are reset to 0.

At time 5, since the symbol having the amplitude V ₂ is input, the first input control signal becomes 1 as shown in FIG. 3 (10) in the same manner as at time 1. Time 7,8,
Although symbols of amplitude V ₂ are continuous in 10 and 12,
Since the output of the first input state storage circuit 205 remains 1 as shown in FIG. 3 (6), the output of the first control signal generation circuit 209 remains 0. Therefore, if a specific symbol that has been input once is input continuously,
Input control signal becomes zero as shown in FIG.

The above is the description of the operation with respect to the positive input symbol. Similarly, with respect to the negative input symbol, the third and fourth comparison circuits 203 and 204 and the third and fourth input state storage are similarly performed. The outputs of the circuits 207 and 208 are shown in FIGS. 3 (4), (5), (8) and (9), respectively. The second input control signal and the second reset signal are as shown in (12) and (13) of FIG. 3, respectively.

As described above, when positive specific symbols are continuously input, the first input control signal from the determination circuit 102 becomes zero, so those symbols are input to the first averaging circuit. It can be seen that the data is not input to 103.
Further, at the time when two positive symbols are input, the first reset signal from the determination circuit 102 is supplied to the first averaging circuit 103. Similarly, when the negative specific symbols continue, the second input control signal of the decision circuit 102 becomes zero, so that those symbols are input to the second averaging circuit 105.
Not entered in. Further, at the time when two types of negative symbols are input, the second reset signal from the determination circuit 102 is supplied to the second averaging circuit 105.

Next, the first averaging circuit 103 in FIG.
The configuration and operation of will be described with reference to FIGS. 4 and 5. Figure 4
FIG. 3 is a block diagram showing a configuration of a first averaging circuit 103 for positive symbols. The determination circuit 102 supplies the first averaging circuit 103 with the first input control signal and the first reset signal. When the first input control signal from the determination circuit 102 is 1, the switch circuit 401 supplies the input demodulation baseband signal to the adder 402. Further, when the first input control signal is 1, the output of the adder 402 is taken into the delay circuit 403. The adder 402 takes the added value of the input demodulated baseband signal and the output of the delay circuit 403. This added value is used as the delay circuit 403 and the hold circuit 4.
It is input to 04. When the first reset signal of the decision circuit 102 changes from zero to 1, the hold circuit 404 holds the output of the adder 402, while the delay circuit 403.
Is reset to 0.

The operation of the first averaging circuit 103 shown in FIG. 4 will be described in more detail. FIG. 5 shows the first averaging circuit 1 of FIG.
3 is a signal waveform diagram for explaining the operation of No. 03. FIG. When the demodulated baseband signal shown in FIG. 5 (1) is input to the first averaging circuit 103 at time 1, the first input control signal of the determination circuit 102 becomes 1 as shown in FIG. 5 (10). . At this time, the switch circuit 401 supplies the symbol of the amplitude V ₂ to the adder 402 as shown in FIG. Then, the delay circuit 40 which is the other input of the adder 402
Assuming that the output of 3 is 0, the output of the adder 402 becomes V ₂ as shown in FIG. 5 (15).

At time 3, a symbol of amplitude V ₁ is input, and the added value of the adder 402 becomes V ₁ + V ₂ . The first reset signal from the determination circuit 102 is shown in FIG.
It becomes 1 as shown in 1). By this first reset signal, the added value V ₁ + V ₂ of the amplitudes of the two symbols is held in the hold circuit 404 and output, as shown in FIG. The delay circuit 403 is reset to zero.

When the symbols of the amplitude V ₂ are continuous as from the time 5, when the symbols of the amplitude V ₂ are input to the first averaging circuit 103 at the time 5, the symbols of the amplitude V ₁ are next. The switch circuit 401 does not turn on until is input. Therefore, the output of the adder 402 is shown in FIG.
As shown in, it remains V ₂ and does not change. Also next amplitude V
Until the first reset signal ₁ symbol is input becomes 1, the output of the adder 402 is not bold bold circuit 404. Therefore, the output of the hold circuit 404 remains unchanged at V ₁ + V ₂ as shown in FIG. 5 (16). The above is a description of the first averaging circuit 103, but the same applies to the operation of the second averaging circuit 105.

As described above, in the configuration of the offset correction circuit of FIG. 1, when the specific symbols are consecutive on the positive side and the negative side, the first and second input control signals of the determination circuit 102 are zero. become. Therefore, those symbols are not input to the first and second averaging circuits 103 and 105. In addition, the first and second averaging circuits 103 and 105
Outputs the added value of the amplitudes of two symbols each having a different identification result by the first and second reset signals from the determination circuit 102. Since the offset is detected from the positive and negative average amplitudes obtained in this way, the offset can be correctly detected even in the case of the input demodulated baseband signal of multi-valued amplitude, even when a specific symbol continues. Therefore, the offset of the input demodulation baseband signal can be removed.

In the embodiment of FIG. 2, the first averaging circuit 103 obtains the average amplitudes of two types of positive symbols and the second averaging circuit 105 obtains the average amplitudes of two types of negative symbols. The determination circuit 102 is configured. Therefore,
First and second OR circuits 21 in the determination circuit 102
3, 214 and the first and second AND circuits 215,
By changing the combination of inputs to 216
It is possible to change the combination of each two types of symbols input to the second averaging circuits 103 and 105. For example,
Combinations of the two symbols of amplitude V ₁ and -V _1, the combination of the two symbols of the amplitude V ₂ and -V ₂ are considered. Further, a combination of two types of symbols of amplitude V ₂ and −V ₁ or a combination of two types of symbols of amplitude V ₁ and −V ₂ may be used. Further, by changing the determination circuit 102, it is possible to detect the offset of the input demodulation baseband signal with one averaging circuit.

FIG. 6 is a block diagram showing a second embodiment of the offset correction circuit of the present invention. In this second embodiment,
The configuration of the first embodiment of FIG. 1 is simplified by detecting the offset of the input demodulation baseband signal with one averaging circuit and one low-pass filter. In FIG. 6, a discriminator 601 discriminates the input demodulated baseband signal by comparing it with a predetermined level, and discriminates the discrimination result from the judgment circuit 6
Output to 02. The determination circuit 602 outputs an input control signal for controlling the input to the averaging circuit 603 and a reset signal indicating that all the symbols for obtaining the average amplitude in the averaging circuit 603 are input according to the identification result.
Supply to 03. The average amplitude of the input demodulated baseband signal obtained by the averaging circuit 603 is calculated by the low-pass filter 60.
The offset is obtained by smoothing at 4. Coefficient unit 60
In step 5, the detected offset is multiplied by a coefficient that determines the loop gain. The subtractor 606 removes the offset from the input demodulation baseband signal by superimposing the output of the coefficient multiplier 605 on the input demodulation baseband signal.

FIG. 7 shows a block diagram of the discriminator 601 and the judgment circuit 602 which constitute the offset correction circuit of FIG. In FIG. 7, the first to fourth comparison circuits 701 and 7
02, 703, 704, first to fourth input state storage circuits 705, 706, 707, 708, and first to fourth
The control signal generation circuits 709, 710, 711 and 712 are similar to those in FIG. However, the first to fourth control signal generation circuits 709, 710, 711, 7
An input control signal is generated from the output of 12 by the OR circuit 713. First to fourth input state storage circuits 705, 7
A reset signal is generated by the AND circuit 714 from the outputs of 06, 707 and 708.

By using the decision circuit 602 shown in FIG. 7, when specific symbols are consecutive in FIG. 6, those symbols are not input to the averaging circuit 603.
Further, the averaging circuit 603 outputs the average amplitude at that time every time all four types of symbols are input. Therefore, in the case of an input demodulated baseband signal having multi-valued amplitude, even when a specific symbol is continuous, the offset can be correctly detected and the offset of the input demodulated baseband signal can be removed.

Although the input demodulation baseband signal of four-valued amplitude has been described above, the input demodulation baseband signal of more multivalued amplitude can be obtained by changing the discriminator and the decision circuit in FIGS. But it is self-evident.

[0029]

As described above in detail, when the present invention is applied to the offset correction circuit used in the demodulator for demodulating a digital modulated wave, it is possible to obtain an input demodulated baseband signal having multi-valued amplitude. Correct offset can be detected even when specific symbols are consecutive. Therefore, the offset of the input demodulation baseband signal can be removed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an offset correction circuit of the present invention.

FIG. 2 is a block diagram showing a discriminator and a determination circuit in a first embodiment of an offset correction circuit of the present invention.

FIG. 3 is a signal waveform diagram for explaining the operation of the discriminator and the determination circuit in the first embodiment of the offset correction circuit of the present invention.

FIG. 4 is a block diagram showing a configuration of a first averaging circuit in the first embodiment of the offset correction circuit of the present invention.

FIG. 5 is a signal waveform diagram for explaining the operation of the first averaging circuit in the first embodiment of the offset correction circuit of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the offset correction circuit of the present invention.

FIG. 7 is a block diagram showing a discriminator and a judgment circuit in a second embodiment of the offset correction circuit of the present invention.

FIG. 8 is a block diagram showing a conventional offset correction circuit.

FIG. 9 is a signal waveform diagram for explaining the operation of the conventional offset correction circuit.

[Explanation of symbols]

101 ... Classifier, 102 ... Judgment circuit, 103 ... First averaging circuit, 104 ... First low-pass filter, 105 ... Second averaging circuit, 106 ... Second low-pass filter, 107 ... Adder,
108 ... Coefficient unit, 109 ... Subtractor, 601 ... Discriminator, 6
02 ... Judgment circuit, 603 ... Average circuit, 604 ... Low-pass filter, 605 ... Coefficient unit, 607 ... Subtractor.

Claims (3)

[Claims] 1. An offset correction signal is detected from an average amplitude of an input demodulation base hand signal sampled at a symbol timing which is a center phase of an eye pattern, and the detected offset correction signal is superimposed on the input demodulation base band signal. In the correction circuit that removes the offset included in the input demodulation baseband signal by the identification means for identifying the amplitude of the input demodulation baseband signal, and is effective for detecting the average amplitude from the identification result of the identification means. Determination means for determining whether or not the input symbols have different amplitudes, and average amplitude generation means for obtaining average amplitudes of input symbols of different amplitudes effective for detecting the average amplitude according to the determination result of the determination means. An offset correction circuit comprising: 2. The average amplitude generating means comprises a plurality of means for obtaining an average amplitude of a symbol group having different amplitudes, and a means for obtaining an average value of outputs of the plurality of means. 1. The offset correction circuit described in 1. 3. The offset correction circuit according to claim 2, wherein the determination unit controls the average amplitude generation unit to obtain an average amplitude of input symbols having different amplitudes of the identification result.