JPH0630284A - Binary image data compressor - Google Patents

Abstract

PURPOSE:To easily discriminate the gap of respective lines by outputting an EOL signal showing final data corresponding to a coded line in the case of outputting a final byte. CONSTITUTION:When a mode to perform compression for each line is designated to a coding mode register 3a, inputted image data are coded and successively outputted to the outside by a compression/extension circuit 2. When the image data come to the end of the line, the EOL signal from the outside is held by an EOL input signal holding part 4 and informed of the circuit 2 and a fraction bit generation instruction part 5. The instruction part 5 controls the circuit 2 and executes processing to arrange the final code data at the border of bytes. When no EOL code is outputted, the circuit 2 stops the line with '0' so as to arrange the final byte at the border of bytes. When the final byte is completed, the circuit 2 instructs the output of the EOL signal to an EOL signal output part 6 and outputs completed code data to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary image data compression device for compressing binary image data.

[0002]

2. Description of the Related Art In a binary image compression / expansion processing device that handles a large amount of binary images, a binary image compression / expansion processing device is used to speed up data transfer.
In many cases, the value image data is encoded and handled. As a typical encoding method used in this type of apparatus, M is
H (Modified Huffman) method, MR (Modified READ)
System and MMR (Modified MR) system.

In a binary image compression / expansion processing apparatus, when compression processing is performed by, for example, the MH method or the MR method, since one page of an input image is used as a unit, line breaks in code data must be decoded. I can't tell. Therefore, it is not possible to easily execute a process of inserting the fill bit by operating the encoded code data.

Further, in code data, the start of a line does not necessarily start at a byte boundary. Therefore, when code data from a line in the middle of an image is input and expanded, a bit shift operation is necessary. Will be. Also, when editing at the code data level in combination with code data corresponding to another image data, the bit shift operation is required.

[0005]

As described above, in the conventional binary image compression / expansion processing device, since the break of each line cannot be easily discriminated, the fill bit insertion process or the like cannot be easily executed, and the line bit insertion process cannot be executed easily. Since the start of does not necessarily start on a byte boundary, a bit shift operation was required.

The present invention has been made in view of the above points, and it is possible to easily discriminate the break of each line, and
An object of the present invention is to provide a binary image data compression device capable of always starting a line on a byte boundary.

[0007]

According to the present invention, there is provided a binary image data compression circuit for inputting binary image data and generating coded data, and a coding mode in the binary image data compression circuit. When the encoding mode register and the encoding mode for performing the encoding for each line are designated by the encoding mode register, the binary image data compression circuit is set to a fractional bit of the encoded data at the end of the line. When the fractional bit generation instruction means for aligning the byte boundaries of the final bytes by aligning “0” and the final byte with the byte boundaries aligned by the fractional bit generation instruction means is output from the binary image data compression circuit. , EOL signal output means for outputting an EOL signal indicating the last data corresponding to the encoding line.

[0008]

According to this structure, when the compression mode is designated for each line of image data, the last bit of the last code data corresponding to the coding line (binary image data) is When the byte boundaries are not matched, a "0" bit is inserted, and when the final byte is output, the EOL signal indicating the last data corresponding to the encoding line is output. Therefore, it is possible to efficiently execute processing (fill bit insertion processing, editing at the code data level, etc.) for code data output from the binary image data compression apparatus (binary image data compression / decompression processing apparatus 1). it can.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a binary image data compression / expansion processing apparatus 1 according to the embodiment. Figure 1
2, the binary image data compression / expansion processing device 1
The compression / expansion circuit 2, the I / O register group 3, the EOL input signal holding unit 4, the fraction bit generation instruction unit 5, and the EOL signal output unit 6 are included.

The compression / expansion circuit 2 inputs the binary image data during the compression process and outputs the coded data, and inputs the coded data during the expansion process and decodes the binary image data. .

The I / O register group 3 holds various data used for compression / expansion processing in the apparatus.
It includes a register (encoding mode register 3a) for setting a mode for the compression / expansion circuit 2. I
Data from the system side is input to and held in the / O register group 3 via the bus.

The EOL input signal holding unit 4 receives the EO input from the outside together with the data input to the compression / expansion circuit 2.
The L signal is held and the compression / expansion circuit 2 and the fraction bit generation instruction unit 5 are notified that the data input to the compression / expansion circuit 2 is the end of the line.

When the EOL input signal holding unit 4 notifies that the last image data of the line has been input, the fractional bit generation instruction unit 5 issues an instruction to fill the fractional bits of the last code data with “0”. This is performed for the compression / expansion circuit 2.

The EOL signal output section 6 outputs the last code data corresponding to the coded line from the compression / expansion processing circuit 2 and, at the same time, outputs the EOL signal indicating the last byte to the outside. If the last bit of the last encoded data does not match the byte boundary, the compression / expansion circuit 2 inserts a “0” bit under the control of the fractional bit generation instruction unit 5 to align the byte boundaries. Has been.

Next, the operation at the time of compression processing in the embodiment will be described with reference to FIG. FIG. 2 is a diagram for explaining the code data output when the mode for performing compression for each line is designated in the binary image data compression / expansion processing device 1. Here, a process of outputting code data line by line by the device 1 will be described.

First, holding of data indicating a mode for performing compression for each line is designated in the encoding mode register 3a in the I / O register group 3. The encoding system (MH system, MR system, etc.) is also used in the I / O register 3.
Assign to a given register in the group.

FIG. 2 shows an example in which the MH system is designated as the encoding system. 2A is binary image data input to the compression / expansion circuit 2, and FIG.
An example of the code data when the OL code is not output is shown, and FIG. 2C shows an example of the code data when the EOL code is output. Whether or not to attach the EOL code at the end of the line can also be selected by designating it in a predetermined register in the I / O register group 3.

After the setting of the I / O register group 3 is completed, the binary image data is input to the compression / expansion circuit 2 line by line. When inputting the last byte of data at the end of the line, the EOL signal is also input to the EOL signal holding unit 4 at the same time.

The compression / expansion circuit 2 encodes the input image data and sequentially outputs the code code to the outside. When the image data reaches the end of the line, the EOL input signal holding unit (register) 4 holds the EOL signal from the outside.
As a result, the compression / expansion circuit 2 and the fraction bit generation instruction unit 5 are notified that the input image data is at the end of the line.

The fractional bit generation instructing section 5 controls the generation / expansion circuit 2 to execute the processing for aligning the last code data to the byte boundary. When the EOL code is not output, the compression / expansion circuit 2 fills "0" so that the final byte is aligned with the byte boundary, as shown in FIG. Also, EOL
When outputting a code, as shown in FIG. 2C, "0" is padded after the code data so that the end of the EOL code becomes a byte boundary.

When the last byte of the code data is completed, the compression / expansion circuit 2 instructs the EOL signal output section 6 to output the EOL signal and outputs the completed code data to the outside. The EOL signal output unit 6 outputs an EOL signal together with code data output from the compression / expansion circuit 2 in response to an instruction from the compression / expansion circuit 2.

EOL output from the EOL signal output unit 6
When the signal is received to the outside, the binary image data compression / decompression processing device 1 returns to the state of performing processing from the start of the line, and is in the state of waiting for the data input of the next line. here,
When the image data is input to the compression / expansion circuit 2, the code data is sequentially generated from the byte boundary and output as the next line as described above.

In this way, the code data output to the outside is E, as shown in FIG. 2 (b) or 2 (c).
The final byte is aligned with the byte boundary by the fractional bit generation instruction unit 5 that operates in response to the notification from the OL input signal holding unit 4. Therefore, when the image is partially expanded from the code data corresponding to the entire image, or when the editing is performed at the code data level, the bit shift operation for aligning the byte boundaries is unnecessary.

Further, since the EOL signal is output from the EOL signal output section 6 at the same time that the last byte of the code data is output, the break of each line can be easily discriminated by this EOL signal, and the fill bit is filled. Processing such as insertion can be easily executed.

In the above embodiment, the coding by the MH system was described as an example with reference to FIG. 2, but it can be applied to other coding systems (MR system, MMR system).

[0026]

As described above, according to the present invention, when the last code data corresponding to the coded line does not coincide with the byte boundary, "0" is inserted in the fractional bits and the last byte is converted into the byte. Since the EOL signal is output at the time of outputting the final byte while aligning with the boundary, it is possible to always make the start of the line a byte boundary and easily determine the break of each line. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a binary image data compression / expansion processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of binary image data to be processed and code data output by a compression process.

[Explanation of symbols]

1 ... Binary image data compression / expansion processing device, 2 ... Compression / expansion circuit, 3 ... I / O register group, 3a ... Encoding mode register, 4 ... EOL input signal holding unit, 5 ... Fractional bit generation instruction unit, 6 ... EOL signal output section.

Claims (1)

[Claims] 1. A binary image data compression circuit for inputting binary image data to generate code data, a coding mode register for designating a coding mode in the binary image data compression circuit, and the code. When the encoding mode for encoding each line is designated by the encoding mode register, the binary image data compression circuit is padded with "0" to the fractional bits of the code data at the end of the line to obtain the final byte. Of the fractional bit generation instructing means for aligning the byte boundaries of the binary image data compression circuit and the final byte of which the byte boundary is aligned by the fractional bit generation instruction means is output from the binary image data compression circuit. And an EOL signal output means for outputting an EOL signal indicating that the image data is the binary image data compression device.