JPH06302782A - Manufacture of capacitor - Google Patents

Abstract

PURPOSE:To increase the relative permittivity of ferroelectric layer for increasing the accumulated charge amount by a method wherein a MgO layer as an insulator is formed on the lower side of lower electrode of a capacitor comprising an upper electrode, ferroelectric layer and lower electrode. CONSTITUTION:Impurities are selectively implanted in the surface of a Si substrate 11 to form a diffused layer 12 and then a SiO2 layer 13 is formed on the whole surface. Next, single crystalline Si is epitaxially grown by ELO and then after the formation of a single crystal Si layer 14, a MgO layer 15 is epitaxially grown on the layer 14. Next, the periphery of the MgO layer 15 is removed leaving the epitaxially grown layer of the MgO layer 15 only intact. Later, Ti or Ta layer 16 is formed by CVD step etc. Next, a Pt layer 17 as a lower electrode is formed on the Ti or Ta layer 16, the MgO layer 15 and the SiO2 layer 13. In such a constitution, the MgO layer 15 is provided on the lower side of the Ti layer 17 as the lower electrode but on the upper side of the single crystal Si layer 14 so that the relative permittivity of a ferroelectric layer 18 may be increased thereby enabling the accumulated charge amount to be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor in a semiconductor memory such as a dynamic random access memory (hereinafter referred to as DRAM) which can obtain a higher charge storage capacity. is there.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1; JAPANESE JOURNAL OF APPLIED PHYSIC
S) 30 [9B] (1991-9) Japan Society of Applied Physics,
Kenji IIJIMA, Ichiro UEDA and Koichi KUGIMIYA “Preparation and Properties of Lead Zirconate-Tit
anate Thin Films ”P.2149-2151 Reference 2; JAPANESE JOURNAL OF APPLIED PHYSIC
S) 29 [4] (1990-4) Japan Society of Applied Physics, Ma
saru OKADA ， Koji TOMINAGA ， Teruhiko ARAKI ， Shigeh
“Metalorganic” by isa KATAYAMA and Yukio SAKASHITA
Chemical Vapor Deposition of c-Axis Oriented PZT T
hin Films ”P.718-722 Reference 3; JOURNAL OF APPLIEDPHYSICS 60 [8] (1986)
-10) American Institute of Physics (US) Kenji IIJIMA, Ryoichi TAKAYAMA, Yos
hihiro TOMITA and Ichiro UEDA “Epitaxial growth
and the crystallographic ， dielectric, and pyroelec
tric properties of lanthanum-modified lead titanate
thin films ”P.2914-2919 Reference 4; Applied Physics Letter (APPLIED
PHYSICS LETTER) 57 [23] (1990-12) American Institute of Physics (US)
Toshiyuki SAKUMA, Shintaro YAMAMICHI, Shogo MATSUB
ARA, Hiromu YAMAGUCHI and Yoichi MIYASAKA “Barr
ierlayers for realization of high capacitance dens
ity in SrTiO ₃ thin-film capacitor on silicon ”P.2
431-2433 Reference 5; Applied Physics Letter (APPLIED
PHYSICS LETTER) 60 [4] (1992-1) American Institute of Physics (US) J.
L.Glenn, Jr., GWNeudeck, CKSubramanian and J.P.De
nton's'A fully planar method for creating adjace
nt “self-isolating” silicon-on-insulator and epi
taxial layers byepitaxial lateral overgrowth 'P.4
83-485 Reference 6; Applied Physics Letter (APPLIED
PHYSICS LETTER) 58 [20] (1991-5) American Institute of Physics (US)
DKFork, FAPonce, JC Tramontana, TH Geballe “Epitaxial MgO on Si (001) for Y-Ba-Cu-O thin-film
growth by pulsed laser deposition "P.2294-2296 Fig. 2 is a schematic cross-sectional view showing a configuration example of a conventional capacitor in a DRAM. In this capacitor manufacturing method, impurities are first formed on the surface of a Si substrate 1. The diffusion layer 2 is selectively implanted to form the diffusion layer 2. The SiO ₂ layers 3a and 3b are formed by a chemical vapor deposition method (hereinafter referred to as a CVD method) in a state of overlapping with a part of the diffusion layer 2. , The diffusion layer 2 and the SiO ₂ layers 3a and 3b so as to be in contact with the poly S
The i layer 4 is formed. The diffusion layer 2 constitutes a MOS transistor with another diffusion layer and a gate electrode (not shown).
On the upper side of the poly-Si layer 4, Pt / T is formed by the CVD method or the like.
The i (or Pt / Ta) layer 5, the ferroelectric layer 6, and the upper electrode 7 are sequentially formed. Pt / Ti (or Pt / T
a) The layer 5 is used as a lower electrode, and the ferroelectric layer 6 and the upper electrode 7 constitute a capacitor. With this capacitor and the MOS transistor,
A DRAM memory cell is constructed. Regarding the method of forming a capacitor, various proposals have been made in Documents 1 to 6.

By the way, PbTiO which is the ferroelectric layer 6
₃ , Pb (Zr, Ti) O ₃ , (Pb, La) (Zr,
Thin film formation of Ti) O ₃ etc. is performed by reactive sputtering,
When a film is formed on Pt formed on a single crystal MgO substrate as described in References 1 to 3 by a forming method such as metalorganic chemical vapor deposition, the relative dielectric constant is It is known that the ferroelectric layer 6 can be formed to have an excellent electrical property and be electrically excellent. Further, as described in Document 6, single crystal MgO can be formed on single crystal Si. On the other hand, when the ferroelectric layer 6 is formed on the Si substrate 1 to form a capacitor, Pt /
By forming an electrode having a laminated structure of Ti and Pt / Ta, it is possible to create a capacitor having a larger charge storage amount. In Reference 1, reactive sputtering is used as a film forming method of Pb (Zr, Ti) O ₃ . The board is P
t / MgO, Pt / Si, a _{Pt / R-Al 2 O 3} .
Although Pt / MgO is electrically inferior to Pt / R-Al ₂ O ₃ on top, it is described that the relative dielectric constant is about 500. In Reference 2, a metal organic chemical vapor deposition method is used as a film forming method of Pb (Zr, Ti) O ₃ . The board is P
t / MgO. Then, contents such as a relative dielectric constant of about 500 are described. In Reference 3, (Pb, La)
Reactive sputtering is used as a film forming method of (Zr, Ti) O ₃ , a substrate is Pt / MgO, and a relative dielectric constant is about 400. In Reference 4, SrTiO ₃
Is formed by ion beam sputtering. The substrates are Pt / Ti and Pt / Ta. It describes contents such as no decrease in capacity that occurs when a film is formed on Pt / Si. In Reference 5, ELO (Epitaxial Lateral Overgrowt) on a (100) plane Si substrate and SiO ₂ is used.
It is described that a single crystal layer can be formed by carrying out h). In Document 6, the MgO film is formed by the pulse laser deposition method. The substrate is (100) plane Si. (20
0) plane MgO can be epitaxially grown.

[0004]

However, the conventional method of manufacturing a capacitor has the following problems.
In the conventional method, the area of the capacitor is generally small, and there is no method for compensating for it, so the amount of accumulated charge is small.
Therefore, in order to solve this drawback, it is conceivable to apply the techniques of the above-mentioned documents 1 to 3. However, the above-mentioned document 1
Methods 3 to 3 are techniques for forming a ferroelectric film on a MgO bulk single crystal, and therefore cannot be applied to devices using a Si substrate. The present invention provides a method for manufacturing a capacitor, which solves the problem that the amount of accumulated charge is small, as a problem that the above-mentioned conventional technique has.

[0005]

In order to solve the above problems, the present invention provides an ELO epitaxial layer on a Si substrate.
Then, conductivity is imparted to the epitaxial layer and a MgO layer is selectively formed on the epitaxial layer by epitaxial growth. Forming a conductor layer in contact with the epitaxial layer and the MgO layer,
A lower electrode is formed on the MgO layer and the conductor layer. Then, after forming a ferroelectric layer on the conductor layer, an upper electrode is formed on the ferroelectric layer.

[0006]

According to the present invention, since the method of manufacturing a capacitor is configured as described above, the capacitor is composed of the upper electrode, the ferroelectric layer and the lower electrode. Since the MgO layer as an insulator is formed below the lower electrode of this capacitor, the relative dielectric constant of the ferroelectric layer is increased,
The amount of accumulated charge can be increased. Therefore, the above problem can be solved.

[0007]

1 is a schematic sectional view of a capacitor in a DRAM showing an embodiment of the present invention. In this capacitor manufacturing method, first, an n ⁺ diffusion layer (hereinafter, simply referred to as a diffusion layer) 12 is formed on a Si substrate 11. The SiO ₂ layer 13 is formed so as to partially overlap the diffusion layer 12. Next, Si is epitaxially grown by ELO and conductivity is imparted to the single crystal Si.
The film 14 is formed. Then, a MgO layer 15 is formed on the single crystal Si film 14 by epitaxial growth, a Ti or Ta layer 16 is formed thereon, and a Pt layer 17 as a lower electrode is further formed thereon. After forming the ferroelectric layer 18 on the lower electrode, and then forming the upper electrode 19 on the ferroelectric layer 18, the manufacture of the capacitor is completed.

3A to 3D and 4A to 4D.
(D) is a manufacturing process diagram of the capacitor shown in FIG. 1.
Referring to these figures, the detailed manufacturing process (1) of FIG.
(4) will be described. (1) Step of FIG. 3A The impurity is selectively implanted into the surface of the Si substrate 11 to form the diffusion layer 12. SiO _{2 is formed on the} entire surface by the CVD method or the like
After forming the layer 13, an opening is formed in a part of the layer 13 by photolithography and etching. Next, ELO
After the single crystal Si is epitaxially grown by the method, the single crystal Si layer 14 is formed by performing a treatment to make it conductive. The conditions for epitaxial growth of the single crystal Si layer 14 include, for example, (SiH ₂ Cl ₂
+ HCl + H ₂ ) gas at 950 ° C. Also,
The treatment for imparting conductivity is performed by ion implantation of arsenic (As) and heat treatment.

(2) Steps of FIGS. 3B to 3D An MgO layer 15 is epitaxially grown on the single crystal Si layer 14. As conditions for epitaxial growth of the MgO layer 15, for example, a Mg metal target is used and ablation is performed by a XeCl excimer laser in an O ₂ atmosphere to grow the MgO layer 15 at 400 ° C. Next, the peripheral portion of the MgO layer 15 is removed by photolithography and etching, and only the epitaxial growth layer of the MgO layer 15 is left. After that, if the Ti or Ta layer 16 is formed by sputtering or CVD, the coating layer as shown in the drawing is formed.

(3) Steps of FIGS. 4A to 4C The Ti or Ta layer 16 is a layer disposed above and below the MgO layer 15, that is, a single crystal because the MgO layer 15 is an insulating layer. In order to maintain electrical contact between the Si layer 14 and the Pt layer 17, which will be described later, the Si layer 14 is formed into a shape as shown in FIG. Also,
By disposing the Ti or Ta layer 16, the single crystal Si layer 1
4 diffuses on the surface of the Pt layer 17 and oxidizes to form a low dielectric constant Si.
It is possible to prevent the O2 layer from being formed at the interface between the Pt layer 17 and the ferroelectric layer 18 described later. Then, the Pt layer 17 as the lower electrode is formed on the Ti or Ta layer 16, the MgO layer 15, and the SiO 2 layer 13 by the sputtering method.

(4) Step of FIG. 4D: A ferroelectric layer 18 is formed on the Pt layer 17. The ferroelectric layer 18 is made of PbTiO ₃ , Pb (Zr, T
i) O ₃ , (Pb, La) (Zr, Ti) O ₃ or the like is used. An upper electrode 19 is formed on the upper side of the ferroelectric layer 18. The formation of the ferroelectric layer 18 is performed under any of the following conditions (i) to (iii). (I) By a reactive sputtering method using a composite metal target, for example, 650 ° C. in Ar containing 50% O _2.
Form with a degree. (Ii) It is formed by a sputtering method using an oxide sintered body target at about 650 ° C. in Ar containing 10% O ₂ . (iii) Formed using a multi-target. When the CVD method is used, it is formed at about 650 ° C. This forms a capacitor.

As described above, in this embodiment, since the MgO layer 15 as the oxide film is provided below the Pt layer 17 as the lower electrode and above the single crystal Si layer 14, the ferroelectric substance is used. The relative permittivity of the layer 18 can be increased, and the amount of accumulated charge can be increased. Further, by disposing the Ti or Ta layer 16 as described above, it is possible to prevent the single crystal Si layer 14 from diffusing on the surface of the Pt layer 17 and oxidizing to form a low dielectric constant SiO ₂ layer. . The present invention is not limited to the above-mentioned embodiment, and various modifications can be made, for example, by treating each layer by a method different from the above technique. Further, in the above-mentioned embodiment, the method of manufacturing the capacitor of the DRAM is described, but the present invention is not limited to this, and the method of manufacturing the capacitor other than the DRAM is also described.
The same applies.

[0013]

As described above in detail, according to the present invention, since the MgO layer is selectively formed between the lower electrode and the epitaxial layer, the relative dielectric constant of the ferroelectric layer can be improved. It is possible to increase the charge storage amount, and thereby increase the charge storage amount.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a capacitor showing an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a conventional capacitor.

FIG. 3 is a manufacturing process diagram of FIG. 1.

FIG. 4 is a manufacturing process diagram of FIG. 1.

[Explanation of symbols]

11 Si Substrate 12 n ⁺ Diffusion Layer 13 SiO ₂ Layer 14 Single Crystal Si Layer 15 MgO Layer 16 Ti or Ta Layer 17 Pt Layer 18 Ferroelectric Layer 19 Upper Electrode

Claims (1)

[Claims] 1. An epitaxial layer is formed on a Si substrate using ELO, conductivity is imparted to the epitaxial layer, and a MgO layer is selectively formed on the epitaxial layer by epitaxial growth. A conductor layer is formed in contact with the MgO layer, a lower electrode is formed above the MgO layer and the conductor layer, a ferroelectric layer is formed on the conductor layer, and a ferroelectric layer is formed on the ferroelectric layer. A method of manufacturing a capacitor, which comprises forming an upper electrode.