JPH06301440A - Digital processing system - Google Patents

Abstract

PURPOSE:To speed up the operation of a single-chip microcomputer, etc., equipped with a timer circuit and to improve its software design efficiency by simplifying the access procedure of the timer circuit and decreasing the number of dynamic steps at the time of timer circuit access by the central processing unit, etc. CONSTITUTION:The timer circuit TIM is provided with a carry flag TCUF which is selectively set while each counter is placed in carry operation and a bus interface circuit BI which holds a wait signal WT selectively at an effective level when a counter read cycle is executed while the carry flag TCUF is set; when the wait signal WT is held at the effective level, the counter read cycle by the central processing unit is selectively extended to make a wait until the carry operation ends. Consequently, counter counted values of the timer circuit which are read out in the counter read cycle can all be guaranteed and flag confirming operation after the read is omitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital processing system and, more particularly, to a technique which is particularly effective when used in a single-chip microcomputer having a timer circuit having a clock / calendar function.

[0002]

2. Description of the Related Art Second counter, minute counter, hour counter,
There is a timer circuit having a day counter, a day of the week counter, a month counter and a year counter, and having a so-called clock / calendar function. There are also microcomputers that couple such timer circuits to their system bus. The microcomputer further has a central processing unit coupled to its system bus, which central processing unit has a counter read cycle for reading the count value of each counter of the timer circuit as needed.

Regarding a timer circuit (clock / calendar LSI) having a clock / calendar function and its counter read (time read) cycle, for example, 198
It is described on page 13, etc. of "Watch / Calendar LSI HD64610 Data Sheet" issued by Hitachi, Ltd. in September 1997.

[0004]

In the above timer circuit, the second counter divides the clock signal of, for example, 32.768 KHz (kilohertz) by 1/256 and further divides by 1/256.
The carry is cyclically carried in response to the rising edge of the carry signal of 1 second cycle obtained by dividing by 128, and the minute counter is cyclically carried in response to the overflow signal of the second counter. In addition, the hour counter receives the overflow signal of the minute counter and carries the signal periodically, and the day counter, the day of the week counter, the month counter and the year counter receive the overflow signals of the preceding hour counter, day counter and month counter, respectively. And carry is carried out cyclically. From these facts, the carry required time as the timer circuit is, for example, about 100 μs (microsecond), especially when all the counters are carried.

On the other hand, the central processing unit of the microcomputer operates synchronously by receiving a clock signal of, for example, 20 MHz (megahertz) which is formed asynchronously with the clock signal of the timer circuit, according to a program stored in the read-only memory. Executes predetermined arithmetic processing. In other words, the central processing unit operates asynchronously with the timer circuit, and the counter read cycle by the central processing unit is relatively unlikely to be executed within the carry operation period as described above. Also exists. Needless to say, when the counter read cycle by the central processing unit is executed during the carry operation of the timer circuit,
The normality of the read result is not guaranteed. Therefore, the timer circuit has a carry flag for indicating that a carry operation has been performed, and the central processing unit that accesses the timer circuit has a flag clear cycle for resetting the carry flag. .

When it is necessary to read the count value of each counter of the timer circuit, the central processing unit first executes a flag clear cycle in step ST11 to set the carry flag of the timer circuit, as shown in FIG. Reset. Next, in steps ST12 to ST18, seven counter read cycles are executed to sequentially read the count values of the second counter, minute counter, hour counter, day counter, day counter, month counter and year counter, and store them in registers. Then, in step ST19, the flag read cycle is executed to read the state of the carry flag of the timer circuit, and the state of the carry flag is determined by the jump instruction in step ST20. At this time, if the read carry flag remains in the reset state, the central processing unit determines that the carry operation has not been performed during the execution of the seven counter read cycles. , Terminate access to the timer circuit. If the read carry flag is changed to the set state, it is determined that the carry operation of the timer circuit is performed during the execution of the seven counter read cycles, and step ST11 is performed. Start again from the flag clear cycle of.

However, the inventors of the present application have encountered the following problems in an attempt to accelerate the speed of the microcomputer including the timer circuit. That is,
Second counter of timer circuit, minute counter, hour counter,
As described above, the time required to carry the day counter, the day counter, the month counter, and the year counter is about 100 μs even when all the counters carry, and the central processing unit during the carry operation. The probability that the counter read cycle is executed by 1 becomes as small as about 1 / 10,000 when the carry cycle is 1 second. However, as described above, the central processing unit must execute the flag clear cycle for resetting the carry flag of the timer circuit prior to the counter read cycle, and after executing the counter read cycle, the flag read cycle is executed. A cycle must be executed to read the carry flag, and a series of processes must be repeated depending on the state. As a result, the number of dynamic steps of the central processing unit during normal operation increases, the speed of the microcomputer is restricted, the program becomes complicated, and the efficiency of software design is reduced.

An object of the present invention is to simplify the access procedure of the timer circuit and reduce the number of dynamic steps when accessing the timer circuit of the central processing unit or the like. Another object of the present invention is to promote the speeding up of a microcomputer having a timer circuit and the like, and to improve the software design efficiency thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a timer circuit having a clock / calendar function, a carry flag that is selectively set during the carry operation of the counter and a counter read cycle by the central processing unit while the carry flag is set. And a bus interface circuit that selectively sets the wait signal to the effective level when the wait signal is executed, and the counter read cycle is selectively extended when the wait signal is set to the effective level until the carry operation ends. Meet up.

[0011]

According to the above means, since the counter count value of the timer circuit read in each counter read cycle can be all guaranteed and the confirmation operation by the carry flag can be omitted, the timer circuit of the central processing unit or the like can be omitted. The number of dynamic steps during access can be reduced. As a result, it is possible to promote the speed-up of a microcomputer having a timer circuit, simplify the program, and improve the software design efficiency.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a single-chip microcomputer (digital processing system) to which the present invention is applied.
A block diagram of one embodiment of is shown. An outline of the configuration and operation of the single-chip microcomputer of this embodiment will be described first with reference to FIG. The circuit elements forming each block in FIG. 1 are the crystal oscillator X1.
And X2 are formed on one semiconductor substrate surface such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the single-chip microcomputer of this embodiment has a so-called stored program type central processing unit CPU as its basic constituent element. Further, the microcomputer is a system bus BU
A read-only memory ROM, a random access memory RAM, a timer circuit TIM and a serial communication interface SCI, which are coupled to the central processing unit CPU via S, are provided, and two oscillator circuits O are further provided.
It comprises SC1 and OSC2. The system bus BU
As will be described later, S is composed of an address bus AB and a data bus DB each having a predetermined bit, and a control bus including an address strobe signal AS, a read / write signal RW, a wait signal WT and the like.

Here, the central processing unit CPU has the system clock signal CPS supplied from the oscillation circuit OSC2.
It operates synchronously in accordance with the (second clock signal), executes predetermined arithmetic processing in accordance with a program stored in the read-only memory ROM, and controls / controls each unit of the microcomputer. Read-only memory RO
M is a mask ROM or the like having a predetermined storage capacity, and stores programs and fixed data necessary for controlling the central processing unit CPU. Further, the random access memory RAM is a static type RA having a predetermined storage capacity.
The processing result of the central processing unit CPU, the control data, etc. are temporarily stored.

On the other hand, the timer circuit TIM, as will be described later, has a second counter, a minute counter, an hour counter, a day counter, which are stepped in accordance with a timer clock signal CPT (first clock signal) supplied from the oscillator circuit OSC1.
It implements the so-called clock / calendar function, including the day of the week counter, month counter, and year counter. The count value of each counter of the timer circuit, that is, the counter data is selectively read by executing the counter read cycle and transmitted to the central processing unit CPU. The serial communication interface SCI is, for example, a serial input / output device or the like coupled to the outside of the microcomputer and a central processing unit CPU or a random access memory R.
It controls and manages the exchange of data with AM.

Next, the oscillator circuit OSC1 is coupled to the crystal oscillator X1 via a corresponding pair of external terminals, forms a timer clock signal CPT, and supplies it to the timer circuit TIM. Further, the oscillator circuit OSC2 is coupled to the crystal oscillator X2 via the corresponding pair of external terminals to form the system clock signal CPS to generate the central processing unit CPU.
Etc. In this embodiment, the crystal oscillator X1
Has a relatively low natural frequency of 32.768 KHz, and the timer clock signal CPT is
It has the same frequency as the natural frequency of 1. Further, the crystal oscillator X2 has a relatively high natural frequency of 20 MHz,
The system clock signal CPS has the same frequency as the natural frequency of the crystal oscillator X2.

FIG. 2 is a block diagram showing an embodiment of the timer circuit TIM included in the single chip microcomputer shown in FIG. Further, FIG. 3 shows a partial circuit diagram of an embodiment of the bus interface circuit BI included in the timer circuit TIM of FIG. Further, FIG. 4 shows a signal waveform diagram of an embodiment of the timer circuit TIM of FIG. 2, and FIG. 5 shows the timer circuit T of FIG.
An access process flow diagram for one embodiment of a central processing unit CPU accessing an IM is shown. Based on these figures, the specific configuration and operation of the timer circuit TIM included in the single-chip microcomputer of this embodiment, the access processing flow of the central processing unit CPU, and its characteristics will be described. Note that FIG. 4 shows a relative time relationship of each signal, and its absolute value is not accurate.

In FIG. 2, the timer circuit TIM includes a frequency dividing circuit FD1 for receiving the output signal of the oscillator circuit OSC1, that is, a timer clock signal CPT, and the frequency dividing circuit F.
Internal clock signal S for carrying the output signal of D1
And a frequency dividing circuit FD2 forming P. In this embodiment, the frequency of the timer clock signal CPT is set to 32.768 KHz as described above, and the frequency division ratios of the frequency dividing circuits FD1 and FD2 are 1/256 and 1/12, respectively.
Eight. Therefore, the frequency of the internal clock signal SP is, as shown in FIG.
It is 1 / (256 × 128) of PT, that is, 1 Hz, and its cycle is 1 second.

The output signal of the frequency dividing circuit FD2, that is, the internal clock signal SP is used as a carry signal of the second counter SE.
In addition to being supplied to CC, it is supplied to the carry flag TCUF as its set signal. Of these, the seconds counter SECC is a so-called BCD (Binary Code).
d Decimal: Binary coded decimal number) It is composed of a coded 7-bit 60-bit counter and carries a carry every 1 second in response to the rising edge of the carry signal, that is, the internal clock signal SP. The carry flag TCUF is
The counter data selection circuit CDS, which will be described later, is set by receiving the rising edge of the internal clock signal SP.
Upon receiving the rising edge of the internal control signal TR output from L, the reset state is set. The count value of the second counter SECC, that is, 7-bit counter data is supplied to the first input terminal of the counter data selection circuit CDSL, and its overflow signal OS is supplied to the minute counter MINC as its carry signal. The output signal TF of the carry flag TCUF is supplied to the bus interface circuit BI via the internal bus IBUS.

The minute counter MINC is composed of a 7-bit BCD coded hexadecimal counter, and carries a carry every minute in response to a carry signal, that is, a rising edge of the overflow signal OS of the second counter SECC. The count value of the minute counter MINC, that is, 7-bit counter data is supplied to the second input terminal of the counter data selection circuit CDSL, and its overflow signal ON is supplied to the hour counter HRC as a carry signal. On the other hand, the hour counter HRC is composed of a BCD-encoded 6-bit 24-bit counter and carries a carry signal, that is, a minute counter MINC.
1 upon receiving the rising edge of the overflow signal ON
Carry is carried every hour. The count value of the hour counter HRC, that is, 6-bit counter data, is supplied to the third input terminal of the counter data selection circuit CDSL, and its overflow signal OH is used as a carry signal for the day counter DAY.
C and the day of the week counter WKC.

Similarly, the day counter DAYC is composed of a BCD-encoded 6-bit 28th to 31st counter and receives a carry signal, that is, a rising edge of the overflow signal OH of the hour counter HRC, and a digit is displayed every day. Be raised. Further, the day-of-week counter WKC is composed of a BCD-coded 3-bit hex counter and carries out carry every day in response to a carry signal, that is, a rising edge of the overflow signal OH of the hour counter HRC. The count value of the day counter DAYC, that is, 6-bit counter data is supplied to the fourth input terminal of the counter data selection circuit CDSL, and its overflow signal OD is supplied to the month counter MTHC as a carry signal. The count value of the day of the week counter WKC, that is, 3-bit counter data is supplied to the fifth input terminal of the counter data selection circuit CDSL. The step mode of the day counter DAYC includes a month counter MTHC and a year counter YRC, which will be described later.
The 28-31 mode is selectively switched according to the count value of.

Further, the month counter MTHC is composed of a BCD-coded 5-bit binary counter and carries a carry signal, that is, an overflow signal O of the day counter DAYC.
Carry a carry every month in response to the rising edge of D. The count value of the month counter MTHC, that is, the 5-bit counter data is the sixth value of the counter data selection circuit CDSL.
Of the overflow signal OM supplied to the input terminal of
It is supplied to the year counter YRC as a carry signal. On the other hand, the year counter YRC is not particularly limited, but the BCD
It consists of a coded 8-bit 100-base counter,
In response to the carry signal, that is, the rising edge of the overflow signal OM of the month counter MTHC, carry is carried out every year. The count value of the year counter YRC, that is, 8-bit counter data is supplied to the seventh input terminal of the counter data selection circuit CDSL.

The counter data selection circuit CDSL has counter data selection signals CSL0 to CSL (not shown) supplied from the bus interface circuit BI when the counter read cycle is executed by the central processing unit CPU.
According to 6, the counter data of the second counter, minute counter, hour counter, day counter, day counter, month counter and year counter is selectively selected and supplied to the bus interface circuit BI via the internal bus IBUS. These counter data are transmitted from the bus interface circuit BI to the central processing unit CPU via the data bus DB. In this embodiment, the counter data selection circuit CD
SL includes a carry look-ahead (carry look ahead) circuit and outputs its output signal TR when the carry by the second counter, minute counter, hour counter, day counter, day counter, month counter and year counter is no longer necessary. Temporarily set to high level. This output signal TR is supplied to the carry flag TCUF as a reset signal. As a result, the carry flag TCUF receives the rising edge of the internal clock signal SP and starts the carry operation of the second counter SECC as shown in FIG.
It is set to the high level for the minimum required time until the carry operation of all counters is completed.

The timer circuit TIM of this embodiment further includes a control register CREG and a cycle interrupt flag PIR.
F and carry prohibit flag CUIF. Among them, the control register CREG holds various control data for controlling / adjusting the operation of the timer circuit TIM, and is accessed from the central processing unit CPU via the bus interface circuit BI and the internal bus IBUS. Further, the cycle interrupt flag PIRF is set to a cyclic state by receiving the internal control signal PS output from the frequency dividing circuit FD2, and its output signal PF is transmitted to the bus interface circuit BI via the internal bus IBUS. After that, it is transmitted to the central processing unit CPU as an interrupt request signal IR. As a result, in the microcomputer of this embodiment, the timer circuit TIM can generate a periodic interrupt in accordance with the internal control signal PS to the central processing unit CPU. The periodic interrupt flag PIRF receives the interrupt request signal IR by the central processing unit CPU, and the internal control signal P by the bus interface circuit BI.
When R is set to high level, it is reset.

On the other hand, the carry inhibit flag CUIF is an internal control signal C output from the bus interface circuit BI.
Upon receiving the rising edge of S, the state is set, and upon receiving the falling edge of the internal control signal CR, the state is reset. In this embodiment, the timer circuit TIM
As described above, the n counter, that is, seven counters, the minute counter, the hour counter, the day counter, the day counter, the month counter, and the year counter are provided, and the counter read cycle by the central processing unit CPU is Correspondingly executed first to seventh counter read cycles. In these counter read cycles, the timer circuit TIM is selectively designated by the upper predetermined bits of the address signal supplied via the address bus AB, and the second counter, minute counter, The hour counter, the day counter, the day of the week counter, the month counter, and the year counter are selectively designated. Therefore, the bus interface circuit B
As shown in FIG. 3, I is a decoder DEC1 for receiving a predetermined upper bit of the address signal and selectively raising the internal control signal TEN or CS or CR to a high level,
It includes a decoder DEC2 which receives predetermined lower bits of the address signal and selectively sets the counter data selection signals CSL0 to CSL6 to the high level.

Decoder D of bus interface circuit BI
The internal control signal TEN formed by EC1 is shown in FIG.
As shown in, the first to seventh counter read cycles are executed to repeatedly set the high level,
In other words, it is supplied to each part of the timer circuit TIM as an activation signal of these counter read cycles. On the other hand, the internal control signal CS is set to a high level by executing the first counter read cycle, and the internal control signal CR is
It is set to a high level by executing the seventh counter read cycle. As described above, the internal control signal CS is
The carry inhibit flag CUIF is supplied as a set signal, and the internal control signal CR is supplied as a reset signal thereof. As a result, the carry inhibit flag CUIF is set to the high level from the start of the first counter read cycle by the central processing unit CPU to the end of the seventh counter read cycle.

By the way, as shown in FIG. 2, the output signal CF of the carry inhibit flag CUIF is the second counter SE.
Supplied to CC. When the output signal CF of the carry inhibit flag CUIF is set to the low level, the second counter SECC performs the carry operation in response to the rising edge of the internal clock signal SP as described above, but outputs the carry inhibit flag CUIF. When the signal CF is at high level, the carry operation is not performed even if the internal clock signal SP is at high level. The second counter SECC includes a latch for holding the high level of the internal clock signal SP, and starts the carry operation again when the carry inhibit flag CUIF is returned to the low level. As a result of these, prior to the carry of the second counter SECC, the central processing unit CP
When the counter read cycle by U is started, the carry operation of the second counter SECC by the internal clock signal SP is prohibited, and each counter of the timer circuit TIM is not updated while the counter read cycle is executed.

On the other hand, as shown in FIG. 3, the bus interface circuit BI of the timer circuit TIM of this embodiment receives the internal control signal TEN output from the decoder DEC1 at one of its input terminals and receives the other input. The terminal includes a NAND gate NAG1 for receiving the output signal TF of the carry flag TCUF. The output signal of the NAND gate NAG1 is used as a wait signal WT by the central processing unit CP.
Transmitted to U. Needless to say, Nandgate NAG
The output signal 1 of 1 or the wait signal WT is the output signal TF of the carry flag TCUF with the internal control signal TEN at the high level, as shown as access B in FIG.
Is set to a high level, in other words, when the counter read cycle is started, the carry operation of the second counter, minute counter, hour counter, day counter, day counter, month counter and year counter by the internal clock signal SP has already been performed. When started, it is selectively set to low level. When the wait signal WT is set to the low level, the central processing unit CPU temporarily stops its operation,
A so-called waiting state is set. Then, this waiting state is continued until the wait signal WT is returned to the high level, and when the wait signal WT is returned to the high level, the operation before stop is restarted.

From these things, as shown in FIG. 5, the access of the timer circuit TIM by the central processing unit CPU is suddenly started from step ST1, that is, the read (read) operation of the second counter SECC by the first counter read cycle. And then step ST2
To ST7, that is, the reading operations of the minute counter, the hour counter, the day counter, the day of the week counter, the month counter and the year counter in the second to seventh counter read cycles need only be sequentially executed. Further, for the above reason, all the counter data of the timer circuit TIM that is read in each counter read cycle has a guaranteed value, and therefore, the flag reset cycle prior to the counter read cycle and the flag read cycle after the counter read cycle are completed The flag confirmation operation can be omitted, and accordingly, the number of dynamic steps in accessing the timer circuit of the central processing unit CPU can be reduced. As a result, the timer circuit TIM
It is possible to accelerate the speedup of a microcomputer equipped with, and to simplify the program and improve the software design efficiency.

The second counter S in step ST1
When the read operation of the ECC and the carry operation of the timer circuit TIM compete with each other and the wait signal WT is set to the low level,
The central processing unit CPU is in a waiting state, but during this period, the program is in a stopped state, and thus the waiting does not affect the normal dynamic step number of the central processing unit CPU. The probability that the carry operation of the timer circuit TIM and the counter read cycle of the central processing unit CPU compete with each other is as described above.
Since it is less than 1 / 10,000, the decrease in the processing capacity of the central processing unit CPU due to this waiting is so small that it can be ignored.

By applying the present invention to a digital processing system such as a single chip microcomputer provided with a timer circuit having a clock / calendar function as shown in the above embodiment, the following operational effects can be obtained. To be That is, (1) In the timer circuit having the clock / calendar function, the carry flag selectively set during the carry operation of the counter and the central processing unit or the like while the carry flag is set. A bus interface circuit that selectively sets the wait signal to the effective level when the counter read cycle is executed is provided, and when the wait signal is set to the effective level, the counter read cycle of the central processing unit is selectively extended and carried. By waiting until the operation is completed, there is an effect that all the counter count values of the timer circuit read in each counter read cycle can be guaranteed.

(2) According to the above item (1), it is possible to omit the confirmation operation by the carry flag. (3) According to the above items (1) and (2), it is possible to reduce the number of dynamic steps when accessing the timer circuit of the central processing unit or the like. (4) According to the above items (1) to (3), it is possible to accelerate the speed of a microcomputer provided with a timer circuit, simplify the program, and improve the software design efficiency. To be

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the frequencies of the timer clock signal CPT and the system clock signal CPS can be set arbitrarily, and the crystal oscillators X1 and X2 externally attached to the oscillation circuits OSC1 and OSC2 are replaced with, for example, a ceramic oscillator or the like. be able to. Also, the timer circuit TIM
May be accessible by a functional block other than the central processing unit CPU.
It may be independently formed on a surface of a semiconductor substrate different from the above.
The single-chip microcomputer does not have to include a random access memory RAM and a serial communication interface SCI, etc.
The block configuration can take various embodiments.

In FIG. 2, when the counter read cycle is executed by the central processing unit CPU during the carry operation of the timer circuit TIM, waiting can be performed by a method other than the wait signal WT. Further, the frequency division ratios of the frequency division circuits FD1 and FD2 can be arbitrarily set according to the frequency of the timer clock signal CPT, or the same frequency division ratio may be realized by three or more frequency division circuits. Further, the block configuration of the timer circuit TIM shown in FIG. 2, the circuit configuration of the bus interface circuit BI shown in FIG. 3, the signal form shown in FIG. 4 and the access procedure of the timer circuit TIM shown in FIG. It is not restricted by these embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto, and, for example, the same. It can also be applied to microprocessors and workstations equipped with various timer circuits. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a digital processing system including at least timer circuits that operate asynchronously with each other and a functional block that accesses the timer circuits.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a timer circuit having a clock / calendar function, a carry flag that is selectively set during the carry operation of the counter and a counter read cycle by the central processing unit while the carry flag is set. And a bus interface circuit for selectively setting the wait signal to the effective level when the wait signal is executed, and selectively extending the counter read cycle of the central processing unit when the wait signal is set to the effective level and ending the carry operation. Wait until you do. As a result, all the counter count values of the timer circuit read out in each counter read cycle can be guaranteed, and the confirmation operation by the carry flag can be omitted. Therefore, the number of dynamic steps when the timer circuit is accessed by the central processing unit is reduced. be able to. As a result, it is possible to promote the speed-up of a microcomputer having a timer circuit, simplify the program, and improve the software design efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

2 is a block diagram showing an embodiment of a timer circuit included in the single-chip microcomputer shown in FIG.

3 is a partial circuit diagram showing an embodiment of a bus interface circuit included in the timer circuit of FIG.

FIG. 4 is a signal waveform diagram showing an embodiment of the timer circuit of FIG.

5 is an access processing flow chart showing an embodiment of a central processing unit for accessing the timer circuit of FIG.

FIG. 6 is an access processing flow chart showing an embodiment of a central processing unit for accessing a conventional timer circuit.

[Explanation of symbols]

CPU ... Central processing unit, BUS ... System bus, ROM ... Read only memory, RAM ...
Random access memory, TIM ... Timer circuit,
SCI ... Serial communication interface, OSC1-OSC2 ... Oscillation circuit, X1-X2.
..Crystal oscillators AB ... Address bus, DB ...
Data bus, AS ... Address strobe signal, RW
... Read / write signal, IR ... Interrupt request signal, WT ... Wait signal, BI ... Bus interface circuit, IBUS ... Internal bus, CREG ...
Control register, SECC ... second counter, MINC.
..Minute counter, HRC ... hour counter, DAYC
..Day counters, WKC ... Day of the week counters, MTHC
・ ・ ・ Month counter, YRC ・ ・ ・ Year counter, PIRF
... Cycle interrupt flag, CUIF ... Carry prohibit flag, TCUF ... Carry flag, CDSL ...
Counter data selection circuit, FD1 to FD2 ... Frequency divider circuit. DEC1 to DEC2 ... Decoder, NAG1 ...
・ Nand gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideyuki Ochiai 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Ltd. (72) Inventor Noriyuki Tanaka 5-chome, Mizumizumoto-cho, Kodaira-shi, Tokyo 22-1 No. 1 in Hitachi Microcomputer System Co., Ltd. (72) Inventor Keitsugu Nemoto 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Nobuo Kitagawa Kodaira, Tokyo 5-20-1 Joumizuhonmachi, Ichi, Ltd. Within the Semiconductor Business Division, Hitachi, Ltd.

Claims (4)

[Claims] 1. A timer circuit including a counter that carries a carry periodically according to a first clock signal, and a second clock signal that is formed asynchronously with the first clock signal and operates as necessary. A functional block having a counter read cycle for reading the count value of the counter, and when the counter read cycle by the functional block is executed during the carry of the counter, until the carry operation is completed. A digital processing system characterized by selectively extending the counter read cycle. 2. The counter read cycle is selectively extended by setting a wait signal to a valid level, and the timer circuit selectively outputs the carry operation of the counter. A carry flag to be set, and a bus interface circuit for selectively setting the wait signal to an effective level when the counter read cycle is executed while the carry flag is set. The digital processing system of claim 1, wherein the digital processing system is a digital processing system. 3. The counter comprises n counters that are substantially connected in series, and the counter read cycle includes first to nth counters for sequentially reading the count values of the n counters. The timer circuit is configured to selectively carry a carry inhibit flag from the start of the first counter read cycle to the end of the nth counter read cycle. 3. The digital processing according to claim 1 or 2, wherein the carry operation of the counter is selectively prohibited while the carry prohibit flag is set. system. 4. The digital processing system is a microcomputer, the functional block is a central processing unit, and the timer circuit is formed on the same semiconductor substrate surface as the central processing unit. The digital processing system according to claim 1, 2 or 3, wherein the digital processing system is provided.