JPH0630035B2 - Clock switching control method for clock synchronous system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] [Prior Art] Problems to be Solved by the Invention Means for Solving Problems Problems Working Example [Summary] Having a plurality of devices and oscillators Regarding the clock switching control method in a clock synchronous system, the purpose is to guarantee a logical phase relationship between the basic clock and a clock having an integral multiple period when switching the clock. For multiple pairs with clocks,
Means for detecting the occurrence of an abnormality and generating a selection instruction signal for selecting a pair of a normal basic clock and a corresponding integer multiple clock, and a normal basic clock and an integer corresponding thereto according to the selection instruction signal Means for selecting a set of double clocks, means for detecting a change in the selection instruction signal in relation to the phase of the integer multiple clock, and means for outputting a set of the selected basic clock and integer multiple clock And a means for determining the timing of the output based on the selected basic clock and the integer multiple clock and the change of the selection instruction signal, and an abnormality occurs in the basic clock or the integer multiple clock being used. When this is done, a set of a normal basic clock and a corresponding integer multiple clock is output as an internal clock at a timing that maintains a logical phase relationship. To configure.

[Industrial application field]

The present invention relates to a clock switching control system, and more particularly to a clock switching control system in a clock synchronous system having a plurality of devices and oscillators.

A large-scale computer system and a multiprocessor system are generally composed of a plurality of devices (for example, semiconductor devices). Then, each device is operated in synchronization with a basic clock commonly supplied to each device from an external oscillator.

Therefore, if a failure occurs in the supply of the basic clock, the logic circuit malfunctions and the system goes down.

[Conventional technology]

Multiple oscillators (and cables) to prevent the system from going down due to a failure of the basic clock oscillator itself or the clock system such as the cable that transmits the basic clock
It is possible to prepare.

That is, the oscillation outputs (clocks) of a plurality of oscillators are supplied to each of a plurality of devices. Then, at a certain point of time, a clock from one oscillator is selected and used as a basic clock, and when an abnormality occurs in the clock, the basic clock is switched to a clock from another oscillator.

As a result, even if one clock system fails,
You can avoid system down and continue system operation.

[Problems to be solved by the invention]

According to the above-mentioned conventional technique, when there are a plurality of devices that use a plurality of clocks having different cycles in the system, a malfunction of the logic circuit may occur when the clocks are switched.

For example, when the system is composed of a plurality of devices that use only a single cycle clock, or when the system is composed of a single device, switching the clocks does not cause a big problem. On the other hand, each device operates in synchronization with the basic clock and a clock having a cycle of an integral multiple (2, 4, 8 ...) Of the basic clock (clock obtained by dividing the basic clock by an integral multiple). In this case, it is necessary to guarantee a logical phase relationship between the basic clock and a clock having a cycle of an integral multiple thereof when switching the clock.

However, according to the conventional technique, it is not possible to know at what timing the clock switching was performed.
This may cause the logical phase relationship to collapse, resulting in a malfunction.

An object of the present invention is to provide a clock switching control method capable of guaranteeing a logical phase relationship between a basic clock and a clock having a cycle of an integral multiple thereof when switching clocks.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention, showing a clock synchronous system according to the present invention.

In FIG. 1, 1 is a processor including a logic circuit such as a processor, 11 is a clock selection circuit, 12 is a selection instruction circuit, 13 is a timing determination circuit, 14 is a rise detection circuit, 15 is a clock output circuit, 21 and Reference numeral 22 is a clock distribution source (clock generation means) including an oscillator.

The clock distribution sources 21 and 22 respectively supply the basic clock and a clock having a cycle of an integral multiple of this (hereinafter, n-fold clock) to the processing device 1.

According to the selection instruction signal from the selection instruction circuit 12, the clock selection circuit 11 selects a pair of the basic clock and the n-times clock supplied from one clock distribution source from the two basic clocks and the n-times clock. , Send.

The selection instruction circuit 12 receives the four clocks from the clock distribution sources 21 and 22 and monitors whether there is any abnormality in these clocks. When there is an abnormality in the clock from one clock distribution source currently used by the processing device 1, the selection instruction circuit 12 issues a selection instruction signal to select and use the clock from the other clock distribution source. Send out.

The rise detection circuit 14 rises (changes) the selection instruction signal.
To detect.

The timing determination circuit 13 receives the pair of basic clocks and the n-fold clock selected by the clock selection circuit 11 and the detection output of the rising edge detection circuit 14 and determines the timing at which the selected pair of clocks should be transmitted. To do.

The clock output circuit 15 outputs the pair of selected basic clocks and n-fold clocks to the inside of the processing device 1 as internal clocks at the timing indicated by the timing determination circuit 13. Then, in the processing device 1, a plurality of clocks are further generated using the basic clock and the n-fold clock and used as operation clocks.

[Action]

A clock having no abnormality (that is, a clock distribution source) is selected by the clock selection circuit 11 by detecting the presence or absence of abnormality in the clocks from the plurality of clock distribution sources by the selection instruction circuit 12.

In addition, when the selection instruction signal was generated when the pair of basic clocks used by the processing device 1 and the n-fold clock had a logical phase relationship (the relevant clock is changed from the selected state to the non-selected state). Is the rising edge detection circuit 1
4 and the timing determination circuit 13,
Retained. Based on this, the newly selected pair of clocks is output from the clock output circuit at the timing when the newly selected pair of basic clocks and the n-fold clock have the same logical phase relationship.

Therefore, when switching the clocks, the matching of the logical phase relationship is maintained between the pair of unselected clocks and the pair of newly selected clocks.

Note that the output of the clock from the clock output circuit 11 is interrupted until the output of the newly selected pair of clocks is started after the output of the pair of unselected clocks is stopped.

〔Example〕

 FIG. 2 is a block diagram of an embodiment of the present invention.

In FIG. 2, 111 and 112 are the first and second
Clock selection circuits corresponding to the clock selection circuit 11, reference numerals 121 and 122 are first and second selection instruction circuits corresponding to the selection instruction circuit 12, and 131 and 132 are first and second timing determination circuits. Yes Corresponding to the timing determination circuit 13, 141 and 142 are first and second rising edge detecting circuits corresponding to the rising edge detecting circuit 14, 31 to 33 are OR (O
R) gate circuit, 211 is an oscillator, and 212 is an n-fold frequency dividing circuit.

Further, FIGS. 3 to 6 are concrete configuration diagrams of main circuit blocks of the embodiment shown in FIG.

FIG. 3 shows the first and second clock selection circuits 111 and 112 and the first and second selection instruction circuits 121 and 1.
A part of 22 is shown. In FIG. 3, 34
1 to 356 are D flip-flop circuits, 361 to 366 are AND gate circuits, and 371 and 372 are OR gate circuits.

FIG. 4 mainly shows the first timing determination circuit 131. In FIG. 4, 381 is a JK flip-flop circuit, 382 to 387 are D flip-flop circuits, 40 is an exclusive logic circuit, 411 is an AND gate circuit, 311 and 321 are OR gate circuits, which correspond to the OR gate circuits 31 and 32, respectively. What you do.

FIG. 5 shows the first and second rising edge detection circuits 141 and 142 and the second timing determination circuit 132. In FIG. 5, 388 to 393 are D flip-flop circuits, 412 to 414 are AND gate circuits, 42 is an inverter circuit, and 322 is an OR gate circuit corresponding to the OR gate circuit 32.

FIG. 6 shows the clock output circuit 15.
In FIG. 6, 394 to 397 are D flip-flop circuits, 415 to 418 are AND gate circuits, 4
Reference numeral 3 is an OR gate circuit, and 312 and 323 are OR gate circuits respectively corresponding to the OR gate circuits 31 and 32.

Hereinafter, referring to FIGS. 3 to 6 as needed, the second
The illustrated embodiment will be described.

In the clock distribution source 21, the oscillator 211 generates a clock (a-clock) having a predetermined cycle, which is a basic clock, and divides the basic clock a-clock into n times by an n-fold frequency dividing circuit 212 to obtain an n-times clock. (A-clock (n)) is generated. The clock distribution source 22 is the same as the clock distribution source 21, and generates the basic clock b-clock and its n-fold clock b-clock (n). Basic clocks a-clock and b
-Clock and n-fold clocks a-clock and b-clock have the same period, but their phases are different because they are not synchronized. These four clocks are distributed to the plurality of processing devices 1 (only one is shown in FIG. 2) by each clock distribution source.

A first clock selection circuit 111 and a first selection instruction circuit 1 corresponding to a pair of clocks a-clock and a-clock (n).
21 and a first rising edge detection circuit 141 are provided. The same applies to the other pair of clocks b-clock and b-clock (n).

The first selection instruction circuit 121 internally selects the selection instruction signal Se when selecting the clocks a-clock and a-clock (n).
lect a is set to a high level (logic 1), and as shown in FIG. 3, the selection instruction signal Select a
-1 and Select a-2 are set to high level. on the other hand,
The first selection instruction circuit 121 selects the selection instruction signal Select- when the clocks a-clock and a-clock (n) are not selected.
a, Select a-1 and Select a-2 are set to low level (logic 0).

The first clock selection circuit 111 has a selection instruction signal Select
When a-1 is at a high level, the clocks a-clock and a-clock (n) are output as the clocks a-clock-1 and a-clock (n) -1, as can be seen from FIG. On the other hand, when the selection instruction signal Select a-1 is at low level, the two outputs of the clock selection circuit 111 are both at low level (supply is stopped).

Second selection instruction circuit 122 and second clock selection circuit 1
The same applies to 12.

In FIG. 3, the device 1 supplies a selection instruction signal (outputs of the OR gate circuits 371 and 372) to another device (not shown), and the same selection instruction signal of another device is supplied to the AND gate circuit. 361 and 362 receive it. As a result, the selection (switching) of the clock a-clock or b-clock can be performed at the same time in all the devices.

The output of the OR gate circuit 31 is a-clock (n) -1 when the clock a-clock is selected, b-clock (n) -1, clocks a-clock and b when the clock b-clock is selected.
When −clock is not selected, it is set to low level (clock supply is stopped).

The same applies to the output of the OR gate circuit 32.

When the supply of the clock in use is stopped, the first timing determination circuit 131 determines the stopped timing, specifically, how many basic clocks were supplied in the cycle of n times the clock. Remember.

Therefore, as shown in FIG. 4, the JK flip-flop circuit 381D flip-flop circuit 382 and the exclusive OR circuit 40 synchronize with the rising edge of the n-fold clock in use, and A high level pulse signal is generated only during the cycle. This pulse signal is sequentially transferred to the D flip-flop circuits 383 to 387 in synchronization with the basic clock being used. Then, the transfer of the pulse signal is stopped by the signal OUT ENABLE (described later) which is set to the low level in accordance with the stop of the supply of the basic clock in use. Therefore, by knowing which of the D flip-flop circuits 384 to 387 holds the pulse signal, it is possible to know at what timing the supply of the basic clock (and the n-fold clock) is stopped.

The number of D flip-flop circuits 383 to 387 is (n + 1) when the clock is n times as many. That is,
The illustrated example is an example in which a quadruple clock is supplied.
By setting the number of (n + 1) clocks, the timing of a new clock can be set in the next (immediate) cycle after the cycle of the n-fold clock (which should be selected next) when the supply of the clock in use is stopped. It can regulate and supply can be started.

The first rising edge detection circuit 141 includes the first selection instruction circuit 1
From 21, the selection instruction signal Select a-1 and the selection instruction signal Select a-2 generated after a predetermined time delay are supplied. The same applies to the second rising edge detection circuit 142.

When the clock a-clock is deselected and the clock b-clock is selected, the procedure is as follows. That is, the selection instruction signal
By the low level of Select a-1, the output of the first clock selection circuit 111 is set to the low level, and the output of the first rising edge detection circuit 141 is also set to the low level. On the other hand, the high level of the selection instruction signal Select b-1 causes the second clock selection circuit 112 to output the clocks b-clock-1 and b-clock.
-Clock (n) -1 is output. In addition, the selection instruction signal Se
lect b-2 is an n-fold clock b to be newly selected
−High level synchronized with rising edge of clock (n). Therefore, the output of the OR gate circuit 33 is the n-fold clock b-
The level is changed from low level to high level in synchronization with the rising edge of clock (n). That is, the OR gate circuit 33 generates a pulse signal which is set to the high level only immediately after the clock switching.

The second timing decision circuit 132 is supplied with what time the clock newly selected by the clock selection circuit and started to be output, specifically, what number of clocks in the cycle of n times the clock. Indicates whether it is in a state.

For this purpose, a high-level pulse signal obtained as the output of the OR gate circuit 33 and synchronized with the n-fold clock is used. As shown in FIG. 5, this pulse signal is
AND gate circuit 414, D flip-flop circuit 38
8 and the inverter circuit 42, in synchronism with the rising edge of the newly selected n-fold clock, the pulse signal is converted to a high level for one cycle of the newly selected basic clock. The converted pulse signal is sequentially transferred to the D flip-flop circuits 389 to 393 in synchronization with the newly selected basic clock. Therefore, by knowing which of the D flip-flop circuits 390 to 393 holds the pulse signal, it is possible to know in which state (timing) the newly selected clock is.

The number of D flip-flop circuits 389 to 393 is the same as that in FIG.

The clock output circuit 15 outputs a new internal clock whose logical phase relationship is the same as that of the internal clock whose supply has been stopped, based on the outputs of the first and second timing circuits 131 and 132.

Therefore, as shown in FIG. 6, the outputs X0, X1, X2 and X3 of the first timing decision circuit 131 and the second timing decision circuit 131
An AND signal with the outputs Y0, Y1, Y2 and Y3 of the timing decision circuit 132 is used. The pulse signal held in any of the D flip-flop circuits 384 to 387 and the D flip-flop circuits 390 to 393.
The pulse signals in progress (transfer) are those that are synchronized with the rising edge of the n-fold clock and are sequentially transferred with the basic clock. Therefore, when both the corresponding outputs are at the high level, it indicates that the logical phase of the new clock is equal to the logical phase of the clock whose supply is stopped at the stopped timing. As a result, the signal OU
T ENABLE is set to high level and the internal clock is output.

The D flip-flop circuits 394 to 397 and the AND gate circuits 415 and 416 are for keeping the signal OUT ENABLE at a high level.

FIG. 7 is an operation waveform diagram. From clocks a-clock and a-clock (n), clocks b-clock and b-clock are obtained.
It shows the case where the internal clock is switched to (n).

n-times clocks a-clock (n) and b-clock (n) (n =
It is assumed that 4) is in reverse phase.

The exclusive OR circuit 40 outputs a pulse signal that is brought to a high level for one cycle of the basic clock a-clock in synchronization with the rising of the n-fold clock a-clock (n).
Now, at the timings shown, the clocks a-clock and a-c
Suppose the supply of lock (n) is stopped. At this time, the pulse signals are sequentially transferred to the D flip-flop circuit 38.
It is held at 4. That is, the signal X3 is at the high level and the other signals X0, X1 and X2 are at the low level.

Clock system n times the clock system to be selected next b-cl
The output of the OR gate circuit 33 becomes high level in synchronization with the earliest rise of ock (n) (after the supply of the clock is stopped).

As a result, the AND gate circuit 414 outputs a pulse signal which is at a high level for one cycle of the basic clock b-clock in synchronization with the rising of the n-fold clock b-clock (n). This pulse signal is the basic clock b-cloc
The data is sequentially transferred from the D flip-flop circuit 389 in synchronization with k.

When this pulse signal is transferred to the D flip-flop circuit 390 and the output Y3 becomes high level, the signal OUT
ENABLE is set to high level, and the output of the internal clock is restarted at this timing.

Although the present invention has been described above with reference to the embodiments, the present invention can be variously modified according to the spirit thereof.

For example, each of the clock distribution source and the device for receiving the clock from this point can be installed in any number.

Further, in the clock distribution source or the device that receives the clock, a plurality of n-fold clocks having different cycles are generated,
Alternatively, when used, a clock that is the greatest common divisor of these n-times clocks (for example, an 8-times clock when there are 2, 4, 8-times clocks) is used as the n-times clock in the present invention from the clock distribution source to each device. Is supplied to.

〔The invention's effect〕

As described above, according to the present invention, in the clock switching in the clock synchronous system, the new logical phase relationship is the same as the logical phase relationship between the supply-stopped basic clock and the n-fold clock. Since the basic clock and the n-fold clock can be supplied, malfunction of the logic circuit can be prevented and system reliability can be improved.

[Brief description of drawings]

 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment, FIG. 3 is a specific block diagram, FIG. 4 is a specific block diagram, FIG. 5 is a specific block diagram, and FIG. Figure is a concrete configuration diagram, Figure 7 is an operation waveform diagram. In the drawing, 1 ... Processing device, 21, 22 ... Clock distribution source, 11, 111, 112 ... Clock selection circuit, 12, 121, 122 ... Selection instruction circuit, 13, 131, 132 ... Timing determination circuit, 14, 141, 142 ... Rise detection circuit, 15 ... Clock output circuit.

Claims (1)

[Claims] 1. A plurality of clock generating means (21, 22) each for generating a basic clock and an integer multiple clock corresponding to the basic clock and having an integer multiple period thereof, and a logic circuit. A clock synchronous system comprising the basic clock, the integral multiple clock, or a device (1) that operates in synchronization with a clock generated based on the basic clock, the integral multiple clock, and a plurality of the basic clock and the integral multiple clock. Means (12) for detecting the occurrence of an abnormality and selecting a pair of a normal basic clock and an integer multiple clock corresponding thereto for the pair of, and a normal basic signal according to the selection instruction signal. Means (11) for selecting a pair of clock and corresponding integer multiple clock
Means for detecting a change in the selection instruction signal in relation to the phase of the integral multiple clock; means for outputting a set of the selected basic clock and integral multiple clock; Selected basic clock and integral multiple clock,
The device (1) is provided with means (13) for determining the timing of the output based on the change of the selection instruction signal, and the basic clock or the integer multiple clock used in the device (1) is abnormal. Clock switching control characterized by selecting a pair of a normal basic clock and a corresponding integer multiple clock when the above occurs, and outputting them as internal clocks at timings that maintain a logical phase relationship. method.