JPH06295589A - Semiconductor storage element - Google Patents

Abstract

PURPOSE:To increase storage capacity per unit area of a semiconductor chip by forming a plate electrode, which becomes the confronted electrode of a node electrode on a bit line side, while dividing it into plural pieces in each bit line and varying impressed voltage to each divided plate electrode in accordance with each write-in data. CONSTITUTION:By an individual charging to each of divided plate electrodes PL0-PL3 by a circuit 5 for generating the potential of a plate electrode, data are written in capacitances C0-C3 constituting storage cells. That is, by the circuit 5, the voltage of Vss or Vcc/2 is impressed to the plate electrode 1, and the impressed voltages Vss/Vcc are variably set for each of divided plate electrodes PL0-PL3 in accordance with the write-in data. The stored charge amount of the divided storage capacitance C0+C1+C2+C3, which are formed by the divided plate electrodes PL0-PL3 through the circuit 5, is variably set stepwise by the number of combinations of impressed level 1 or 0 to each of divided plate electrodes PL0-PL3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and further to a DRA which retains data by charges accumulated in a capacitor.
The present invention relates to a technique effective when applied to an M-type semiconductor memory element, for example, a technique effective when applied to a large-capacity 1-transistor / cell-type DRAM.

[0002]

2. Description of the Related Art Each memory cell in a one-transistor / cell type DRAM is composed of a memory capacity for holding data by accumulating charges and a transfer MOS for switching data input / output to / from this memory capacity. Each memory cell is selected by a word line and a bit line. Data writing / reading is selectively performed with respect to the storage capacitance connected to the bit line via the transfer MOS switched by the word line. The storage capacitor is formed between the node electrode connected to the bit line via the transfer MOS and the plate electrode facing the node electrode.

Here, in the conventional DRAM, the plate electrode is commonly formed for each memory mat with respect to the node electrode independently formed for each memory cell. That is, the node electrode is formed as an individual electrode that is independent for each memory cell, while the plate electrode that is the counter electrode thereof is formed as a common electrode.

A constant reference voltage HVC (Vcc / 2) is always applied to this plate electrode. Then, based on the applied voltage (Vcc / 2) to this plate electrode, H
Storage of 1-bit data by (high) / L (low) is performed for each storage cell (for example, "Nikkei Microdevice, May 1989, published by Nikkei BP, Inc. (n
o. 47) ", pages 38-46).

[0005]

However, the present inventors have clarified that the above-mentioned technique has the following problems.

That is, in the conventional semiconductor memory element, the data stored in one transfer MOS is only one bit. Therefore, when trying to increase the capacity of the memory, the transfer MOS
There is a problem in that the required number of semiconductor chips naturally increases, which also increases the required area of the semiconductor chip.

An object of the present invention is to provide a technique for increasing the storage capacity per unit area of a semiconductor chip by suppressing an increase in the required number of transfer MOSs accompanying an increase in memory capacity.

The above and other objects and characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, among the electrodes forming the storage capacitor for holding data, the plate electrode serving as the counter electrode of the node electrode on the bit line side is divided into a plurality of parts within each bit line, and each divided plate is formed. The voltage applied to the electrodes is changed according to the write data.

[0011]

According to the above-mentioned means, the transfer MOS
The charge accumulated in the storage capacitor connected to the bit line via the multi-value can be made multi-valued by a combination of the voltages applied to the respective divided plate electrodes, and by this multi-valued, a plurality of bits can be stored for one transfer MOS. Data can be stored.

Thus, the object of increasing the storage capacity per unit area of the semiconductor chip by suppressing the increase in the required number of transfer MOSs accompanying the increase in the capacity of the memory is achieved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a semiconductor memory device to which the technique of the present invention is applied. The semiconductor memory device here performs a DRAM type memory operation.

In FIG. 1, 1 is a plate electrode, 2 is a bit line, 3 is a word line, 4 is a transfer MOS, and 5 is a transfer electrode.
Is a plate electrode potential generation circuit, 6 is a bit line, 7 is a bit line data amplification circuit, 8 is a Y select signal by a logic signal, 9 is a plate electrode control signal by a logic signal, 10 is a plate electrode potential control signal by a logic signal , 11 are node electrodes A on the bit line side, and 12 and 13 are write (Wr
te) data line, 14 is a plate electrode I / O (input / output) line, 15 is a plate level selector, and 16 is I / O
It is an O switch.

The plate electrode 1 is provided independently for each bit line 6, and is divided into a plurality of (four) plate electrodes (PL0 to PL3) in each bit line 6. Each divided plate electrode (PL0 to P
To L3), the potentials that are variably set stepwise by the plate electrode potential generation circuit 5 are individually applied.

A plate electrode (PL
0 to PL3) form divided storage capacitors (C0 to C3) with the node electrode 11, respectively. By the parallel combined capacity of the divided storage capacities (C0 to C3), one transfer capacity (C0 + C1 + C2) is provided for each transfer MOS4.
+ C3) is formed.

Next, the operation will be described.

In FIG. 1, first, when data is written in the capacitors (C0 to C3) forming a memory cell, the bit line 2
When 6 has a full amplitude and the transfer MOS 4 is in the ON state (word line 3 is in the H state), the storage capacity (C0 to C
Between the divided plate electrodes (PL0 to PL3) of 3) and the node electrode 11, charging / accumulation of electric charges according to data, that is, data writing is performed.

This writing is performed by individual charging of the divided plate electrodes (PL0 to PL3) by the plate electrode potential generation circuit 5. That is, the plate electrode potential generation circuit 5 generates a voltage of Vss or Vcc / 2 and applies it to the plate electrode 1, but the applied voltage (Vss
/ Vcc) is a divided plate electrode (P
It is variably set for each L0 to PL3). That is, each divided plate electrode (PL0 to PL3) has a voltage of Vcc /
With reference to 2, the battery is charged with a potential of either H level or L level.

By charging each of the divided plate electrodes (PL0 to PL3) by the plate electrode potential generation circuit 5,
The accumulated charge amount of the storage capacitance (C0 + C1 + C2 + C3), which is the parallel combined capacitance of the divided storage capacitances (C0 to C3) formed by each divided plate electrode (PL0 to PL3), is stored in each divided plate electrode (PL0 to PL3). The number of combinations of application levels (1 or 0) is variably set in stages.

That is, four divided plate electrodes (PL
0 to PL3) when the applied voltage is selected from two types of 1 (= Vss) and 0 (= Vcc / 2), the storage capacity (C0 + C1 + C2 + C4) that is the parallel combined capacity of the divided storage capacities (C0 to C3) With respect to the accumulated charge amount of, it is possible to obtain four combinations by the plate electrode potential generation circuit 5. In this case, one transfer MOS4
Storage capacity switched by (C0 + C1 + C2 +
In C4), four kinds of multivalued data can be held respectively.

Further, four divided plate electrodes (PL0 to PL0
The applied voltage to PL3) is 1 (= Vss) and 0, respectively.
When selecting from three types (= Vcc / 2) and -1 (= Vcc), the accumulated charge amount of the storage capacity (C0 + C1 + C2 + C4) that is the parallel combined capacity of the divided storage capacities (C0 to C3) is the plate electrode potential generation. The circuit 5 makes it possible to obtain 9 combinations. As a result, the storage capacity (C0 + C1 + C2 + C4) switched by one transfer MOS 4 can hold 9 sets of multi-valued data.

As described above, the storage capacity (C0 + C1 + C) in which data is written according to the plurality of accumulated charge amounts.
Data can be read from 2 + C3) by setting all the divided plate electrodes (PL0 to PL3) to Vcc / 2, similarly to a normal DRAM.

The read data from the bit lines 2 and 6 is CD
From the relationship of (bit line capacity) / CS (storage capacity), Vc
It is read out as a minute signal which can take a total of 8 levels of plus / minus 4 with respect to c / 2. The read minute signal is amplitude-amplified and level-discriminated by a dedicated bit line data amplifier circuit 7. The output of this level discrimination is sent to the plate electrode potential generation circuit 5 for the retry because of the plate electrode control signal 9 (RPL0 to RPL0).
PL3).

To read data to the outside, the plate electrode control signal 9 (RPL0 to RPL3) system signal is set to Y.
I / O for plate electrode linked to select signal 8
This can be done by connecting to the line 14 (RWPL0 to RWPL3).

In addition, when writing data from the outside, Y
Select signal 8 and select plate electrode I / O line 14
(RWPL0 to RWPL3) is used to select the potential applied to each divided plate electrode (PL0 to PL3), and Vcc or Vss is applied to the bit lines 2 and 6.

In the above-described semiconductor memory device, when writing data, the plate electrode in the bit line is divided into m pieces and the potential applied to each is divided by Vss or Vcc /.
By selecting from two types, it is possible to write a plurality of data corresponding to (2m + 1) kinds of charge amounts to one transfer MOS.

When the potential of each divided plate electrode is set to Vcc / 2 except during the writing operation, the signal potential of the data read to the bit line is m +/- m with respect to Vcc / 2. The electric potential of can be obtained. That is, 2m kinds of data can be read from one memory cell.

As described above, among the electrodes forming the storage capacitor for holding data, the plate electrode serving as the counter electrode of the node electrode on the bit line side is divided into a plurality of parts within each bit line, and By varying the applied voltage to each divided plate electrode according to the write data,
The charge accumulated in the storage capacitor connected to the bit line via the transfer MOS can be multi-valued by the combination of the voltages applied to the divided plate electrodes. With this multi-valued conversion, data of a plurality of bits can be stored in one transfer MOS.

As a result, it is possible to suppress an increase in the required number of transfer MOSs as the memory capacity increases and to increase the storage capacity per unit area of the semiconductor chip.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, among the electrodes forming the storage capacitor for holding data, the plate electrode serving as the counter electrode of the node electrode on the bit line side is made independent for each bit line, and the plate electrode corresponding to the selected bit line is provided. The voltage applied to each may be varied according to the write data. That is, although the plate electrode is independent for each bit line, it is possible to store multi-valued data by changing the applied voltage without dividing the plate electrode in the bit line.

[0035]

The outline of the typical inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, the effect that the storage capacity per unit area of the semiconductor chip can be increased by suppressing the increase in the required number of transfer MOSs accompanying the increase in the memory capacity is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a main part of a semiconductor memory device to which the technique of the present invention is applied.

[Explanation of symbols]

 1 plate electrode PL0 to PL3 divided plate electrode C0 to C3 divided storage capacity 2 bit line 3 word line 4 transfer MOS 5 plate electrode potential generation circuit 6 bit line 7 bit line data amplifier circuit 8 Y select signal by logic signal 9 by logic signal Plate electrode control signal 10 Control signal of plate electrode potential by logical signal 11 Node electrode on bit line side 12, 13 Data line for write (Write) 14 I / O (input / output) line for plate electrode 15 Plate level selector 16 I / O switch

Claims (2)

[Claims] 1. A DRAM type semiconductor memory device, wherein a plurality of plate electrodes serving as a counter electrode of a node electrode on the bit line side among electrodes forming a storage capacitor for holding data are provided in each bit line. A semiconductor memory element, which is formed by dividing and is capable of varying an applied voltage to each divided plate electrode in accordance with write data. 2. A DRAM type semiconductor memory device, wherein plate electrodes serving as counter electrodes of node electrodes on the bit line side among electrodes forming a storage capacitor for holding data are independent for each bit line, and A semiconductor memory device characterized in that a voltage applied to a plate electrode corresponding to a selected bit line is varied according to write data.