JPH06291799A - Modulator - Google Patents

Abstract

PURPOSE:To reduce power consumption and the cost by halving the number of digital filters in comparison with the number of a conventional filter, dividing filter coefficients into n (= sampling frequency/symbol speed) series thereby reducing the quantity of arithmetic operation to 1/n. CONSTITUTION:A multi-carrier signal is fed to a gray coder 2, in which the signal is coded into an in-phase component and an orthogonal component and they are given to an S/P converter 3, in which they are divided into subcarrier signal and inputted and converted by a symbol converter 4 and stored in shift registers 5-20. Each of digital filters 25-28 uses filter coefficients divided into n pieces of series and any of the shift registers selectively to execute simultaneously orthogonal modulation by DELTAomega and operation of a low pass filter. Orthogonal modulation by 2.DELTAomega is executed by modulators 45, 46 and the result is D/A-converted by D/A converters 37, 38, and a modulator 47 executes orthogonal modulation by a carrier signal. Thus, the quantity of arithmetic operation is reduced to 1/2n of a conventional constitution and the power consumption and cost are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitter of a digital mobile communication system using multiple subcarriers.

[0002]

2. Description of the Related Art FIG. 5 shows one of four conventional multi-subcarriers.
It is a block diagram of a 6QAM modulator. In FIG. 5, 10
Reference numeral 1 is a transmission data input terminal, which is connected to 102. Reference numeral 102 denotes a Gray coder for generating I and Q weighted impulses from the transmission data.
It is connected to the. Reference numeral 103 is a serial / parallel converter that converts the outputs I and Q of the Gray encoder 2 into four sets of signals Ii and Qi, which are connected to 102 and 104 to 111. Reference numeral 104 denotes a first band limiting 88th-order FIR low-pass filter, which is connected to 103 and 112. Reference numeral 105 is a second band limiting 88th-order FIR low-pass filter, which is connected to 103 and 113. 1
Reference numeral 06 is a third band limiting 88th-order FIR low-pass filter, which is connected to 103 and 114. Reference numeral 107 denotes a fourth band limiting 88th-order FIR low pass filter, which is connected to 103 and 115. Reference numeral 108 denotes a fifth band limiting 88th-order FIR low pass filter,
It is connected to 03,116. 109 is a sixth band limiting 88th-order FIR low-pass filter,
It is connected to 117. 110 for the seventh band limitation 8
8th-order FIR low pass filter, 103, 118
It is connected to the. 111 is the 88th F for the eighth band limitation
It is an IR low pass filter and is connected to 103 and 119. 112 is a first DA converter, and 10
It is connected to 4,121. Reference numeral 113 is a second DA converter, which is connected to 105 and 122. Reference numeral 114 denotes a third DA converter, which is connected to 106 and 123. 115 is a fourth DA converter, and 107, 12
4 is connected. Reference numeral 116 is a fifth DA converter, which is connected to 108 and 125. Reference numeral 117 denotes a sixth DA converter, which is connected to 109 and 126.
Reference numeral 118 denotes a seventh DA converter, which is connected to 110 and 127. 119 is an eighth DA converter,
1, 128 are connected. 120 is a synthesizer, which is connected to 121-128. 121 is the first
, And is connected to 112 and 129. 122 is a second analog multiplier, 113,
129 is connected. Reference numeral 123 is a third analog multiplier, which is connected to 114 and 129. Reference numeral 124 is a fourth analog multiplier, which is connected to 115 and 129. 125 is a fifth analog multiplier,
6,129 are connected. Reference numeral 126 is a sixth analog multiplier, which is connected to 117 and 129. 12
Reference numeral 7 is a seventh analog multiplier, which is connected to 118 and 129. 128 is an eighth analog multiplier,
It is connected to 119 and 129. Reference numeral 129 is an analog adder, which is connected to 121 to 128. 130
Is a transmission output terminal and is connected to 129.

The operation of the conventional example of the multi-subcarrier 16QAM modulator configured as described above will be described below. 64 from the transmission data input terminal 101
When the kb / s transmission data is input, the Gray encoder 10
2 has 4 ternary weighted impulses for I and Q every 4 bits.
It occurs at intervals of kHz. Serial / parallel converter 10
3 sequentially separates the impulse generated in 102 into four sets of subcarriers. These are (I1, Q1), (I2,
Q2), (I3, Q3), and (I4, Q4). These are band-limited by the filters 104 to 111, respectively, and DA-converted by the D / A converters 112 to 119, respectively.
On the other hand, the synthesizer 120 generates a total of eight types of carriers of four types of in-phase and quadrature subcarriers, and the analog multipliers 121 to 128 and the analog adder 129 perform the four-channel quadrature modulation on the DA conversion outputs and add them. Output terminal 130
To output the output signal S (t) represented by (Equation 1).

[0004]

[Equation 1] S (t) = I ₁ (t) ・ cos (ω _c -3 ・ Δω) t + Q ₁ (t) ・ sin (ω _c -3 ・ Δω) t + I ₂ (t) ・ cos (ω _c -Δω) t + Q ₂ (t) ・ sin (ω _c -Δω) t + I ₃ (t) ・ cos (ω _c + Δω) t + Q ₃ (t) ・ sin (ω _c + Δω ) t + I ₄ (t) ・ cos (ω _c +3 ・ Δω) t + Q ₄ (t) ・ sin (ω _c +3 ・ Δω) t where I ₁ (t), Q ₁ (t) , ... Are transmission filter outputs (after analog conversion), ω _c is the carrier angular frequency, and Δω is the quadrature modulation angular frequency.

As described above, the multi-subcarrier 16QAM modulator can also be realized by this conventional example.

[0006]

However, in the above-described conventional multi-subcarrier 16QAM modulator, since it is necessary to calculate a band-limiting digital filter having a large order of 88 taps eight times every 36 kHz, real-time processing is performed. Therefore, high-speed arithmetic execution is required, which makes it difficult to reduce power consumption and cost of the device.

[0007]

In order to achieve the above object, the present invention provides a symbol converting means for converting the signals Ii and Qi of each channel into a signal sequence suitable for simultaneous quadrature modulation, and the symbol converting means. The storage means for storing the signal sequence, the data sequentially read from the storage means, and the data of the coefficient table are sequentially selected, and the modulation angular frequency Δω
, A plurality of digital filters that simultaneously perform quadrature modulation and low-pass filtering, and a plurality of quadrature modulations that perform a product-sum operation on the data of the sine function table or cosine function table for each output of the corresponding set of the digital filters. It is provided with quadrature modulation means, D / A conversion means for converting the output of the quadrature modulation means into an analog signal, and means for quadrature modulating the D / A converted signal with a carrier signal.

[0008]

The symbol converting means converts both Ii and Qi channels into a signal sequence suitable for quadrature modulation at the same time,
The digital filter sequentially selects this data and the data in the coefficient table and simultaneously performs the quadrature modulation and the low-pass filter processing at the modulation angular frequency Δω, so that the number of digital filters can be halved compared to the conventional method. .

Further, since the number of data in the coefficient table is divided into n (sample rate / data transfer rate) series and switched and used, the operation amount can be reduced to 1 / n. Therefore, the operation amount is 1 / (2n) as a whole. ) Can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a 16-QAM modulator of 4 multi-subcarriers in an embodiment of the present invention. Figure 1
, 1 is a transmission data input terminal and is connected to 2. Reference numeral 2 is a Gray encoder which generates I and Q weighted impulses from the transmission data, and is connected to 1 and 3. 3 is a serial / parallel converter,
4 is connected. 4 is a symbol converter, 5 to
Connected to 20.

Reference numeral 5 denotes a 10-stage first shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 6 denotes a 10-stage second shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 7 denotes a 10-stage third shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 8 denotes a 10-stage fourth shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 9 denotes a 10-stage fifth shift register for storing the symbol conversion output.
21 is connected. Reference numeral 10 denotes a 10-stage sixth shift register for storing the symbol conversion output, which is connected to 4, 21. 11 stores the symbol conversion output 1
It is a seventh shift register with 0 stages and is connected to 4, 21. Reference numeral 12 is a ten-stage eighth shift register that stores the symbol conversion output, and is connected to 4, 21. Reference numeral 13 denotes a tenth-stage ninth shift register for storing the symbol conversion output, which is connected to 4, 21. 1
Reference numeral 4 is a ten-stage tenth shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 15 is an eleventh shift register of 10 stages for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 16 is a twelfth shift register of 10 stages for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 17 is a thirteenth shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 18 denotes a tenth-stage fourteenth shift register for storing the symbol conversion output, which is connected to 4, 21. Reference numeral 19 is a ten-stage fifteenth shift register for storing the symbol conversion output,
It is connected to 4,21. Reference numeral 20 is a 16-stage shift register having 10 stages for storing the symbol conversion output.
21 is connected.

Reference numeral 21 is a first switch for selecting the output of the first, second, third and fourth shift registers at a sampling interval (36 kHz) and is connected to 5, 6, 7, 8, 25. Reference numeral 22 is a second switch for selecting the fifth, sixth, seventh and eighth shift register outputs at a sampling interval (36 kHz), which is connected to 9,10,11,12,26. Reference numeral 23 is a third switch for selecting the 9th, 10th, 11th, and 12th shift register outputs at a sampling interval (36 kHz).
6 and 27. 24 is the sampling interval (36 kHz) of the 13th to 16th shift register outputs
It is a fourth switch selected by and is connected to 17 to 20, 28.

Reference numeral 25 is a first band limiting 88th-order FIR low-pass filter, which is connected to 21 and 31.
Reference numeral 26 is a second band limiting 88th-order FIR low pass filter, which is connected to 22 and 32. 27 is a third band limiting 88th order FIR low pass filter,
It is connected to 3, 33. 28 is for the fourth band limitation 8
It is an 8th order FIR low pass filter and is connected to 24 and 34.

29 is a first for performing subcarrier modulation.
Table and is connected to 31, 33. Thirty
Is a second table for subcarrier modulation and is connected to 32 and 34. Reference numeral 31 is a first multiplier for multiplying the output of the first filter by the first table value, which is connected to 25, 29 and 35. A second multiplier 32 multiplies the second filter output by the second table value and is connected to 26, 30, 35. 33 is the output of the third filter and the first table.
The third multiplier for multiplying the bull value is 27, 29, 37.
It is connected to the. 34 is a fourth multiplier for multiplying the output of the fourth filter by the second table value, and
It is connected to 8, 30, and 36. 35 is the above first and second
Is a first adder for adding the multiplier outputs of
2, 37 are connected. 36 is a second adder for adding the outputs of the third and fourth multipliers, and 33, 34, 3
8 is connected.

Where 45 is a multiplier of 31, 32 and 3
It is a digital quadrature modulation means for quadrature modulating the signals of the FIR filters 25 and 26 by using the adder 5 and the tables 29 and 30. Similarly, 46 is a digital quadrature modulation means for quadrature modulating the signals of the FIR filters 27 and 28.

Reference numeral 37 is a first DA converter,
It is connected to 0. 38 is a second DA converter,
It is connected to 36 and 41. A synthesizer 39 is connected to the synthesizers 40 and 41. 40 is the first D above
A first analog multiplier for multiplying the output of the A converter by the in-phase carrier of the synthesizer, 37, 39, 4
Connected to 2. 41 is a second for multiplying the output of the first DA converter by the in-phase carrier of the synthesizer.
, And is connected to 38, 39 and 42. An analog adder 42 adds the outputs of the first and second multipliers and is connected to 40, 41 and 43. 43 is a transmission output terminal, which is connected to 42.

Reference numeral 47 is an analog quadrature modulation means for quadrature modulating the analog signals of the D / A converters 37 and 38 with the carrier signal of 39 by the multipliers of 40 and 41 and the adder of 42.

FIG. 2 is a block diagram of the subcarrier modulator and filter processor in this embodiment. In FIG. 2, 50 is the first (or fifth, ninth, or fifth) in FIG.
The thirteenth) shift register input terminal is connected to 54. 51 is the second (or sixth, or sixth) in FIG.
The tenth and fourteenth) shift register input terminals,
It is connected to the. Reference numeral 52 is a third (or seventh, eleventh, fifteenth) shift register input terminal in FIG. 1 and is connected to 55. Reference numeral 53 is a fourth (or eighth, twelfth, sixteenth) shift register input terminal in FIG. 1 and is connected to 56.

Reference numeral 54 is the first (or fifth, ninth and thirteenth) shift register in FIG.
It is connected to 0. 55 is the second (or sixth, tenth, fourteenth) shift register in FIG. 1,
51 and 60 are connected. Reference numeral 56 denotes the third (or seventh, eleventh, fifteenth) shift register in FIG. 1, which is connected to 52 and 60. 57 is shown in FIG.
Is the fourth (or eighth, twelfth, sixteenth) shift register in, and is connected to 53.

Reference numeral 58 is a counter having a cycle of 9 and operating at 36 kHz, which is connected to 59. Reference numeral 59 is a decoder for the counter output, which is connected to 60 and 62. Reference numeral 60 is a switch for selecting the shift register of 54, 55, 56, 57, and 54, 55, 56,
It is connected to 57,59,63. Reference numeral 61 is a memory that stores 88 filter coefficients divided into 9 series, and is connected to 62. Reference numeral 62 denotes a switch for selecting the filter coefficient series, which is connected to 59, 61 and 63. Reference numeral 63 is an arithmetic unit for performing a sum-of-products operation of the shift register selected by the switch of 60 and the filter coefficient selected by the switch of 62.
Connected to 64. 64 is a filter output end,
It is connected to 63.

FIG. 3 is an explanatory diagram of the operation of subcarrier modulation and filter processing, and FIG. 4 is an explanatory diagram of processing of switching and executing by dividing the filter coefficient into n (= sampling frequency / symbol speed) series. Is.

Next, the multi-subcarrier 16 according to the present invention
The operation of the embodiment of the QAM modulator will be described.

First, 64 kb from the transmission data input terminal of 1.
/ S transmission data is input, the gray encoder of 2 is 4b
Three-valued weighted impulses are generated in I and Q at 4 kHz intervals for each it. 3 serial / parallel converter is 2 above
The impulses generated in 4 are sequentially separated into 4 subcarriers,
(I1, Q1), (I2, Q2), (I3, Q3), (I4,
Q4) and the symbol converter of 4 is I1 ', I1' + Q1 ',
Q1 ', I1'-Q1', I2 ', I2' + Q2 ', Q2', I2'-Q
2 ', I3', I3 '+ Q3', Q3 ', I3'-Q3', I4 ', I4'
+ Q4 ', Q4', I4'-Q4 'are generated. Where I1 ',
Q1 ', I2', Q2 ', I3', Q3 ', I4', Q4 'are (Equation 2)
Calculated at.

[0024]

## EQU2 ## I1 '= I1 + I2 + I3 + I4 Q1' =-Q1-Q2 + Q3 + Q4 I2 '=-Q1 + Q2-Q3 + Q4 Q2' =-I1 + I2 + I3-I4 Q3 '= I1 + I2 + 3 + 4 + 3 + 4 + 3 + Q4 + 4 + 2 + 4 + 4 + 4 + 4. '= -Q1 + Q2 + Q3-Q4 When the symbol conversion output is input to the first to twelfth shift registers once at 4 kHz intervals, the filter 25
While switching the switch 21 cyclically at 36 kHz, on the other hand, the filter coefficient of 9 series is internally changed to 36 kHz.
Then, the sum-of-products calculation is executed by switching with, and the output of 9 samples is calculated at 36 kHz, so that the orthogonal modulation by Δω and the filter calculation are executed at the same time.

FIG. 3 shows quadrature modulation with Δω = 2.25 kHz at 36 k
In order to consider the case of sampling at Hz, a 2.25 kHz cosine wave and a sine wave are expressed at 36 kHz, and when quadrature modulation is performed with these, the output is I, (I + Q) / √2,
It can be seen that Q, (I−Q) / √2, ... Therefore, if four types of filter input shift registers are prepared and used by switching at 36 kHz, it is possible to execute the filter operation of the I and Q2 channels with one filter. Further, when the input of the filter is 4 kHz even when the filter output of the 88th order is calculated at 36 kHz sampling, it can be seen that the number of product sums per sample output is 10 instead of 88 as shown in FIG. . Therefore, the filter coefficient is divided into 9 series in advance and 3
The filter operation may be executed while selecting at 6 kHz. The same applies to the filters 26, 27 and 28. The multiplier 3 is applied to these filter calculation outputs.
1, 32, 33, 34 and adders 35, 36 for 2 · Δω
= 4.5 kHz quadrature modulation, and I (t) of the above (Equation 2),
Get Q (t). DA converter 3 for I (t) and Q (t)
After converting to an analog signal at 7, 38, multipliers 40, 4
1 and the adder 42 perform quadrature modulation with the carrier generated in the synthesizer 39 to obtain S (t) shown in (Equation 3), and send it from the output terminal 43.

[0026]

[Number 3] S (t) = I (t ) · cos (ω c t) + Q (t) · sin (ω c t) here, I (t) = Ii ( t) · cos (Δωt) + Qi (t) ・ sin (Δωt) Q (t) = Iq (t) ・ cos (Δωt) + Qq (t) ・ sin (Δωt) The coefficients Ii, Qi, Iq, Qq are expressed by (Equation 4). .

[0027]

[Formula 4] Ii (t) = {I ₁ (t) + I ₂ (t) + I ₃ (t) + I ₄ (t)} ・ cos (2 ・ Δωt) + {-Q ₁ (t)- Q ₂ (t) + Q ₃ (t) + Q ₄ (t)} ・ sin (2 ・ Δωt) Qi (t) = {-Q ₁ (t) + Q ₂ (t) -Q ₃ (t) + Q ₄ (t)} ・ cos (2 ・ Δωt) + {-I ₁ (t) + I ₂ (t) + I ₃ (t) -I ₄ (t)} ・ sin (2 ・ Δωt) Iq (t ) = (Q ₁ (t) + Q ₂ (t) + Q ₃ (t) + Q ₄ (t)} ・ cos (2 ・ Δωt) + {I ₁ (t) + I ₂ (t) -I ₃ (t) -I ₄ (t)} ・ sin (2 ・ Δωt) Qq (t) = {I ₁ (t) -I ₂ (t) + I ₃ (t) -I ₄ (t)} ・ cos ( 2 ・ Δωt) + {-Q ₁ (t) + Q ₂ (t) + Q ₃ (t) -Q ₄ (t)} ・ sin (2 ・ Δωt) When (Equation 3) is transformed into (Equation 1 ) Can be expressed in the same form.

As described above, according to the embodiments shown in FIGS. 1, 2, 3, and 4, the number of filters is halved by simultaneously performing the orthogonal modulation by Δω and the filter calculation, and the difference in the input / output signal speed is utilized. Since the calculation amount is reduced by executing the minimum necessary number of product-sum calculations, it is possible to reduce the power consumption and cost of the device.

[0029]

As described above, according to the present invention, the number of filters is reduced by half by simultaneously executing the subcarrier modulation and the low-pass digital filter by the conversion of the filter input and the switching thereof, and the filter coefficient is n. Since the calculation amount can be reduced to 1 / n by dividing into a series of (= sampling frequency / symbol speed) and used by switching, the total calculation amount is 1 / (2
It is possible to reduce the power consumption and cost of the device.

[Brief description of drawings]

FIG. 1 is a block diagram of a modulator according to an embodiment of the present invention.

FIG. 2 is a block diagram of a subcarrier modulator and a filter processor according to the present invention.

FIG. 3 is an operation explanatory diagram of subcarrier modulation and filter processing of the present invention.

FIG. 4 is an explanatory diagram of a process of switching and executing filter coefficients.

FIG. 5 is a block diagram of a conventional modulator.

[Explanation of symbols]

 1 Transmit Data Input Terminal 2 Gray Encoder 3 Serial / Parallel Converter 4 Symbol Converter 5-20 Shift Register 21-24 Switch 25-28 FIR Low Pass Filter 29 First Table 30 Second Table 31 to 34 Multiplier 35, 36 Adder 37, 38 DA converter 39 Synthesizer 40, 41 Analog multiplier 42 Analog adder 43 Transmission output end 45, 46 Digital quadrature modulator 47 Analog quadrature modulator 50- 53 shift register input terminal 54 to 57 shift register 58 counter 59 decoder 60 switch 61 memory 62 switch 63 product-sum calculator 64 filter output terminal 101 transmission data input terminal 102 gray encoder 103 serial / parallel converter 104 ~ 111 FIR low-pass filter 11 ～119 DA converter 120 synthesizer 121-128 analog multiplier 129 analog adder 130 transmits the output end

Claims (3)

[Claims] 1. An encoding circuit for encoding multi-channel transmission data to generate a weighted impulse sequence (I, Q) for an in-phase (I) channel and a quadrature (Q) channel, and the encoding circuit. A serial / parallel conversion circuit that divides the output signal (I, Q) from the circuit into signals (Ii, Qi) of each channel, and quadrature modulation of both Ii and Qi channels from the signals (Ii, Qi) of each channel. Symbol conversion means for converting into a signal sequence suitable for, and storage means for storing the symbol-converted signal sequence for each channel,
The signal series and the filter coefficient data stored in the storage means are sequentially selected to obtain the modulation angular frequency Δω for each channel.
, A plurality of digital filters that simultaneously perform quadrature modulation and low-pass filtering, and a plurality of quadrature modulations that perform a product-sum operation on the data of the sine function table or cosine function table for each output of the corresponding set of the digital filters. A modulator comprising quadrature modulating means, D / A converting means for converting the output of the quadrature modulating means into an analog signal, and means for quadrature modulating the D / A converted signal with a carrier signal. 2. The digital filter sequentially selects the signal series stored in the storage means and the data of the filter coefficient, and performs subcarrier modulation by Δω of both Ii and Qi channels and a low pass filter. Modulator according to claim 1, characterized in that it performs a function. 3. The modulation device according to claim 1, wherein the filter coefficient is divided into a series having a ratio equal to a ratio of a sampling frequency and a symbol transmission rate.