JPH06291329A - Preparation of virtual earthing type non-volatile semiconductor device - Google Patents

Abstract

PURPOSE:To have the structure where the part of a floating gate is projected from a field insulating film to improve a coupling ratio while improving write speed and read speed by forming a stripe-shaped insulating film having a two- layer structure of the members having different etching rates. CONSTITUTION:A lamination film, where an insulating lower film containing a second conductive type impurity and an upper layer film having a different etching ratio from this lower layer film are laminated-formed, is formed on the first conductive type surface of a semiconductor substrate 101. The first conductor films 105 are buried-formed on the semiconductor substrate 101 in the gaps of these stripe-shaped laminated films through the first gate insulating film 104. Next, the second conductive type impurity is diffused in a solid phase, the upper layer film of the laminated film is etched off for projecting the first conductor film 105. Then, a second conductor film 108 is formed on the upper face and the sides through a second gate insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a virtual ground type non-volatile semiconductor device which can easily secure a coupling ratio, realize a large capacity by miniaturization and a high speed.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices have the advantage that data cannot be erased even when the power is turned off, and therefore the demand for them has increased significantly in recent years. A flash memory, which is a non-volatile semiconductor memory device that can be electrically collectively erased, can configure a memory cell with one transistor, unlike a two-transistor byte type non-volatile semiconductor memory device. Among these, an example of a contactless virtual ground type memory that significantly reduces bit line contacts is 5 of IEDM87.
Details are provided on pages 48 to 554. As a result, it becomes possible to effectively reduce the size of the memory cell, and it is expected to be used as a substitute for a large-capacity magnetic disk.

By the way, in order to improve the write / erase characteristics of the stacked gate type non-volatile memory cell, the capacitance between the floating gate and the control gate should be made larger than the capacitance between the floating gate and the substrate. is necessary. In order to increase this capacitance ratio (hereinafter abbreviated as a coupling ratio), a normal NOR flash memory (not a virtual ground type) has a floating gate extending over a field oxide film. This example is described, for example, in JP-A-57-6959.
2 in detail. However, in the above-mentioned contactless virtual ground type memory, it is difficult to extend the floating gate on the field oxide film because the field oxide film is buried after the floating gate is formed. The above-mentioned IEDM 87, pages 548 to 551, deal with it by making the insulating film quality different, but it is not possible to secure a sufficient coupling ratio.

In order to increase the coupling ratio, the normal NOR flash memory uses the sidewall of the floating gate as a part of the electrode. An example in which this is further advanced is described in Japanese Patent Laid-Open No. 215481/1992. But,
For the virtual ground type memory, there is no manufacturing method for realizing the structure, that is, a method for forming a field insulating film on the diffusion layer wiring and making the thickness thereof thinner than the film thickness of the floating gate. Therefore, the sidewall of the floating gate cannot be used as a part of the electrode.
Therefore, the region that can be used as a capacitance between the floating gate and the control gate is limited to the channel.

[0005]

As described above, in the conventional contactless virtual ground type memory, the sidewall of the floating gate cannot be used as a part of the electrode, so that a sufficient coupling ratio is obtained. I could not secure. Therefore, the writing speed, the erasing speed, and the reading speed are reduced.

The present invention eliminates the above-mentioned drawbacks, and is a method of manufacturing a virtual ground type non-volatile semiconductor memory device which is a contactless type, secures a sufficient coupling ratio, and has improved write speed, erase speed and read speed. The purpose is to provide.

[0007]

In order to achieve the above object, according to the present invention, an insulating lower layer film containing an impurity of the second conductivity type on the surface of the first conductivity type of a semiconductor substrate and the lower layer. A step of forming a laminated film in which a film and an upper film having a different etching ratio are laminated, and a first conductor via a first gate insulating film on a semiconductor substrate in a gap between the stripe laminated films. A step of embedding a film, a step of solid-phase diffusing a second conductivity type impurity from a lower layer film to a semiconductor substrate, a step of etching away an upper layer film of a laminated film to protrude a first conductor film, And a step of forming a second conductor film on a top surface and a side surface of a polysilicon film via a second gate insulating film, to provide a method for manufacturing a virtual ground type nonvolatile semiconductor memory device.

Further, a lower layer film containing an impurity of the second conductivity type and having an insulating property, an etching stopper film on the lower layer film, and an upper layer film thereon are laminated on the surface of the first conductivity type of the semiconductor substrate. Forming the laminated laminated film in a stripe shape, and forming a first gap on the semiconductor substrate in the gap between the laminated laminated films.
Of the first conductor film via the gate insulating film, the step of solid-phase diffusing second conductivity type impurities from the lower layer film to the semiconductor substrate, and the etching stopper film for the upper layer film of the laminated film. Is used as an etching stopper to remove the first conductor film by etching, and a step of forming a second conductor film on the upper surface and the side surface of the polysilicon film via the second gate insulating film. A method of manufacturing a virtual ground type nonvolatile semiconductor memory device is provided.

[0009]

When the means provided by the present invention is used, a stripe-shaped insulating film having a two-layer structure sandwiching a member having a different etching rate between the lower layer film and the upper layer film or an etching stopper layer is formed on the semiconductor substrate. Only one (upper layer film) of the two-layer structure can be etched and dug down so that it becomes thinner than the first conductive film thickness of the gate. Therefore, the floating gate has a structure protruding more than the field insulating film. Further, a second conductive film which is a control gate is formed through the second gate insulating film. As a result, the side wall of the first conductive film can also be used as an electrode for capacitive coupling, and the coupling ratio is improved. As a result, it is possible to use the sidewall of the floating gate as an electrode for capacitive coupling with the control gate, even though it is a contactless virtual ground memory, and the coupling ratio is higher than that of the conventional virtual ground memory cell. improves. This leads to an improvement in writing speed, reading speed and erasing speed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. 1 to 6. As shown in [Fig. 1],
A 200 nm-thick AsSG film (arsenic-doped oxide film) 102 is formed on the surface of the P-type silicon substrate 101 by the LPCVD method. Further, an LPD film (silicon oxide film formed by liquid layer growth) 103 having a film thickness of 200 nm is laminated and formed by the LPCVD method.

Then, as shown in FIG. 2, AsSG
The film 102 and the LPD film 103 are etched and removed in stripes using a resist (not shown) as a mask to expose the P-type silicon substrate 101. Then, the exposed P-type silicon substrate 101 is thermally oxidized to form a first gate insulating film 104 having a film thickness of 20 nm.

Subsequently, as shown in FIG. 3, a polysilicon film is formed on the entire surface and then etched back to form a first polysilicon film in a gap between stripes of the AsSG film 102 and the LPD film 103. The film 105 is embedded. Subsequently, the polysilicon film 105 is N-type doped with an impurity dopant gas such as POCl ₃ and, at the same time, the AsSG film 102 is removed from the P-type silicon substrate 101.
Stripe-shaped N-type diffusion layer 106 is formed by solid-phase diffusing arsenic.

Then, as shown in FIG. 4, AsSG
The LPD film 103 on the film 102 is removed by etching. At this time, in the AsSG film 102, arsenic impurities have moved to the P-type silicon substrate 101, so that the AsS film having a small impurity content is used.
Change to G film. Therefore, the AsSG film 102 and AsSG
The LPD film formed on the film 102 can secure an etching selection ratio, and as is well known, only the LPD film 103 having a high etching rate can be removed by a mixed gas of CF ₄ and H ₂ . In this case, the selection ratio is about 1: 3, and the BPSG film 103 has a higher etching rate than the AsSG film 102.

Subsequently, as shown in FIG. 5, the second gate insulating film 107 is formed on at least the first polysilicon film 1.
Form on 05. This second gate oxide film 107 is O
A three-layer structure of NO, a 12 nm-thick oxide film formed by thermal oxidation of the first polysilicon film 105, LPCVD
It has a three-layer structure including a nitride film having a film thickness of 20 nm formed by a thermal oxidation method and an oxide film having a film thickness of 6 nm formed by a thermal oxidation method.
Subsequently, a second polysilicon film 108 having a film thickness of 500 nm is formed on the entire surface by the CVD method.

Subsequently, as shown in FIG. 6, the second polysilicon film 108 is formed into a stripe-shaped N-type diffusion layer 106.
A stripe-shaped resist (not shown) is formed in a direction perpendicular to the direction of, and the second polysilicon film 1 is formed using this as a mask.
08, the second gate insulating film 107, and the first polysilicon film are removed by etching.

The memory cell of the virtual ground type memory is formed by the manufacturing method described above. That is, the striped AsSG film serves as a field insulating film, the first polysilicon film 105 is electrically floated to serve as a floating gate, and the striped N-type diffusion layer 106 serves as a virtual ground line or a virtual bit line. The stripe-shaped second polysilicon film perpendicular to the virtual ground line or virtual bit line functions as a word line. See IEDM 87, pages 548 to 551, for details of the write operation.

According to the present invention, it is possible to use the side wall of the floating gate as an electrode for capacitive coupling with the control gate, even though it is a contactless virtual ground type, and the conventional contactless virtual ground type memory. The coupling ratio is improved compared to the cell. This is the writing speed,
This leads to improvement in read speed and erase speed.

As described above, in the present invention, the AsSG film and L
Since the stripe-shaped insulating film having a two-layer structure made of a member having a different etching rate from that of the PD film is formed on the semiconductor substrate, the two-layer structure of the two-layer structure is made thinner than the first polysilicon film which is the floating gate. Only one of them (LPD film) can be etched and dug down. This is As
This is because the LPD film on the AsSG film was removed by etching after the impurity concentration of the SG film was lowered to ensure the selection ratio. Therefore, the floating gate has a structure protruding more than the field insulating film. Further, a second polysilicon film which is a control gate is formed via a thin insulating film. As a result, the side wall of the first polysilicon film can also be used as an electrode for capacitive coupling, and the coupling ratio is improved. Since the insulating film on the stripe is doped with N-type impurities, the N-type impurities are solid-phase diffused into the substrate by the subsequent thermal diffusion, and as a result, virtual ground lines and virtual bit lines on the stripes are formed. .

Next, a second embodiment of the present invention [FIG. 7].
Through [FIG. 12]. As shown in FIG. 7, a 200 nm-thick AsSG film (arsenic-doped oxide film) 202 is formed on the surface of the P-type silicon substrate 201 by the LPCVD method. Further, after forming a nitride film 220 with a film thickness of 20 nm by the LPCVD method, LP
A 200-nm-thick BPSG film (an oxide film doped with boron and phosphorus) 203 is laminated by a CVD method.

Subsequently, as shown in FIG. 8, AsSG
The film 202 and the BPSG film 203 are stripped by etching using a resist (not shown) as a mask to expose the P-type silicon substrate 201. Then, the exposed P-type silicon substrate 201 is thermally oxidized to form a first gate insulating film 204 having a film thickness of 20 nm.

Then, as shown in FIG. 9, a polysilicon film is formed on the entire surface and is subsequently etched back to form the first polysilicon in the gap between the stripes of the AsSG film 202 and the BPSG film 203. The film 205 is embedded. Then, the polysilicon film 205 is N-type doped with an impurity dopant gas such as POCl ₃ and, at the same time, the AsSG film 202 is removed from the P-type silicon substrate 20.
Stripe-shaped N by arsenic solid-phase diffusion into 1
The mold diffusion layer 206 is formed.

Then, as shown in FIG. 10, AsS
The BPSG film 203 on the G film 202 is removed by etching. At this time, the nitride film 220 is used as an etching stopper. Therefore, wet etching with NH ₄ F has become possible.

Subsequently, as shown in FIG. 11, a second gate insulating film 207 is formed on at least the first polysilicon film 205. This second gate oxide film 207 has a three-layer structure of ONO, and the first polysilicon film 205
12 nm thick oxide film formed by thermal oxidation of LPCV
It has a three-layer structure of a 20 nm-thick nitride film formed by the D method and a 6 nm-thick oxide film by the thermal oxidation method. Then, a second polysilicon film 208 having a film thickness of 500 nm is formed on the entire surface by the CVD method.

Subsequently, as shown in FIG. 12, the second polysilicon film 208 is formed into a stripe-shaped N-type diffusion layer 20.
A stripe-shaped resist (not shown) is formed in a direction orthogonal to the direction of 6, and the second polysilicon film 208, the second gate insulating film 207, and the first polysilicon film are removed by etching using this as a mask.

By the manufacturing method described above, the memory cell of the virtual ground type memory is formed as in the first embodiment.
In the second embodiment, the insulating film is not dug deeper than the film thickness of the floating gate by utilizing the difference in etching rate between the AsSG film and the LPD film, but the nitride film between both insulating films is used as an etching stopper. Used as. Therefore, only one (BPSG film) of the two-layer structure can be easily etched and dug down so as to be thinner than the first polysilicon film thickness of the floating gate. Therefore, the floating gate has a structure protruding more than the field insulating film. Further, a second polysilicon film which is a control gate is formed via a thin insulating film. As a result, the side wall of the first polysilicon film can also be used as an electrode for capacitive coupling, and the coupling ratio is improved.

Although the first and second embodiments have been described above, various modifications can be made without departing from the spirit of the present invention. For example, in the first embodiment, the LPD film is used as the insulating film of the second layer, but it is possible to obtain an etching ratio with the insulating film of the first layer and the etching ratio of the floating gate member and that of the floating gate member. As long as it is possible, a BPSG film, a PSG film, or the like may be used. Even in this case, a selection ratio of about 1: 2 can be secured. In addition to these, a material such as a nitride film can be used. Also, the second
In the above embodiment, the nitride film was used as the etching stopper, but it may be thin polysilicon. However,
Since it needs to be an insulating film because it contacts the floating gate,
Use polysilicon that is not doped with impurities, or
Alternatively, it may be completely oxidized. Further, in the second embodiment, it is not necessary to make the etching rates different between the lower layer film and the upper layer film. This is because the etching stopper layer exists between the lower layer film and the upper layer film. Therefore, the same member, for example, an AsSG film, may be used for both the upper layer film and the lower layer film. Further, in both of the examples, the second gate insulating film is turned on.
Although the O film is used, only a thermal oxide film of silicon may be used.

[0027]

According to the present invention, it is possible to provide a method for manufacturing a virtual ground type non-volatile semiconductor memory device which secures a sufficient coupling ratio and increases the write speed, erase speed and read speed.

[Brief description of drawings]

FIG. 1 is a perspective view showing a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a perspective view showing a manufacturing process of the first embodiment of the present invention.

FIG. 3 is a perspective view showing a manufacturing process of the first embodiment of the present invention.

FIG. 4 is a perspective view showing a manufacturing process of the first embodiment of the present invention.

FIG. 5 is a perspective view showing the manufacturing process of the first embodiment of the present invention.

FIG. 6 is a perspective view showing a manufacturing process of the first embodiment of the present invention.

FIG. 7 is a perspective view showing the manufacturing process of the second embodiment of the present invention.

FIG. 8 is a perspective view showing the manufacturing process of the second embodiment of the present invention.

FIG. 9 is a perspective view showing the manufacturing process of the second embodiment of the present invention.

FIG. 10 is a perspective view showing a manufacturing process of the second embodiment of the present invention.

FIG. 11 is a perspective view showing the manufacturing process of the second embodiment of the present invention.

FIG. 12 is a perspective view showing the manufacturing process of the second embodiment of the present invention.

[Explanation of symbols]

101 P-type silicon substrate 102 AsSG film (field insulating film) 104 First gate insulating film 105 First polysilicon film (floating gate) 106 N-type diffusion layer (virtual ground line or virtual bit line) 107 Second gate Oxide film 108 Second polysilicon film (control gate)

Claims (2)

[Claims] 1. A second conductivity type is formed on the surface of the first conductivity type of the semiconductor substrate.
A step of forming a laminated film in which an insulating lower layer film containing a conductivity type impurity and an upper layer film having a different etching ratio from this lower layer film are formed in a stripe shape; and the semiconductor in the gap between the stripe-shaped laminated film A step of burying and forming a first conductor film on a substrate via a first gate insulating film; a step of solid-phase diffusing second conductivity type impurities from the lower layer film on the semiconductor substrate; A step of etching away an upper layer film of the film to project the first conductor film, and a step of forming a second conductor film on the upper surface and the side surface of the polysilicon film through a second gate insulating film. A method of manufacturing a virtual ground type nonvolatile semiconductor memory device, comprising: 2. A step of forming a laminated film in which an insulating lower layer film is laminated on the surface of the first conductivity type of a semiconductor substrate and an upper layer film is laminated on the lower layer film via an etching stopper film in a stripe shape. A step of embedding a first conductor film on the semiconductor substrate with a first gate insulating film interposed between the stripe-shaped laminated films, and a second conductivity type from the lower layer film on the semiconductor substrate. Solid-phase diffusing the impurities of the above step, a step of etching away the upper layer film of the laminated film by using the etching stopper film as an etching stopper to project the first conductor film, and an upper surface and a side surface of the polysilicon film. And a step of forming a second conductor film via a second gate insulating film, the method of manufacturing a virtual ground type nonvolatile semiconductor memory device.