JPH06291052A - Compound semiconductor substrate, semiconductor device using it, and manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To provide a semi-insulation compound semiconductor epitaxial layer exhibiting a high resistivity by growing an undoped compound semiconductor epitaxial layer on the surface of a single-element semiconductor substrate and then performing heat treatment of the substrate for semi-insulating the epitaxial layer. CONSTITUTION:A substrate which is subjected to epitaxial growth is taken out, is loaded into a crystal ampoule along wit arsenic, and then is vacuum- sealed. In this case, the amount of arsenic is determined so that a vapor pressure preventing arsenic from volatilizing from the substrate surface at a heat treatment temperature can be obtained. Then, after the crystal ampoule is loaded into a heating furnace and then is subjected to heat treatment for three hours at 950 deg.C, it is cooled. After heat treatment, the surface of the wafer is eliminated by approximately 10mum by lapping and then resistivity is measured by the Van der Pauw method to confirm that GaAs epitaxial layer with a resistivity of 1X19<7>OMEGA.cm or higher is formed. Hence, the epitaxial layer can be semiinsulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor substrate used for semiconductor devices, and more particularly to a substrate having a high resistivity GaAs epitaxial layer formed on the surface of a single element semiconductor substrate such as a silicon substrate and the like. The present invention relates to a technique suitable for use in manufacturing a semiconductor device using the semiconductor device and a semiconductor substrate thereof.

[0002]

2. Description of the Related Art A single element semiconductor substrate is superior to a compound semiconductor substrate in terms of cost, strength and degree of integration when manufacturing a semiconductor device. However, it is difficult to realize the high frequency characteristics and optical characteristics peculiar to compound semiconductor devices with a device using a single element semiconductor substrate. Therefore, conventionally, research and development of a heterostructure substrate in which a compound semiconductor is epitaxially grown on a single element semiconductor substrate have been carried out, and a monolithic device such as an OEIC in which an electronic element and an optical element are integrated has also been devised. Conventionally, for a heterostructure substrate in which a compound semiconductor is epitaxially grown on a single element semiconductor substrate, a MOCVD method or MB method is used on a silicon single crystal substrate.
Vigorous attempts have been made to grow a GaAs layer by the E method.

However, since silicon and GaAs have a relatively large difference in lattice constant, there is a problem that crystal defects such as dislocations are generated at a high density in the above structure due to lattice mismatch and difference in thermal expansion coefficient. There are many studies aimed at reducing the dislocation density. Among them, during the thermal cycle, that is, from the start to the end of epitaxial growth, the substrate temperature is increased from the growth temperature to a higher temperature in multiple steps in a stepwise manner to move dislocations and release them to the surface, thereby increasing the dislocation density. It is well known that the reduction method is relatively easy and effective, and it is reported that a substrate having a GaAs layer with a dislocation density of 2.5 × 10 ⁶ cm ² was obtained. On the other hand, as other methods for reducing the dislocation density due to the lattice mismatch, a method of adding impurities such as indium into the epitaxial crystal and a method of inserting a strained superlattice layer have been proposed.

[0004]

According to the above-mentioned various methods, a substrate having a compound semiconductor epitaxial layer having a relatively low dislocation density can be obtained, and therefore it is expected to be applied to an optical device substrate. However, when applied to an electronic device integrated into a circuit, each element must be separated by an insulator or a semi-insulator in order to prevent a leak current. Therefore, in a conventional electronic device using a silicon substrate, the substrate is selectively oxidized to form SiO ₂ for element isolation. On the other hand, in the compound semiconductor device, the electronic device substrate is required to have a higher resistance and a lower carrier concentration than the optical device substrate. Specifically, when a heterostructure substrate in which a compound semiconductor is epitaxially grown on a single element semiconductor substrate is used as a substrate for an electronic device, the resistivity is 1 × 10 ⁷ Ω · cm or more and the carrier concentration is 1 ×. It is essential that an epitaxial layer of 10 ⁹ cm ^-3 or less is under the operating layer.

However, in the substrate in which the compound semiconductor is epitaxially grown on the single element semiconductor substrate by the above-mentioned conventional method, the lower limit of the carrier concentration is 2 × 10 ¹⁵ cm ⁻³ , which is higher than 1 Ω · cm. Since resistivity could not be obtained, application to electronic devices or OEICs could not be expected. Therefore, it has been attempted to make the compound semiconductor semi-insulating after being epitaxially grown. Conventional semi-insulation of compound semiconductor epitaxial layers is generally
A method of flowing a doping gas containing a semi-insulating impurity from a bypass pipe during vapor phase growth, or adding a semi-insulating impurity to a source material for vapor phase growth in advance and doping the epitaxial layer on the substrate surface during growth. Etc.

However, in the former method, the compound of the semi-insulating impurity introduced from the bypass pipe is decomposed and deposited in the bypass pipe, or the semi-insulating impurity reacts with HCl in the bypass pipe to generate chloride. Since it is transported in a form, there is a defect that the HCl concentration becomes high and the substrate is etched when the doping amount is increased. On the other hand, in the latter method, if the segregation coefficient of the semi-insulating impurity source with respect to the source material is small, the required amount of semi-insulating impurities cannot be transported, so that sufficient semi-insulating cannot be achieved. The present invention has been made by focusing on the above problems,
The object of the invention is to provide a substrate having a semi-insulating compound semiconductor epitaxial layer on the surface of a single element semiconductor substrate, which exhibits a much higher resistivity than before, a semiconductor device using the same, and a method for manufacturing the semiconductor substrate. To provide.

[0007]

As a result of earnest studies on the semi-insulating property of the epitaxial layer, the present inventor has found that the cause of the compound semiconductor epitaxial layer not exhibiting sufficient semi-insulating property is the semi-insulating property. This is because the deep level necessary for the compound semiconductor epitaxial layer is not sufficiently formed. After the compound semiconductor is epitaxially grown on the single-element semiconductor substrate, heat treatment is performed to increase the defect concentration at the deep level to increase the compound semiconductor epitaxial layer. It has been found that can be semi-insulating.

The present invention has been made based on the above findings. After growing an undoped compound semiconductor epitaxial layer on the surface of a single element semiconductor substrate, the substrate is heat-treated to make the epitaxial layer semi-insulating. It is a proposal to do. It is desirable that the heat treatment of the substrate is performed in a state where the vapor pressure of the constituent elements of the compound semiconductor forming the epitaxial layer is applied. However, in the heat treatment performed after forming the protective film such as silicon nitride on the surface of the epitaxial layer, it is not necessary to apply the vapor pressure of the constituent elements.

[0009]

According to the above-described means, since a defect having a deep level is formed in the undoped compound semiconductor epitaxial layer by the heat treatment, impurities forming a shallow level in the epitaxial layer are not affected by the defect of the deep level. It is compensated and the epitaxial layer is semi-insulating.

[0010]

【Example】

(Example 1) Using a low pressure MOCVD apparatus, GaAs layers 2a, 2 are formed on a silicon single crystal substrate 1 as shown in FIG.
After b and 3 were epitaxially grown in three stages, heat treatment was performed. In this example, 2 ° from the (100) plane.
A tilted off-angle silicon substrate was prepared and placed in a low pressure MOCVD apparatus.
Hold for minutes. Next, the substrate temperature was lowered to 450 ° C. and the first GaAs layer 2a was epitaxially grown on the surface of the substrate 1 as a buffer layer for relaxing lattice mismatch to a thickness of 50 Å. Then, the substrate temperature was raised to 750 ° C., and the second GaAs layer 2b was epitaxially grown to a thickness of 3 μm while performing instantaneous heat treatment at 900 ° C. for 1 minute five times.

After that, the substrate was taken out from the MOCVD apparatus, placed in a chloride growth apparatus together with a gallium boat, heated to 750 ° C. in a hydrogen atmosphere, and then H ₂
Arsenic trichloride (AsCl ₃ ) was supplied using the gas as a carrier gas to epitaxially grow the third GaAs layer 3 to a thickness of 30 μm. Next, the substrate on which the above epitaxial growth was performed was taken out, put into a quartz ampoule together with arsenic, and vacuum-sealed. At this time, the amount of arsenic was determined so as to obtain a vapor pressure at which arsenic does not volatilize from the substrate surface at the heat treatment temperature. Next, this quartz ampoule was placed in a heating furnace, heat-treated at 950 ° C. for 3 hours, and then cooled.

After the heat treatment, the wafer surface is removed by about 10 μm by lapping, and then van der Pau (Van) is used.
The resistivity was measured by the der Pauw method. As a result, it was confirmed that a GaAs epitaxial layer having a resistivity of 1 × 10 ⁷ Ω · cm or more was formed. further,
A field effect transistor was prepared by forming a channel layer in the GaAs epitaxial layer of the substrate after the heat treatment by an ion implantation method, and its characteristics were evaluated.
It was confirmed that it has characteristics that are almost the same as those of the field effect transistor formed on the aAs substrate.

(Embodiment 2) A GaAs layer is grown on a silicon single crystal substrate at a low temperature using an MBE apparatus and heat-treated, and then a strained superlattice layer is formed. Then, the GaAs layer is epitaxially grown in two steps and heat-treated. gave. As in Example 1, an off-angle silicon substrate tilted by 2 ° from the (100) plane was prepared and placed in the MBE apparatus.
Perform thermal cleaning at 00 ° C for 10 minutes to clean the surface, then lower the substrate temperature to 300 ° C and Ga
The As layer was grown to a thickness of 100 nm. Then, the substrate temperature was raised to 600 ° C. and held for 10 minutes, and then the substrate temperature was lowered again to 300 ° C. to grow a GaAs layer of 2 μm.

[0014] Next, strained superlattice layer [In _{0. 3} GaAs (1
0 nm) / GaAs (20 nm)] for 20 cycles, and then the GaAs layer was grown to 5 μm while maintaining the substrate temperature at 300 ° C. After that, the substrate was taken out from the MBE apparatus, placed in a chloride growth apparatus with a boat containing gallium, heated to 750 ° C. in a hydrogen atmosphere, and then H ₂ gas was used as a carrier gas for arsenic trichloride (As).
Cl ₃ ) was supplied to epitaxially grow the GaAs layer to a thickness of 30 μm. Next, the epitaxially grown substrate was taken out and vacuum-sealed in a quartz ampoule together with arsenic, and the same conditions as those in Example 1 (950) were used.
The heat treatment was performed at 3 ° C. for 3 hours.

After the heat treatment, the surface of the wafer was removed by about 10 μm by lapping, and the resistivity was measured. As a result, it was confirmed that a GaAs epitaxial layer having a resistivity of 1 × 10 ⁷ Ω · cm or more was formed. Further, a channel layer was formed on the GaAs epitaxial layer of the substrate after the heat treatment by an ion implantation method to prepare a field effect transistor, and its characteristics were evaluated.
It was confirmed that the hysteresis of current-voltage characteristics, which was observed in the field effect transistor formed on the As substrate, was suppressed. Further, when the voltage applied to one of the two adjacent FETs was changed and the drain current of the other FET was measured, there was no change in the drain current, and the side gate effect, which was a problem with conventional bulk crystals, was observed. It turned out that it was suppressed.

In the above embodiments, the compound semiconductor buffer layer for relaxing the lattice mismatch with the substrate is formed by stepwise epitaxial growth by MOCVD and strained superlattice growth by MBE. The formation of is not limited to the above method, and may be formed by using other known techniques. The buffer layer may have a composition gradient layer or other structure. Furthermore, in the above-mentioned embodiment, the case where the GaAs epitaxial layer is grown on the silicon substrate to make it semi-insulating is explained, but the present invention is not limited to this, and a III-V group or other group is formed on a single element semiconductor substrate. It can be generally applied when manufacturing a substrate having a compound semiconductor epitaxial growth layer. In that case, it is desirable to select the optimum heat treatment temperature according to the grown compound semiconductor.

[0017]

As described above, according to the present invention, the undoped compound semiconductor epitaxial layer is grown on the surface of the single element semiconductor substrate, and then the substrate is heat-treated. Since a defect having a deep level is formed in the layer, there is an effect that impurities forming a shallow level in the epitaxial layer are compensated by the defect of the deep level and the epitaxial layer is semi-insulating. . The substrate obtained by the above method has an epitaxial layer of 1 × 10 5.
^{Since it} is a semi-insulating compound semiconductor epitaxial layer having a resistivity of ⁷ Ω · cm or more, when a plurality of electronic devices such as FETs are formed here, isolation between the devices is sufficiently achieved. Moreover, by removing a part of the epitaxial layer on the surface of the substrate to expose a single element semiconductor substrate such as silicon and forming an electronic element there, an element having different semiconductors as a base is combined to form a single substrate. There is an effect that a device integrated above can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of a structure of a compound semiconductor substrate manufactured by the method of the present invention.

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[Procedure amendment]

[Submission date] July 1, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

However, since there is a relatively large difference in lattice constant between silicon and GaAs, there is a problem that the above structure has a high density of crystal defects such as dislocations due to lattice mismatch and distant thermal expansion coefficient. There are many studies aimed at reducing the dislocation density. Among them, during the thermal cycle, that is, from the start to the end of epitaxial growth, the substrate temperature is increased from the growth temperature to a higher temperature in multiple steps in a stepwise manner to move dislocations and release them to the surface, thereby increasing the dislocation density. The reduction method is often performed because it is relatively easy and effective, and thus, for example, GaAs having a dislocation density of 2.5 × 10 ⁶ cm ⁻² is used.
It is also reported that a substrate having a layer was obtained. On the other hand, as other methods for reducing the dislocation density due to the lattice mismatch, a method of adding impurities such as indium into the epitaxial crystal and a method of inserting a strained superlattice layer have been proposed.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Next, the strained superlattice layer [ In _0.3 Ga _0.7
After forming 20 cycles of As (10 nm) / GaAs (20 nm)], Ga is maintained with the substrate temperature kept at 300 ° C.
An As layer was grown to 5 μm. After that, the substrate was taken out from the MBE apparatus and placed in a chloride growth apparatus together with a boat containing gallium, heated to 750 ° C. in a hydrogen atmosphere, and then arsenic trichloride (AsCl ₃ ) was used with H ₂ gas as a carrier gas. Supply the GaAs layer to a thickness of 30μ
m was epitaxially grown. Next, the epitaxially grown substrate was taken out, vacuum-sealed in a quartz ampoule together with arsenic, and heat-treated under the same conditions as in Example 1 (950 ° C., 3 hours).

Claims (4)

[Claims] 1. A semi-insulating compound semiconductor epitaxial layer having a resistivity of 1 × 10 ⁷ Ω · cm or more on the surface of a single-element semiconductor substrate via a compound semiconductor buffer epitaxial layer that relaxes lattice mismatch with the substrate. A compound semiconductor substrate comprising: 2. A semiconductor device comprising an electronic element or an optical element formed on the surface of the compound semiconductor substrate according to claim 1. 3. A compound semiconductor, wherein an undoped compound semiconductor epitaxial layer is grown on a surface of a single element semiconductor substrate, and then the substrate is heat-treated to semi-insulate the epitaxial layer. Substrate manufacturing method. 4. A compound semiconductor buffer layer for relaxing lattice mismatch with the substrate is epitaxially grown on the surface of a single element semiconductor substrate, and an undoped compound semiconductor layer having a desired composition ratio is epitaxially grown thereon. A method for manufacturing a compound semiconductor substrate, characterized in that the substrate is heat-treated to make the epitaxial layer semi-insulating.