JPH06290082A - Inter-cpu data transmission method - Google Patents

Abstract

PURPOSE:To provide an inter-CPU data transmission method inhibiting a CPU other than the one receiving a communication request from executing fault processing in error in the case of transferring data whose transfer time from a certain memory to a common memory is longer than time-out time. CONSTITUTION:In the case of transmitting data whose transfer time from a memory 1-1 in a CPU 1 to the common memory 10 is longer than time-out time set up by a CPU 3 from the CPU 1 to a CPU 2, data length is divided so that the transfer time is less than the time-out time, the CPU 1 transfers each divided data to the common memory 10 and the CPU 2 executes data transfer processing from the memory 10 until all the data are transferred. When a communication request is outputted from the CPU 3 to the CPU 1 during the data transmission of the CPU 1, the CPU 1 outputs a queue request after completing the transfer of the divided data to the memory 10 and the CPU 3 checks whether the queue request is outputted or not in each time-out time, and when the queue request is outputted, sets up the time-out time again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CP for transferring long data between CPUs of a multiprocessor system.
The present invention relates to improvement of a U-to-U data transfer method.

A multiprocessor system having four CPUs will be described below by taking a case where a communication request is sent from the CPU3 to the CPU1 or the CPU2 while transferring long data from the CPU1 to the CPU2.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram of a main part of an example of a multiprocessor system, and FIG. 6 is an example of CPUs n and C of FIG.
FIG. 7 is a diagram showing details of an inter-CPU communication area with PUm, FIG.
FIG. 8 is a flowchart of processing of the conventional CPU 1, and FIG. 8 is a flowchart of processing of the conventional CPU 2. Figure 5
In this case, the CPUs 1 to 4 and the common memory 10 are connected by a bus, and as shown in FIG. 5, the CPU 1 receives the identification number of the CPU that transfers the data and the C to which the data has been transferred.
Inter-CPU interrupt notification register 21 that reads the PU identification number, and CP that writes the identification number of the CPU with the communication request
The U-to-U interrupt request register 22, the memory 1-1 for writing the transfer data, and the mailbox 23 for receiving the transferred data are provided.
And an inter-CPU interrupt request register 32, a memory 2-1 and a mailbox 33,
The CPUs 3 and 4 have the same configuration but are omitted.

The common memory 10 has a free memory area 11 for writing transfer data and an inter-CPU communication area 12, and the inter-CPU communication area 12 transfers data from the CPUs 1, 2, 3, 4 to another CPU. It has a communication area for communication between CPUs, and details of each communication area, for example, CPU
The details of 1 → CPU 2 are, as shown in FIG. 6, a CPU-ID area 41 in which an identification number of a CPU for data transfer is written.
The task ID area 42 for writing the task identification number, the end information area 43 for writing the waiting request in the case of transfer completion or processing, the system call type area 44 for writing the system call type, and various register values Various register value areas 45 to be written, mailboxes N0. , Message start address, message length,
It is made up of various data value areas 46 for storing, etc.

When the CPU 1 transfers the data to the CPU 2, the task A of the CPU 1 executes the steps of FIG.
In step S2, the transfer data to be transferred to the CPU2 is stored in the area acquired in S1.
The data stored in 3 is stored in the mailbox 3 of the CPU 2
Issue a data transfer system call to send to 3.

Then, the OS acquires the area for storing the transfer data in the free memory area 11 in the common memory 10 in S4, and acquires the transfer data stored in the memory 1-1 in the free memory area 11 in S5. Transfer to the designated area, S6
Then, the corresponding column of the CPU2 of the inter-CPU interrupt request register 21 is set to 1, and the type of the data transfer system call is written in the system call type area 44 of the communication area of the CPU1 → CPU2 of the common memory 10. C
CPU1 of the CPU-to-CPU interrupt notification notification register 31 of PU2
Is set to 1 and the transfer request is notified. CPU1 at this time
In the various data value areas 46, the mailbox NO. , Write the start address and message length of the message.

Then, in S7 of FIG. 8, the OS of the CPU 2 sets 1 in the column of CPU 1 in the inter-CPU interrupt notification register 31.
Therefore, the transfer request from the CPU 1 is known,
A storage area for transfer data is acquired in the memory 2-1. In S8, the transfer data copied to the free memory area 11 of the common memory 10 is transferred to the area acquired in S7, and S9
At S3, a data transfer system call is issued in order to substitute the data transfer system call issued by the CPU 1 at S3, the transfer data is transmitted to the mailbox 33, and the processing is terminated, and the termination information area 43 in FIG. 6 is displayed. Write 00.

Then, in S13, the task B issues a system call for receiving the transfer data in the mailbox 33, acquires the transfer data in the mailbox 33 in S14, and sets it in S7 in S15. The acquired area is C
It is returned to the memory 2-1 in the PU.

On the other hand, the OS of the CPU 1 checks whether or not 00 is written in the end information area 43 in S10 of FIG. 7, and if it is written, in S11, the area acquired in S4 is free memory. The area is returned to the area 11, and in step S12, the area acquired in step S1 is returned to the memory 1-1.

When the CPU 3 makes a communication request to the CPU 1 or the CPU 2, the column of the CPU 3 of the inter-CPU interrupt notification register 21 or 31 of the CPU 1 or the CPU 1 becomes 1 and C
It becomes clear from PU3 that there is a communication request. At this time, the CPU 3 sets a timeout time in the timer.

If there is no response from the CPU 1 or the CPU 2 which requested the communication within the time-out time, the CPU 3 times out and determines that a failure has occurred in the CPU to which the communication is requested, and performs a failure occurrence process.

[0012] If the time-out time is made longer to prevent the time-out, the processing speed and performance of the OS will be lowered. Therefore, normally, the time for transferring 2 Kbytes of data from the memory 1-1 to the common memory 10 , Or 10ms which is the time to transfer from the common memory 10 to the memory 2-1
It is below.

[0013]

However, when transferring data from the memory 1-1 to the common memory 10 or from the common memory 10 to the memory 2-1 takes longer than the timeout time, , It may time out. In this case, CPU1 or C
There is a problem that the CPU 3 handles the failure regardless of whether the PU 2 is a failure.

According to the present invention, the transfer time from the memory to the common memory or the transfer time from the common memory to the memory is
An object of the present invention is to provide an inter-CPU data transfer method that prevents other CPUs in a communication request from erroneously performing failure processing when transferring data that takes longer than the timeout time.

[0015]

FIG. 1 shows the principle of the present invention. As shown in FIG. 1, the first CPU 1 of the multiprocessor system transfers the data written in the memory 1-1 to the common memory 10, and the second CPU 2 transfers the data to the common memory 1.
The data transferred to 0 is transferred to the own memory 2-1 and is received in the own mail box 2-2 so that the first CPU 1
Data is transferred to the second CPU 2 by the third C
When the PU 3 makes a communication request to the first CPU 1 or the second CPU 2, a time-out time is set in a timer, and when the time-out time is reached, the CPU of the communication request destination makes a failure and performs a failure process. Is transferred from the memory 1-1 to the common memory 10 by the first CPU 1, or the second CPU 2 is transferred from the common memory 10 to the memory 2-1.
When data longer than the timeout time set by the third CPU 3 is transferred from the first CPU 1 to the second CPU 2, the data length is divided so that the transfer time is within the timeout time, For each divided data,
The first CPU 1 transfers the data to the common memory 10,
CPU 2 performs the process of transferring from the common memory 10 until all the data is transferred, and if the first CPU 1 requests the communication from the third CPU 3 while the first CPU 1 is transferring the data, The first CPU 1 makes a waiting request for each divided transfer of the divided data to the common memory 10,
If there is a communication request from the third CPU 3 to the second CPU 2 while the second CPU 2 is transferring data, the second CP
The U2 makes a waiting request for the divided data from the common memory 10 to the own memory 2-2 each time the transfer is completed.
The CPU 3 checks whether or not a waiting request is issued every time the timeout time elapses, and if so, sets the timeout time again.

[0016]

According to the present invention, the time during which the first CPU 1 transfers the data from the memory 1-1 to the common memory 10,
Alternatively, the data transferred from the common memory 10 to the memory 2-1 by the second CPU 2 is longer than the timeout time set by the third CPU 3 and the data is transferred from the first CPU 1 to the second CPU 2. In this case, the data length is divided so that the transfer time is within the time-out time, the first CPU 1 transfers the divided data to the common memory 10, and the second CPU 2 transfers the common data. Memory 10
Further transfer processing is performed until all data is transferred.

When the first CPU 1 transfers the data during the data transfer.
If there is a communication request from the third CPU 3 to the CPU 1 of
The first CPU 1 stores the divided data in the common memory 10
To the second CPU every time the transfer is completed.
2 is the third CPU while the second CPU 2 is transferring the data.
If there is a communication request from 3, the second CPU 2 requests the divided data from the common memory 10 to the own memory 2-2 every time transfer is completed.

Each time the time-out time elapses, the third CPU 3 checks whether a queuing request has been issued, and if so, sets the time-out time again. Therefore, the third CPU 3 will not erroneously handle the failure of the communication requesting CPU.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a flowchart of the processing of the CPU 1 of the embodiment of the present invention, FIG. 3 is a flowchart of the processing of the CPU 2 of the embodiment of the present invention, and FIG. 4 is a waiting request and a timeout time of the embodiment of the present invention. It is a time chart.

The following is the transfer time of data from the memory 1-1 to the free memory area 11 of the common memory 10 or the transfer time from the free memory area 11 to the memory 2-1 in the multiprocessor system shown in FIG. An example will be described in which 5 Kbytes of data, which takes longer than the time-out period, is transferred from CPU 1 to CPU 2 and a communication request is sent from CPU 3 to CPU 1 or CPU 2.

The task A of the CPU 1 is S1 in FIG.
An area for storing transfer data is acquired in the memory 1-1 of the own CPU, the transfer data to be transferred to the CPU 2 is stored in the area acquired in S1, and the data stored in S3 is stored in the CPU 2 in S2. Issue a data transfer system call for transmission to the mailbox 33 of

Then, the OS acquires an area for storing the transfer data in the free memory area 11 in the common memory 10 in S4, checks the transfer data length stored in S2 in S5, and checks the transfer data length in 5 Kbytes. Since the transfer time is longer than 1K bytes which can be shorter than the timeout time, it is divided into 1K bytes.

Then, in S6, the divided 1 Kbyte of data is transferred to the acquired area of the free memory area 11, and in S7, another C is stored in the inter-CPU interrupt notification register 21.
Checks if there is a communication request from the PU, and if there is, the corresponding C
The queuing request is issued to the PU, and the queuing request is not issued if there is no queuing request. This is repeated in S8, S6, and S7 until the transfer of all 5 Kbytes is completed.

In this case, the fact that the total transfer data length is 5 Kbytes means that the CPU in the inter-CPU communication area of the common memory 10
1 → Write to various data value areas 46 of CPU2, and inform CPU2 that the transfer data length is 5 Kbytes.

When there is a communication request from the CPU 3, the CPU
Since the column of CPU3 of the inter-interrupt notification register 21 becomes 1, in this case, a write wait request is issued to the end information area 43 of the CPU3 → CPU1 of the inter-CPU communication area of the common memory 10 at the end of each 1 Kbyte transfer. To do.

Next, in S9, the OS sets the CPU2 column of the inter-CPU interrupt request register 22 to 1, and sets the common memory 1
The data transfer system call type is written in the system call type region 44 of the CPU1 → CPU2 in the inter-CPU communication region of 0. Then, the OS of the CPU 2 knows the data transfer from the CPU 1 because the column of the CPU 1 of the inter-CPU interrupt notification register 31 is 1, and the common memory 1
Looking at the various data value areas 46 of the CPU1 → CPU2 in the inter-CPU communication area of 0, it is known that the transfer data is 5 Kbytes, and in S10 of FIG. 3, the storage area of the transfer data of 5 Kbytes in the memory 2-1. And proceed to S11.

In S11, the OS transfers the 1 Kbyte data transferred to the free memory area 11 of the common memory 10 to the acquired area, and in S12, sees the inter-CPU interrupt notification register 31 and sees from another CPU. The presence or absence of a communication request is checked, and if there is, a waiting request is made to the corresponding CPU, and if there is no waiting request, the waiting request is not made repeatedly at S13, S11, and S12 until the end of the 5 Kbyte transfer. 00 in the end information area 43 of the CPU1 → CPU2 of the inter-CPU communication area of the common memory 10
Write.

When there is a communication request from the CPU 3, the CPU
Since the column of CPU3 of the inter-interrupt notification register 31 is 1, in this case, a write wait request of 01 is written to the end information area 43 of the CPU3 → CPU2 of the inter-CPU communication area of the common memory 10 at the end of each 1 Kbyte transfer. To do.

Next, in S14, the OS issues a data transfer system call and sends the transfer data to the mailbox 33 in order to perform the data transfer system call on behalf of the CPU 1 in S3 of FIG. CPU1 is S in FIG.
At 15, the CPU in the inter-CPU communication area of the common memory 10
1 → Whether or not 00 of the processing end is written in the end information area 43 of the CPU 2 is checked, and if it is not ended, S1
At S6, the same process as S7 is performed, and if it is completed, S1
The area acquired in S4 is returned to the free memory area 11 in 7, and the area acquired in S1 is stored in the memory 1 in S18.
-1, returns to S1, checks the presence / absence of a communication request from the other CPU in the inter-CPU interrupt notification register 21. If not, END, and if there is, responds to the communication request CPU, for example, 3 in S25. Process and set to END.

On the other hand, the task B of the CPU 2 is S21 of FIG.
, Issue a system call for receiving the transfer data in the mailbox 33, acquire the transfer data in the mailbox 33 in S22, and store the area acquired in S10 in S23 in the memory 2-1. To return.

In step S19, the OS checks the presence / absence of a communication request from the other CPU in the inter-CPU interrupt notification register 31. If there is no communication request, END is set. If there is, the OS responds to the communication request CPU, eg, 3, in step S20. Process and set to END.

In this case, a time chart of the waiting setting of the CPU 1 and the communication request and the timeout time setting of the CPU 3 is shown in FIG.
Irrespective of whether the CPU 1 or the CPU 2 is normal, erroneously determine that a failure has occurred and no failure processing is performed.

[0033]

As described above in detail, according to the present invention, when a data transfer from the memory to the common memory or a transfer time from the common memory to the memory takes longer than the timeout time, a communication request is made. Other C
This has the effect of preventing the PU from performing fault handling by mistake.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention,

FIG. 2 is a flowchart of processing of the CPU 1 according to the embodiment of the present invention,

FIG. 3 is a flowchart of processing of the CPU 2 according to the embodiment of the present invention,

FIG. 4 is a time chart of a queuing request and a timeout time according to the embodiment of the present invention,

FIG. 5 is a block diagram of a main part of an example multiprocessor system,

6 is an example C between CPUn and CPUm of FIG.
A diagram showing details of a communication area between PUs,

FIG. 7 is a flowchart of processing of the CPU 1 of the conventional example,

FIG. 8 is a flowchart of processing of a CPU 2 of a conventional example.

[Explanation of symbols]

 1 to 4 are CPUs, 1-1 and 2-1 are memories, 10 is a common memory, 11 is a free memory area, 12 is a communication area between CPUs, 21 and 31 are interrupt notification registers between CPUs, and 22 and 32 are between CPUs Interrupt request register, 23 and 33 are mailboxes, 41 is CPU-ID area, 42 is task ID area, 43 is end information area, 44 is system call type area, 45 is various register value area, and 46 is various data value area Indicates.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yama ▲ Saki ▼ Mitsuo 3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Communication Systems Ltd.

Claims (1)

[Claims] 1. A first CP of a multiprocessor system.
The U (1) transfers the data written in the memory (1-1) to the common memory (10), and the second CPU (2) transfers the data transferred to the common memory (10) to its own memory (2-). It is transferred to the first CPU (1) and transferred to the second CPU (2) by being transferred to the own mailbox (2-2).
Data is transferred to the third CPU (3) and the first CPU (3)
When a communication request is made to the CPU (1) or the second CPU (2), a time-out time is set in a timer, and when the time-out time is reached, the CPU of the communication request destination is regarded as a failure and the failure processing is performed. To
Time for the first CPU (1) to transfer from the memory (1-1) to the common memory (10), or the second CPU
(2) is the memory (2-1) from the common memory (10)
The data transferred to the first CPU (1) is longer than the time-out time set by the third CPU (3).
When transferring to the second CPU (2), the data length is divided so that the transfer time is within the timeout time, and the first CPU (1) is divided for each divided data.
Is transferred to the common memory (10) and the second CPU
(2) performs the process of transferring from the common memory (10) until all the data is transferred, and the first CPU (1) transfers the third data to the first CPU (1) during data transfer. CPU
If there is a communication request from (3), the first CPU (1) makes a waiting request at the completion of transfer of the divided data to the common memory (10), and the second CPU (2) transfers the data. Inside the second CPU (2) to the third CPU (3)
If there is a communication request, the second CPU (2) issues a waiting request to the own memory (2-2) of the divided data from the common memory (10) each time transfer is completed, and the third C
The PU (3) checks whether or not a waiting request is issued each time the timeout time elapses, and if so, sets the timeout time again.
U-to-U data transfer method.