JPH06289811A - Driving method for memory type plasma display panel - Google Patents

Abstract

PURPOSE:To make the operation of a scanning modulation pulse generating circuit sure and stable and to improve the productivity and reliability by holding scanning base pulses voltage at a constant value while scanning modulation pulses are outputted to all scanning lines. CONSTITUTION:The scanning base pulses 3 are held at the constant voltage at least in a period wherein the scanning pulses 3 are applied, one after another. The voltage of the pulses 3 is suppressed to a voltage which does not cause write discharge even when superposed on the voltage of data pulses. Then subscanning pulses 6 which have a constant voltage are applied to a maintaining electrode in the batch scanning period wherein the scanning pulse voltage is applied to all the scanning lines one after another so that the potential difference between the scanning electrodes applied with the scanning pulse voltage and the maintaining electrode exceeds a discharge start voltage to cause misdischarge. Consequently, the scanning pulse voltage can be raised to a value required for the write discharge without misdischarge between the scanning electrodes and maintaining electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called dot matrix type memory type AC plasma display panel for use in personal computers, office workstations, wall-mounted televisions, etc., which are expected to grow in recent years. A drive device.

[0002]

2. Description of the Related Art A conventional AC type plasma display panel has a structure shown in FIG. In FIG. 8, (A) is a plan view and (B) is a sectional view taken along line xx ′ of (A). This plasma display panel includes a first insulating substrate 11 made of glass, a second insulating substrate 12 also made of glass, a row electrode 13, a column electrode 14, a discharge gas space 15 filled with a discharge gas such as He and Xe, and a discharge. A partition wall 16 that secures a gas space and divides pixels, and a phosphor 1 that converts ultraviolet light generated by discharge of a discharge gas into visible light
7. Insulating layer 18a covering row electrodes, insulating layer 1 covering column electrodes
8b, a protective layer 19 made of MgO or the like for protecting the insulator from discharge. In addition, in FIG.
Reference numeral 20 indicates a pixel. A plasma display capable of color display can be obtained by separately applying the phosphor 17 to each pixel in three colors.

Next, FIG. 9 shows a diagram focusing only on the electrodes of the plasma display panel. In FIG. 9, 20 is a pixel, 21 is a plasma display panel, and 22 is a first.
A seal portion for adhering the insulating substrate 11 and the second insulating substrate 12 together, sealing the discharge gas inside and hermetically sealing, S ₁ , S
₃ , ..., S _m-2 , S _m are sustain electrodes, S ₂ , S ₄ , ...
.., _Sm-3 and _Sm-1 are scanning electrodes, and S is a combination of these.
₁ , S ₂ , ..., S _m-1 , S _{m are} row electrodes 13.
Further, D ₁ , D ₂ , ..., D _n-1 , D _n indicate column electrodes.

FIG. 10 is a diagram showing an example of drive voltage waveforms and light emission waveforms of the plasma display panel shown in FIGS. In FIG. 10, a waveform (A) is a voltage waveform applied to the sustain electrodes S ₁ , S ₃ , ..., S _m-2 , S _m , and a waveform (B) is a voltage waveform applied to the scan electrode S _2. , Waveform (C) is a voltage waveform applied to the scan electrode S ₄ ,
The waveform (D) shows the voltage waveform applied to the column electrode D _j , and the waveform (E) shows the light emission waveform of the pixel a _2j . A sustain pulse 31 is applied to the sustain electrodes S ₁ , S ₃ , ..., S _m-2 , S _m . Further, the scanning electrodes S ₂ , S ₄ , ...,
In addition to the sustain pulse 32 common to these electrodes, a scan pulse 33 and an erase pulse 34 are line-sequentially applied to S _m-3 and S _m-1 at respective independent timings. The scan pulse further includes a scan base pulse 33a,
It is divided into scan modulation pulses 33b. Of these, the scan base pulse 33a is commonly applied to all scan electrodes. The scan modulation pulse 33b is line-sequentially applied to each scan electrode individually. When light emission data is present, a data pulse 35 is applied to each column electrode D _j in synchronization with the scan pulse 33.

In the plasma display panel having the structure shown in FIGS. 8 and 9, when the scan pulse and the data pulse are applied between the scan electrodes and the column electrodes at the same timing to perform the write discharge, the adjacent discharge is maintained thereafter. The sustain discharge is sustained by the sustain pulse 31 and the sustain pulse 32 between the electrode and the scan electrode. Such a function is called a memory function. Further, the sustain discharge can be stopped by applying a low voltage pulse having a narrow pulse width called an erase pulse to the scan electrodes.

Next, FIG. 11 shows a block diagram of a circuit for generating the above pulse waveform. A similar example of such a circuit configuration is described in, for example, "Plasma Display", Kenichi Ohwaki, Yoshinori Yoshida, ed., Kyoritsu Shuppan Co., Ltd. (published in 1st edition, November 15, 1983), page 38. In FIG. 11, reference numeral 41 denotes sustain electrodes S ₁ , S ₃ , ..., S _m-2 , S.
A sustain-side common pulse generator that generates sustain pulses 31 to be applied to _m , and 42 are scan electrodes S ₂ , S ₄ , ..., S
_This is a scanning-side common pulse generator that generates a sustain pulse 32, a scanning base pulse 33a, etc. that are common to _m-3 and _Sm-1 . Reference numeral 44 denotes a scan modulation pulse and erase pulse generation circuit, which is often integrated into an IC using a CMOS circuit or the like. An example of this circuit is, for example, JP-A-52-8313.
No. 5 and JP-A No. 52-83136. In this way, by dividing the scan pulse into the scan base pulse common to all scan electrodes and the scan modulation pulse applied to the individual scan electrodes, and combining them in series to generate the scan pulse, the scan modulation pulse voltage is It can be made smaller than when there is no scan base voltage. Therefore, the scan modulation pulse
The operating voltage of the scanning modulation pulse / erasing pulse generating switch 45 in the erasing pulse generating circuit 44 can be reduced, and the withstand voltage of the IC constituting the scanning modulating pulse / erasing pulse generating circuit 44 can be lowered. This allows
The reliability of the IC can be improved and the cost of the IC can be kept low.

In FIG. 11, reference numeral 46 is a data pulse DC power supply, 47 is a data pulse generation circuit, 48 is a data pulse generation switch, 43 is a scan modulation pulse DC power supply, 50 is an erase pulse DC power supply, and 49 is a scan. The modulation pulse generating circuit reference potential point, and 51 is the erase pulse generating circuit reference potential point.

Further, FIGS. 12 and 13 show examples of different plasma display panels. In FIG.
(A) is a plan view and (B) is a sectional view taken along line xx ′ of (A). As can be seen from the figure, one pixel includes two row electrodes 13. Therefore, as can be seen in FIG. 13, the number of sustain electrodes is one less than that in the case of FIG. 6, and S ₁ , S ₃ , ...
・ Up to S _m-2 . For driving this panel, the same drive waveform as in FIG. 10 can be used except that the number of sustain electrodes is one less than that in the case of FIG.

[0009]

In the circuit configuration of FIG. 11, the potentials of the scan modulation pulse generating circuit reference potential point 49 and the erase pulse generating circuit reference potential point 51 change when the sustain pulse and the scan base pulse are applied. Therefore, the IC forming the scan modulation pulse / erase pulse generating circuit 44 malfunctions and cannot be put to practical use.

Then, when this problem was investigated in detail,
In particular, it has been found that the IC picks up noise and malfunctions when the sustain pulse and the scan base pulse change. For example,
In FIG. 10, the sustain pulse has a width of 2 μsec and a period of 16 μm.
Second, peak voltage -160 V, scan pulse width 5 μsec,
The voltage is often -180 V, the scanning base pulse has a width of 5 μsec, and the voltage is often about -100 V. At this time, the time width of the rising and falling portions of the sustain pulse and the scan base pulse is required to be 1 μsec or less. That is,
A voltage change rate of 100 V / μsec or more is required. However, when the potentials of the scanning modulation pulse generating circuit reference potential point 49 and the erase pulse generating circuit reference potential point 51 change at such a large voltage change rate, the scanning modulation pulse.
The entire potential of the erase pulse generation circuit 44 cannot keep up with this change. Therefore, the same situation as that in which noise is added to the scanning modulation pulse / erasing pulse generating circuit 44 occurs. As a result, it was found that the scan modulation pulse / erase pulse generation circuit 44 malfunctions. In order to avoid this malfunction, the scanning modulation pulse generating circuit reference potential point 49,
It is effective to reduce the voltage change rate of the erase pulse generating circuit reference potential point 51. However, with the drive waveform as shown in FIG. 10, there is a problem that this voltage change rate cannot be reduced.

An object of the present invention is to reduce the voltage change rate and put a serial type scanning circuit which can operate with a low withstand voltage into practical use.

Further, in the case of using the driving waveform as shown in FIG. 10, if an attempt is made to increase the scanning voltage in order to ensure the writing discharge of the display data, an erroneous discharge will occur and the normal writing operation cannot be performed. There was a problem. On the contrary, when the writing is performed only with the scan voltage of the sustain pulse, the writing operation may be incomplete.

Another object of the present invention is to provide a plasma display panel driving apparatus using a serial scanning circuit,
It is to realize a more reliable write operation.

[0014]

A driving method of a memory type plasma display panel according to the present invention is a method for driving a memory-type plasma display panel, in which the entire surface of the panel or the divided panel portions are collectively discharged before a sustain discharge for light-emitting display is performed. Scan writing performed collectively over the divided panel portion is performed by a scan pulse in which a scan base pulse having a constant voltage applied during the scan writing period and a scan modulation pulse sequentially applied to scan electrodes are superimposed. It is characterized by

According to the present invention, at least during the period in which the scanning writing is performed collectively on the entire panel surface or the divided panel portions, the scanning electrodes to which the scanning pulse voltage is applied and the sustain electrodes are formed. The potential difference between
A constant voltage that is equal to or higher than the minimum value of the discharge sustaining voltage between the scan electrode and the sustain electrode in the write sustaining discharge, and is within a range equal to or lower than the discharge start voltage between the scan electrode and the sustain electrode in the write sustaining discharge. It is preferable to apply the sub-scanning pulse to the sustain electrodes.

According to the present invention, it is further preferable that the erase pulse is commonly applied to the sustain electrodes.

[0017]

The present invention realizes the stabilization of the serial scanning circuit by adopting the structure described in the means for solving the problems. That is, in order to ensure the operation of the serial type scanning circuit, the batch scanning type write driving method in which scanning and writing are collectively performed and then only sustain discharge is collectively performed is used. Further, the scanning base pulse voltage is kept at a constant value during the collective scanning period. As a result, in the circuit configuration of FIG. 2, the potential of the reference potential point 69 of the scan modulation pulse generation circuit 64 can be made constant during the period of generating the scan pulse. Therefore, first, during the collective scanning period, the malfunction of the scan modulation pulse generating circuit 64 could be eliminated. Further, since the logic circuit of the scan modulation pulse generation circuit 64 does not need to operate during the period other than the collective scanning, the potential of the reference potential point 69 may change at high speed. Therefore, according to the present invention, the serial scanning circuit can be put to practical use.

The batch scanning type write driving method is described in JP-A-63-151997 and JP-A-4-151997.
There is a method described in 195188. The method disclosed in Japanese Patent Laid-Open No. 4-42289 also includes a collective scanning type write driving method.

Further, the present invention solves the problem of stabilization of the write discharge in the case of performing the collective scanning by adopting the structure described in the means for solving the problems. That is,
In order to reliably shift the write discharge to the sustain discharge without erroneous discharge, the write discharge generated by the scan pulse and the data pulse is used as a pilot fire, and the discharge is generated between the scan electrode and the sustain electrode immediately after the write discharge (hereinafter It has been newly found that (writing sustain discharge) is required.

In order to reliably generate the addressing sustain discharge, the potential difference between the scan electrode and the sustain electrode must satisfy the following two conditions at the time when the address discharge occurs. First, the write sustain discharge does not occur unless this potential difference is equal to or higher than the minimum value of the discharge sustain voltage between the scan electrode and the sustain electrode in the write sustain discharge. The minimum value of the write sustaining discharge here does not always match the discharge sustaining voltage generally measured by increasing the AC pulse voltage. That is, the writing discharge is generated between the scan electrodes and the column electrodes, a considerable number of active particles are present, and the wall charges are started to be accumulated on the scan electrodes. It is often higher than the sustain voltage.

The other is that this potential difference is set to a voltage equal to or lower than the voltage (discharge starting voltage) at which the discharge starts by itself only by this potential difference. That is, the write sustain discharge should not occur between the scan electrode to which the scan pulse voltage is applied and the sustain electrode, although there is no write discharge. The discharge starting voltage here is higher than the discharge starting voltage based on only the sustain pulse. This is because the scan pulse cycle is much longer than the sustain pulse cycle.

Therefore, at least during the scanning period in which the scan pulse voltage is applied to the scan electrode, the potential difference between the scan electrode to which the scan pulse voltage is applied and the sustain electrode is
A voltage in a range that is equal to or higher than the minimum value of the discharge sustain voltage between the scan electrode and the sustain electrode in the write sustain discharge and equal to or lower than the discharge start voltage between the scan electrode and the sustain electrode in the write sustain discharge. , Decided to apply the sub-scanning pulse to the sustain electrodes. As a result, (1) since the scan pulse voltage can be set to the optimum value for the write discharge without erroneous discharge, the write discharge can be reliably generated. (2) The write sustain discharge that occurs immediately after the write discharge is now reliably generated without erroneous discharge. (3) When the write sustain discharge is surely generated, the sustain discharge thereafter is also surely generated.

For these reasons, the overall reliability of the writing discharge is greatly improved and the display quality is remarkably improved. A detailed description will be given below with reference to examples.

[0024]

EXAMPLE As a plasma display panel, as shown in FIG.
The one shown in FIG. 9 was used. Further, in FIG. 9, the scanning electrodes S ₂ , S ₄ , ..., S _m-3 , S _m-1 are 240 lines,
The sustain electrodes S ₁ , S ₃ , ..., S _m-2 , S _m are 241.
, Column electrodes D ₁ , D ₂ , ..., D _n-1 , D _n are 960
It is a book. The pitch of each pixel is 0.
6 mm and 0.4 mm between adjacent column electrodes.

FIG. 1 shows drive waveforms according to the first embodiment of the present invention. In FIG. 1, the waveform (A) is the sustain electrode S ₁ ,
S ₃ , ... Voltage waveforms applied to S _m-2 and S _m , waveform (B) is a voltage waveform applied to the first scan electrode S ₂ , and waveform (C) is a voltage waveform applied to the next scan electrode S _4. (D) is a voltage waveform applied to the last scan electrode S _m−1 , and waveform (E) is a voltage waveform applied to the column electrode D _j . For sustain electrodes S ₁ , S ₃ , ..., S _m-2 , S _m , sustain pulse 1 (pulse width 2.5 μs, period 6 μs,
Voltage -160V) is applied. Further, the scan electrodes S ₂ , S
₄ , ..., S _m-3 , S _m-1 are independent of each scan electrode in addition to sustain pulse 2 (the pulse width, period, and voltage are the same as sustain pulse 1) common to these electrodes. The scanning pulse 3 is applied at the timing. The erase pulse 4 has a wide pulse width (50 μsec) but a low voltage (-100 V),
A so-called thick erase pulse was used. Of course, instead of such an erase pulse, a narrow erase pulse, an erase pulse having a blunted waveform, or a composite pulse of these may be used.

The scan pulse further includes the scan base pulse 3
a (pulse width 1400 μsec, voltage −100 V) and scan modulation pulse 3b (pulse width 5 μsec, voltage −80 V). Of these, the scan base pulse 3a is commonly applied to all scan electrodes. The scan modulation pulse 3b is individually applied to each scan electrode. As can be seen from FIG. 1, the scan base pulse 3a is kept at a constant voltage at least during the period in which the scan pulses 3 are successively applied.
As a matter of course, the voltage of the scan base pulse 3a is suppressed to a voltage that does not cause the writing discharge even if it is superimposed on the voltage of the data pulse (pulse width 5 μsec, voltage 80 V). As described above, by keeping the scan base voltage at a constant value during the generation of the scan pulse, even if the drive circuit as shown in FIG. 2 is used, the scan modulation pulse generation circuit 64 malfunctions and an abnormal scan occurs. It is now possible to completely prevent the generation of modulated pulses.

FIG. 2 shows a basic block diagram of the drive circuit used for the drive of FIG. 11 is different from the conventional example shown in FIG.
The erase pulse 4 causes the sustain electrodes S ₁ , S ₃ , ..., S _m-2 ,
It is commonly applied to S _m . This erase pulse is supplied from the sustain-side common pulse generator 61. Since it is not necessary to apply the erase pulse to each scan electrode independently, the scan modulation pulse / erase pulse generation circuit 44 of FIG.
Can be simplified like the scan modulation pulse generation circuit 64. A high breakdown voltage IC, μPD16305, manufactured by NEC Corporation was used as the scanning modulation pulse generation circuit. A high breakdown voltage IC, μPD16306, also manufactured by NEC Corporation was used for the data pulse generation circuit. As the sustain-side common pulse generator 61 and the scan-side common pulse generator 62, well-known CMOS circuits with high breakdown voltage FETs are used.

In FIG. 2, reference numeral 66 is a data pulse DC power supply, 67 is a data pulse generation circuit, 68 is a data pulse generation switch, 63 is a scan modulation pulse DC power supply, 65 is a scan modulation pulse generation switch, and 69 is a reference. This is the potential point.

However, when the improved driving method is used, the gap between the scan electrode and the sustain electrode is
When the gap between the scan electrodes and the column electrodes is narrower, if the scan pulse voltage is increased in order to surely cause the write discharge, erroneous discharge may increase. As a cause of this,
It was considered that erroneous discharge was caused only by the scan pulse voltage between the scan electrode and the sustain electrode.

Therefore, as shown in the voltage waveform diagram of FIG. 3 (waveforms (A) to (E) are the waveforms described in FIG. 1), at least the scanning pulse voltage is applied to all the scanning electrodes one after another. During the collective scanning period, the sub-scanning pulse 6 having a constant voltage is applied so that the potential difference between the scan electrode to which the scan pulse voltage is applied and the sustain electrode does not exceed the discharge start voltage to cause erroneous discharge. It was applied to. As a result, the scan pulse voltage can be increased to a value required for writing discharge without erroneous discharge between the scan electrode and the sustain electrode.

At this time, if the voltage of the sub-scanning pulse 6 is made too large, the potential difference between the scan electrode to which the scan pulse voltage is applied and the sustain electrode becomes too small, and the write sustain discharge can be generated. Disappear. Therefore,
The voltage of the sub-scanning pulse 6 needs to be set such that the potential difference between the scan electrode and the sustain electrode is equal to or higher than the voltage at which the write sustain discharge can be generated.

As a concrete example of the above, consider the case described in FIG. In FIG. 1, in order to more reliably generate the write discharge, the scan modulation pulse voltage is set to −100V.
Then, if the peak value of the scan pulse voltage is set to -200 V, erroneous discharge occurs when the scan pulse is applied. Therefore,
When the voltage of the sub-scanning pulse 6 shown in FIG. 3 is set to −20 V, the writing discharge can be surely generated without erroneous discharge.

Contrary to the above case, particularly when the gap between the scan electrode and the sustain electrode is wider than the gap between the scan electrode and the column electrode, it should occur immediately after the writing discharge.
Write sustaining discharge between scan electrode and sustain electrode does not occur,
The transition from the write discharge to the sustain discharge was not successful in some cases.

Therefore, as shown in the voltage waveform diagram of FIG. 4 (the waveforms (A) to (E) are the waveforms described in FIG. 1), the scanning in which the scanning pulse voltage is applied during the collective scanning period. A sub-scanning pulse 6 having a constant voltage and a polarity opposite to that of the scanning pulse is applied to the sustain electrodes so that the potential difference between the electrodes and the sustain electrodes can generate the write sustain discharge.
That is, as in the embodiment of FIG. 3, the voltage between the scan electrode to which the scan pulse is applied and the sustain electrode is set within the range of the discharge sustain voltage. As a result, the transition from the write discharge to the write sustain discharge can be reliably performed.

In the present invention, the phenomenon is described as the size of the gap between the scan electrode and the sustain electrode and the gap between the column electrodes for the sake of simplicity as described above. There is a magnitude relationship between the characteristic voltages such as the discharge start voltage and the discharge sustain voltage defined by these gaps. It should be added that the characteristic voltage does not necessarily correspond to the size of the gap in a ratio of 1: 1 because it is influenced by factors such as the structure and the discharge gas.

Further, as apparent from the embodiments of FIGS. 3 and 4, by using the sub-scanning pulse of the present invention, the gap between the sustain electrode and the scan electrode and the gap between the scan electrode and the column electrode are Since it becomes possible to freely select when designing the panel, the degree of freedom in design is greatly increased, which is very useful in the production of the plasma display panel.

Further, as shown in the voltage waveform diagram of FIG. 5 (waveforms (A) to (E) are the waveforms described in FIG. 1), the scan pulse 3 is a negative voltage, the sustain pulse 1 and the sustain pulse 2 are set. Can be a positive voltage without any problem.

Further, as shown in the voltage waveform diagram of FIG. 6 (waveforms (A) to (E) are the waveforms described in FIG. 1), the scan pulse 3, sustain pulse 1, and sustain pulse 2 are all positive voltage. Also good. In this case, since the IC on the data side is usually made to generate a positive voltage pulse, this is used as it is. Contrary to the case of using the scan pulse of the negative voltage, when the voltage waveform (E) applied to the column electrode is zero at the timing when the scan pulse of the positive voltage is applied, the voltage between the column electrode and the scan electrode is When the voltage waveform (E) applied to the column electrode is a positive voltage, the potential difference between the column electrode and the scan electrode is small and the writing discharge does not occur.

Next, FIG. 7 shows an example in which a sub-scanning pulse is independently applied to each sustain electrode using the plasma display panel having the electrode structure shown in FIGS. 12 and 13. In FIG. 7, waveform (A) is a voltage waveform applied to sustain electrode S ₁ , waveform (B) is a voltage waveform applied to scan electrode S ₂ , and waveform (C) is a voltage applied to sustain electrode S _3. Waveforms and waveforms (D) are voltage waveforms applied to the scan electrodes S ₄ , waveforms (E) are voltage waveforms applied to the sustain electrodes S _m-2 , and waveforms (F) are applied to the scan electrodes S _m-1 . The waveform (G) indicates the voltage waveform applied to the column electrode D _j . As can be seen from FIG. 7, the sustain electrodes S ₁ ,
The sustain pulse 1 is commonly applied to S ₃ , ..., S _m-2 , and the sub-scanning pulse 6 is line-sequentially applied to each sustain electrode independently. Also, the scan electrodes S ₂ , S ₄ , ...
.., _Sm-3 , and _Sm-1 , in addition to the sustain pulse 2 common to these electrodes, an independent scan pulse 3 is line-sequentially applied to each scan electrode. The scan pulse 3 is the scan base pulse 3a common to all scan electrodes, as in the other embodiments.
And a scan modulation pulse 3b applied line-sequentially independently to each scan electrode. In this case, the write discharge operation is the same as in FIG.

As can be seen from the voltage waveform diagram of FIG. 7, in the present embodiment, unlike the other embodiments, the scan pulse 3 has the positive polarity and the sustain pulse 1 and the sustain pulse 2 have the negative polarity, but the other embodiment. The voltage may be distributed like this. Further, the erase pulse 4 may be applied to the sustain electrodes as in the other embodiments, or may be applied to all the scan electrodes instead of the sustain electrodes as in the present embodiment. Further, in the embodiments other than FIG. 7, the data pulse was continuously applied,
This need not always be the case, and the data pulses may be applied discretely as shown in FIG.

In the above embodiments, the case where the entire surface of the panel is first scanned and then the sustain discharge is performed has been described.
Needless to say, the driving method of the present invention may be applied to each panel portion by dividing the entire panel surface into a plurality of panel portions, not necessarily the entire panel.
Further, in the above embodiment, FIGS. 8, 9 and 12, and FIG.
The case where the AC surface discharge memory type plasma display panel shown in FIG. 3 is driven has been described, but it goes without saying that the present invention is not limited to this and can be applied to any type of AC memory type plasma display panel. .

[0042]

As described above, according to the present invention, when the AC memory type plasma display panel is driven by using the serial scanning circuit, while the scanning modulation pulse is continuously output to all scanning lines, The scan base pulse voltage is kept constant. Therefore, the reference potential of the scanning modulation pulse generating circuit is kept constant, and the operation of the scanning modulation pulse generating circuit can be made reliable and stable.
Therefore, it is possible to practically use a serial type scanning circuit using an IC having high productivity, low cost, high reliability, and low withstand voltage, and to obtain an inexpensive and highly reliable plasma display panel driving device. It is very useful industrially.

Further, by applying the sub-scanning panel to the sustain side during the collective scanning period, the scanning pulse voltage can be freely set within the range where reliable writing discharge occurs. Further, the sub-scanning pulse ensures that the write sustaining discharge is generated almost at the same time as the write discharge.

Therefore, the write discharge is surely generated, the write discharge is surely shifted to the write sustain discharge, and then the sustain discharge is surely performed, so that the overall data write probability is increased and the display quality is improved.

Also, by using the present invention, the gap between the sustain electrodes and the scan electrodes and the gap between the scan electrodes and the column electrodes can be freely selected at the time of designing the panel. It becomes large and is very useful in the production of plasma display panels.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a driving method of the present invention.

FIG. 2 is a configuration diagram of a drive circuit using the drive method of the present invention.

FIG. 3 is a diagram showing a second embodiment of the driving method of the present invention.

FIG. 4 is a diagram showing a third embodiment of the driving method of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the driving method of the present invention.

FIG. 6 is a diagram showing a fifth embodiment of the driving method of the present invention.

FIG. 7 is a diagram showing a sixth embodiment of the driving method of the present invention.

FIG. 8 is a plan view and a sectional view of a plasma display panel.

9 is a configuration diagram of a plasma display panel focusing on the electrode arrangement of the plasma display panel of FIG.

FIG. 10 is a diagram showing a drive voltage waveform and a light emission waveform of the plasma display panel.

FIG. 11 is a drive circuit configuration diagram of a conventional plasma display panel.

FIG. 12 is a plan view and a cross-sectional view of another example of the plasma display panel.

13 is a configuration diagram focusing on the electrode arrangement of the plasma display panel of FIG.

[Explanation of symbols]

1,31 Sustain pulse 2,32 Sustain pulse 3,33 Scan pulse 3a, 33a Scan base pulse 3b, 33b Scan modulated pulse 4,34 Erase pulse 5,35 Data pulse 6 Sub scan pulse 11 First insulating substrate 12 Second insulation Substrate 13 Row electrode 14 Column electrode 15 Discharge gas space 16 Partition 17 Phosphor 18a, 18b Insulating layer 19 Protective layer 20 Pixel 21 Plasma display panel 22 Seal part 41, 61 Sustaining side common pulse generator 42, 62 Scanning side common pulse generation 43,63 DC power supply for scanning modulation pulse 44 Scanning modulation pulse / erasing pulse generating circuit 45 Scanning modulation pulse / erasing pulse generating switch 46,66 DC power supply for data pulse 47,67 Data pulse generating circuit 48,68 Data pulse generating switch 49 Scan modulation pulse generation circuit board Potential point 50 erase pulse DC power supply 51 erase pulse generating circuit reference potential point 64 scans modulated pulse generating circuit 65 scan MPG switch 69 reference potential point _{D 1, D 2, ···,} D n-1, D n columns Electrodes S ₁ , S ₂ , ..., S _m-1 , S _m row electrodes S ₁ , S ₃ , ..., S _m-2 , S _m sustain electrodes S ₂ , S ₄ , ..., S _m-3 , S _m-1 scanning electrode

Claims (3)

[Claims] 1. A scan writing is performed collectively over the entire panel or divided panel portions prior to a sustain discharge for light emission display performed over the entire panel or divided panel portions. A driving method of a memory type plasma display panel, which is performed by a scan base pulse having a constant voltage applied during a writing period and a scan pulse in which a scan modulation pulse sequentially applied to scan electrodes is superimposed. 2. The method for driving a memory-type plasma display panel according to claim 1, wherein a scan pulse voltage is applied during a period in which scan writing is performed collectively on at least the entire surface of the panel or a divided panel portion. The applied potential difference between the scan electrode and the sustain electrode is equal to or higher than the minimum value of the discharge sustain voltage between the scan electrode and the sustain electrode in the write sustain discharge, and the scan electrode and the sustain electrode in the write sustain discharge. A method for driving a memory type plasma display panel, characterized in that a sub-scanning pulse having a constant voltage, which is within a range equal to or lower than a discharge start voltage between the two, is applied to the sustain electrodes. 3. The method of driving a memory type plasma display panel according to claim 2, wherein an erase pulse is commonly applied to the sustain electrodes.