JPH0628847A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a current consumption in the data retention mode of a pseudo static type RAM or the like. CONSTITUTION:The pseudo static type RAM having the data retention mode is equipped with a substrate voltage generating circuit VBBG which prepares a prescribed substrate voltage VBB, and supplies it to a P type semiconductor substrate PSUB, and a well voltage generating circuit VWBG which prepares a prescribed well voltage VWB, and supplies it to an N type well area NWELL. When the data retention mode is designated, the solute values of the substrate voltages VBB and well voltage VWB are selectively made large. Thus, the threshold voltage of an MOSFET is selectively made large, and the sub-threshold current is made small, so that the current consumption in the data retention mode of the pseudo static type RAM or the like can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when used in a pseudo static RAM (random access memory) having a data retention mode.

[0002]

2. Description of the Related Art There is a dynamic RAM having a MOSFET (Metal Oxide Semiconductor Field Effect Transistor. In this specification, MOSFET as a general term for an insulated gate field effect transistor). Pseudo-static RA having a dynamic RAM as a basic configuration and compatibility with static RAM
There is M. Furthermore, these pseudo static RAMs
In the above, by applying an appropriate substrate voltage to the semiconductor substrate on which the MOSFET is formed,
Controls the parasitic capacitance between the FET and the like, the threshold voltage, etc.,
A method for stabilizing the operation is known, and there is a pseudo static RAM including a substrate voltage generating circuit that forms a predetermined substrate voltage based on the power supply voltage of the circuit.

On the other hand, in personal computers, workstations, etc., a so-called battery backup function has been generalized in which the contents of memory are held by a battery or the like even after the main power supply is cut off. At the time of such battery backup, the absolute value of the power supply voltage is There is known a data retention mode for selectively reducing the current consumption of a pseudo static RAM or the like by reducing the size.

A memory integrated circuit device incorporating a substrate voltage generating circuit is described in, for example, Japanese Patent Laid-Open No. 61-059688.

[0005]

In a conventional pseudo-static RAM or the like having a built-in substrate voltage generation circuit, the substrate voltage is less likely to change due to fluctuations in the power supply voltage and fluctuations in the semiconductor substrate and device ambient temperature. The value is stable.

On the other hand, the current consumption in the data retention mode of the pseudo static RAM or the like is defined by an extremely small value corresponding to the subthreshold current of the MOSFET included in the pseudo static RAM and the current consumption of the voltage generating circuit. It However, as apparent from FIGS. 10 and 11, the subthreshold current of the MOSFET changes substantially in proportion to the ambient temperature, for example, 25 ° C.
3 at normal temperature like 80 ° C and at relatively high temperature like 80 ° C
This results in a difference of the order of magnitude, and results in pushing up the entire subthreshold current of the pseudo-static RAM or the like, which was on the order of pA (picoampere), to the order of tens of μA (microamperes). Due to this phenomenon, the consumption current of the pseudo static RAM or the like is increased from about 10 μA to about 100 μA. Such an increase in the standby current does not cause a problem in a normal memory integrated circuit in which the standby current is a few mA (milliamperes) at room temperature, but in the pseudo static RAM having the data retention mode, the product specifications are different. It will be a fatal size that can not satisfy.

An object of the present invention is to provide a pseudo static type R
It is to reduce current consumption in a data retention mode such as AM.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a substrate voltage generating circuit for forming a predetermined substrate voltage and supplying it to a semiconductor substrate in a pseudo static RAM or the like having a data retention mode,
A well voltage generating circuit that forms a predetermined well voltage and supplies it to the well region is provided, and when the data retention mode is designated, the absolute values of the substrate voltage and the well voltage are selectively increased.

[0010]

According to the above means, the pseudo static RAM
Since it is possible to selectively increase the threshold voltage of the MOSFET included in the data retention mode in the data retention mode and reduce the subthreshold current thereof, it is possible to reduce the current consumption in the data retention mode of the pseudo static RAM. You can

[0011]

1 is a block diagram showing an embodiment of a pseudo static RAM to which the present invention is applied. An outline of the structure and operation of the pseudo static RAM of this embodiment will be described first with reference to FIG. The circuit elements forming each block in FIG.
It is formed on one semiconductor substrate like single crystal silicon by a manufacturing technique of a MOS (complementary MOS) integrated circuit.

In FIG. 1, the pseudo static RAM (PSRAM) of this embodiment has an internal logic circuit LC including a memory array and its peripheral circuits as a basic structure. A power supply voltage VCC and a ground potential VSS are supplied to the internal logic circuit LC via external terminals VCC and VSS, respectively, and a chip enable signal CEB (here, a start enable signal which is a start control signal via external terminals CEB, WEB, OEB and RFB). For so-called inverted signals and inverted signal lines, etc., which are selectively brought to a low level when they are enabled, their names are suffixed with B. The same applies hereinafter), write enable signal WEB, output enable The signal OEB and the refresh control signal RFB are supplied respectively. These activation control signals are supplied to the timing generation circuit TG included in the internal logic circuit LC, whereby the internal control signal DRM and the clock signals CP1 and CP2 are selectively formed. Write data is further input to the internal logic circuit LC in 1-bit units via the external terminal Din, and read data is output in 1-bit units via the external terminal Dout. Also, the external terminals AX0-A
An i + 1-bit X address signal is supplied via Xi, and a j + 1-bit Y is supplied via external terminals AY0 to AYj.
An address signal is supplied.

In this embodiment, the power supply voltage VCC is
Although not particularly limited, when the pseudo static RAM is in a normal operation mode, it is set to a positive power supply voltage such as + 5V, and when it is in a data retention mode, + 3V.
The power supply voltage is relatively low. Further, each start control signal, write data, read data, and address signal are so-called TTL (Transistor).
It is a digital signal of the Transistor Logic level. On the other hand, the internal control signal DRM is selectively set to the high level when the pseudo static RAM is in the data retention mode. Further, the clock signal CP1 is temporarily set to the high level in a predetermined cycle, and the clock signal CP2 is set to the high level cyclically and temporarily, slightly behind the clock signal CP1.
A detailed description of the internal logic circuit LC is omitted because it is not directly related to the present invention.

By the way, the internal logic circuit LC uses as its basic logic circuit a CMOS logic circuit in which N-channel and P-channel MOSFETs are combined. Of these, the N-channel MOSFET has an N-type diffusion layer formed on a P-type semiconductor substrate as its source and drain,
The P-channel MOSFET uses the P-type diffusion layer formed in the N-type well region on the P-type semiconductor substrate as its source and drain. Pseudo-static RAM of this embodiment
Then, a predetermined substrate voltage VBB is supplied to the P-type semiconductor substrate in which the N-channel MOSFET is formed, and a predetermined well voltage VWB is supplied to the N-type well region in which the P-channel MOSFET is formed. A method of stabilizing the operation by controlling the parasitic capacitance and the threshold voltage between the MOSFET and the semiconductor substrate or the well region constituting the device is adopted. Therefore, in the pseudo static RAM, the substrate voltage VBB is based on the power supply voltage VCC.
And a substrate voltage generating circuit VBBG which supplies the voltage to the P-type semiconductor substrate (PSUB) and a well voltage VWB based on the power supply voltage VCC.
Well voltage generating circuit VWBG supplied to LL) is provided.

On the other hand, the pseudo static type R of this embodiment
The AM has a data retention mode for selectively reducing the current consumption when the battery is backed up. In the data retention mode, in the pseudo static RAM, the power supply voltage VCC is set to + 3V as described above, and the current consumption thereof is generally reduced. Further, in the data retention mode, as will be described later, the absolute values of the substrate voltage VBB and the well voltage VWB are selectively increased or deepened, whereby the N-channel and P-channel MOS transistors are formed.
The threshold voltage of the FET is selectively increased. As a result, the subthreshold current of the MOSFET is reduced, and the current consumption of the pseudo-static RAM in the data retention mode especially under high temperature is reduced.

In this embodiment, the data retention mode of the pseudo static RAM is + 5V in the normal operation mode when the refresh control signal RFB which is the start control signal is continuously set to the low level for a predetermined time or longer. It is selectively designated by lowering the potential of the power supply voltage VCC to + 3V. Of these, the refresh control signal RFB is monitored by the timing generation circuit TG of the internal logic circuit LC as described above,
When the data generation mode is identified by the timing generation circuit TG, the internal control signal DRM is selectively set to the high level. On the other hand, the potential of the power supply voltage VCC is monitored by the power supply voltage sensor VCCS, and when the data retention mode is identified by the power supply voltage sensor VCCS, or the internal control signal DRM.
Is set to the high level, its output signal, that is, the internal control signal VCL is selectively set to the high level.

The internal control signal VCL is supplied to the substrate voltage generating circuit VBBG and the well voltage generating circuit VWBG. Substrate voltage generation circuit VBBG is further supplied with clock signal CP1, and well voltage generation circuit VWBG is supplied with clock signals CP1 and CP2. When the pseudo-static RAM is set to the normal operation mode and the internal control signal VCL is set to the low level, the substrate voltage generation circuit VBBG forms the substrate voltage VBB having a relatively small absolute value close to −2V and the P-type semiconductor. Supply to the substrate.
In addition, the well voltage generation circuit VWBG has a power supply voltage VCC.
A well voltage VWB having the same potential as that, that is, a relatively small absolute value such as +5 V is formed and supplied to the N-type well region.
On the other hand, when the pseudo static RAM is set to the data retention mode and the internal control signal VCL is set to the high level, the substrate voltage generation circuit VBBG forms the substrate voltage VBB having a relatively large absolute value close to -3V and the P type. Supply to semiconductor substrate. In addition, the well voltage generation circuit VWBG
Is a well voltage V having a relatively large absolute value such as + 6V.
WB is formed and supplied to the N-type well region. Specific configurations and operations of the substrate voltage generating circuit VBBG and the well voltage generating circuit VWBG and their characteristics will be described in detail later.

FIG. 2 shows the pseudo static RA of FIG.
A circuit diagram of one embodiment of the power supply voltage sensor VCCS included in M is shown. Based on the figure, the power supply voltage sensor VCCS included in the pseudo static RAM of this embodiment.
The specific configuration and operation of will be described. In the following circuit diagrams, the MOSFET with an arrow added to its channel (back gate) portion is a P-channel type MOSFET, and is shown separately from the N-channel MOSFET without an arrow.

In FIG. 2, the power supply voltage sensor VCCS
Is not particularly limited, but three P-channel M provided in series between the power supply voltage VCC and the ground potential VSS.
It includes OSFETs QP1 to QP3 and one N-channel MOSFET QN1. Of these, MOSFETQ
The gates and drains of P1 to QP3 are commonly coupled to form a diode,
The clock signal CP1 is supplied to the gate of QN1. The commonly coupled drains of MOSFETs QP3 and QN1 are coupled to the input terminal of inverter N1 as internal node n1. The output terminal of the inverter N1 is coupled to one input terminal of the OR gate OG1, and the internal control signal DRM is supplied to the other input terminal of the OR gate OG1. The output signal of the OR gate OG1 is supplied to the substrate voltage generation circuit VBBG and the well voltage generation circuit VWBG as the output signal of the power supply voltage sensor VCCS, that is, the internal control signal VCL.

When the pseudo static RAM is in the normal operation mode and the internal control signal DRM is at low level, the power supply voltage VCC is + 5V as described above. At this time, in the power supply voltage sensor VCCS, the MOSF is provided on condition that the clock signal CP1 is at the high level.
A predetermined sense current flows through ETQP1 to QP3 and QN1, but internal node n1 receives power supply voltage VC.
By setting C to + 5V, the potential is set to a relatively high potential exceeding the logic threshold of the inverter N1. However,
The output signal of the inverter N1 also becomes low level, whereby the output signal of the OR gate OG1, ie, the internal control signal VCL becomes low level.

On the other hand, when the pseudo static RAM is set to the data retention mode, the internal control signal DRM is set to the high level or the power supply voltage VCC is set to + 3V as described above. When the internal control signal DRM is set to the high level, in the power supply voltage sensor VCCS, the output signal of the OR gate OG1, that is, the internal control signal VCL is set to the high level regardless of the output signal of the inverter N1. Further, when the power supply voltage VCC is +3 V, the power supply voltage sensor VCCS has MOSFETs QP1 to QP provided that the clock signal CP1 is at a high level.
A relatively small sense current is passed through 3 and QN1, and in response thereto, internal node n1 is set to a predetermined potential lower than the logic threshold of inverter N1. However, the output signal of the inverter N1 becomes high level,
As a result, the output signal of the OR gate OG1, that is, the internal control signal VCL becomes high level.

When the clock signal CP1 is at low level, the power supply voltage sensor VCCS detects that the power supply voltage V
The MOSFET QN1 is turned off regardless of the potential of CC. Therefore, the input terminal of the inverter N1 is M
It is set to a high level like the power supply voltage VCC via the OSFETs QP1 to QP3, and its output signal is unconditionally set to a low level. That is, in the pseudo static RAM of this embodiment, the monitoring of the power supply voltage VCC by the power supply voltage sensor VCCS is selectively executed in response to the high level of the clock signal CP1, thereby the steady consumption of the pseudo static RAM. The current will be reduced.

FIG. 3 shows the pseudo static RA of FIG.
A block diagram of an embodiment of the substrate voltage generation circuit VBBG included in M is shown, and FIGS. 4 and 5 show a substrate voltage sensor VBSN for normal operation and data retention included in the substrate voltage generation circuit VBBG of FIG. Substrate voltage sensor VB
The circuit diagrams of one embodiment of SR are respectively shown. 6 is a block diagram of an embodiment of the well voltage generating circuit VWBG included in the pseudo static RAM of FIG. 1, and FIGS. 7 and 8 show the well voltage generating circuit VWBG of FIG. The circuit diagrams of one embodiment of the well voltage sensor VWBS and the well potential leak circuit VWBL included therein are respectively shown. Further, FIG. 9 shows a signal waveform diagram of one embodiment of the substrate voltage generating circuit VBBG of FIG. 3 and the well voltage generating circuit VWBG of FIG. 6, and FIG. 10 and FIG. 11 constitute a pseudo static RAM. General characteristic diagrams for explaining the relationship between the gate-source voltage and the drain current of the N-channel MOSFET and the P-channel MOSFET, respectively, are shown. Based on these figures, the pseudo static RA of this embodiment
The specific configurations and operations of the M substrate voltage generating circuit VBBG and the well voltage generating circuit VWBG and the features thereof will be described. In FIG. 9, the signals SN and SR
And SW are clock signals CP1 as described later.
, And CP2, but in order to avoid complication, they are changed independently of these clock signals. In addition, the pseudo static RAM has a power supply voltage V
It is assumed that the data retention mode is selectively set by setting CC lower than a predetermined potential VCR. Therefore, the internal control signal VCL has a power supply voltage VCC of the above potential VCR.
When it is lower than CR, it is selectively set to the high level.

In FIG. 3, the substrate voltage generating circuit VBBG
Is not particularly limited, but is a substrate voltage sensor VB for normal operation which receives the clock signal CP1 and the internal control signal VCL.
SN (first substrate voltage sensor) and clock signal CP1
And a data retention substrate voltage sensor VBSR (second substrate voltage sensor) for receiving an inverted signal of the internal control signal VCL by the inverter N2, that is, an inverted internal control signal VCLB, and further, a large capacity having a relatively large current supply capability. A substrate voltage output circuit VBGL (first substrate voltage output circuit) and a small capacity substrate voltage output circuit VBGS (second substrate voltage output circuit) having a relatively small current supply capability are provided.

The large capacity substrate voltage output circuit VBGL is connected to the normal operation substrate voltage sensor VBS through the complementary gate G1.
The output signal SN of N is selectively supplied to the complementary gate G2.
Through the data retention substrate voltage sensor VBSR
Output signal SR of is selectively supplied. Of these, the N channel and the P channel M forming the complementary gate G1
The OSFET is supplied with the inverted internal control signal VCLB and the internal control signal VCL, respectively, and the N-channel and P-channel MOSFETs forming the complementary gate G2 are supplied with the internal control signal VCL and the inverted internal control signal VCLB.
Are supplied respectively. As a result, the large-capacity substrate voltage output circuit VBGL is complemented when the internal control signal VCL is at the low level and the inverted internal control signal VCL is at the high level, that is, when the pseudo static RAM is in the normal operation mode. When the output signal SN of the normal operation substrate voltage sensor VBSN is selectively supplied through the gate G1, the internal control signal VCL is set to the high level and the inverted internal control signal VCL is set to the low level, that is, the pseudo static RAM is In the data retention mode, the output signal SR of the data retention substrate voltage sensor VBSR is selectively supplied via the complementary gate G2.

The large-capacity substrate voltage output circuit VBGL is selectively activated by setting the output signal SN of the normal operation substrate voltage sensor VBSN or the output signal SR of the data retention substrate voltage sensor VBSR to low level. A predetermined substrate voltage VBB is formed. Further, the small-capacity substrate voltage output circuit VBGS is a pseudo static type RA.
Regardless of the operating mode of M, the operating state is constantly made, and a predetermined substrate voltage VBB is formed. The substrate voltage VBB formed by the large-capacity substrate voltage output circuit VBGL and the small-capacity substrate voltage output circuit VBGS is supplied to the P-type semiconductor substrate and supplied to the normal operation substrate voltage sensor VBSN and the data retention substrate voltage sensor VBSR. Is also supplied. It should be noted that the substrate voltage generation circuit VBBG has a large capacity substrate voltage output circuit VBG having a relatively large current supply capability.
By including L and the small-capacity substrate voltage output circuit VBGS having a relatively small current supply capability, the current consumption in the standby state of the pseudo static RAM can be further reduced.

As shown in FIG. 4, the substrate voltage sensor VBSN for normal operation has a power supply voltage VCC and a substrate voltage VB.
One P-channel MOS provided in series between B
FET QP4 and 3 N-channel MOSFETs
Includes QN2 to QN4. Of these, MOSFET QP4
An inverted signal of the clock signal CP1 generated by the inverter N3 is supplied to the gate of the MOSFET, and an internal control signal VCL is supplied to the gate of the MOSFET QN2. MOSFET
The gates and drains of QN3 and QN4 are commonly coupled, so that both QN3 and QN4 have a diode configuration. MO
The commonly coupled drains of SFETs QP4 and QN2 are coupled to the input terminal of inverter N4 as internal node n2. The output signal of the inverter N4 becomes the output signal SN of the normal operation substrate voltage sensor VBSN.

When the pseudo static RAM is set to the data retention mode and the internal control signal VCL is set to the high level, the normal operation substrate voltage sensor VBSN:
MOSFET QN2 is turned on almost constantly, and internal node n2 is set to a potential lower than the logic threshold level of inverter N4 almost constantly regardless of the on state of MOSFET QP4. Therefore, the inverter N4
That is, the output signal SN of the normal operation substrate voltage sensor VBSN is constantly set to a high level, that is, an invalid level, as shown in FIG. 9, and the large capacity substrate voltage output circuit VBSN is output.
The GL is selectively activated in accordance with the output signal SR of the constituent data retention substrate voltage sensor VBSR.

On the other hand, when the pseudo static RAM is set to the normal operation mode and the internal control signal VCL is set to the low level, the normal operation substrate voltage sensor VBSN outputs MO.
SFETQP4 is an inverter N3 for the clock signal CP1
Is turned on selectively on condition that the inversion signal by is low level, whereby the normal operation substrate voltage sensor VBSN is enabled. At this time, the substrate voltage V
When the absolute value of BB is larger than a predetermined value VBB1 (first predetermined value) of VBB1 = 3 × Vthn and is at a sufficiently deep potential, the MOSFETs QN2 to QN4 are turned on, and the internal node n2 becomes the logic of the inverter N4. The potential is lower than the threshold. This allows
Inverter N4, that is, substrate voltage sensor VB for normal operation
The output signal SN of SN is set to the high level, that is, the invalid level, and the large-capacity substrate voltage output circuit VBGL is set to the inactive state. However, at this time, if the absolute value of the substrate voltage VBB is smaller than the predetermined value VBB1 and is in a relatively shallow state, the MOSFETs QN2 to QN4 are turned off,
The internal node n2 is at a high level like the power supply voltage VCC. Therefore, the output signal SN of the inverter N4, that is, the normal operation substrate voltage sensor VBSN is set to the low level, that is, the effective level, whereby the large capacity substrate voltage output circuit VBGL is activated. Note that Vthn in the above equation indicates the threshold voltage of the N-channel MOSFET.

Next, the data retention substrate voltage sensor VBSR, as shown in FIG.
And a P provided in series between the substrate voltage VBB and the substrate voltage VBB.
It includes a channel MOSFET QP5 and four N-channel MOSFETs QN5 to QN8. Of these, M
An inverted signal of the clock signal CP1 from the inverter N5 is supplied to the gate of the OSFET QP5, and
The inverted internal control signal VCLB is supplied to the gate of TQN5. The gates and drains of the MOSFETs QN6 to QN8 are commonly coupled to each other so that they have a diode configuration. The commonly coupled drains of MOSFETs QP5 and QN5 are coupled to the input terminal of inverter N6 as internal node n3. The output signal of the inverter N6 is a substrate voltage sensor VBSR for data retention.
Output signal SR.

When the pseudo static RAM is in the normal operation mode and the inverted internal control signal VCLB is at the high level, the substrate voltage sensor for data retention VBS is used.
At R, the MOSFET QN5 is turned on almost constantly, and the internal node n3 is set to a potential lower than the logic threshold level of the inverter N6 almost constantly regardless of the on state of the MOSFET QP5. However, the output signal SR of the inverter N6, that is, the data retention substrate voltage sensor VBSR, is as shown in FIG.
Since the high-level substrate voltage output circuit VBGL is almost constantly set to the high level, that is, the ineffective level, the large-capacity substrate voltage output circuit VBGL is selectively operated according to the output signal SN of the normal operation substrate voltage sensor VBSN.

On the other hand, when the pseudo static RAM is set to the data retention mode and the inverted internal control signal VCLB is set to the low level, in the data retention substrate voltage sensor VBSR, the MOSFET QP5 inverts the clock signal CP1 by the inverter N5 to the low level. Under certain conditions, it is selectively turned on, whereby the data retention substrate voltage sensor VBSR is enabled. At this time, when the absolute value of the substrate voltage VBB is larger than a predetermined value VBB2 (second predetermined value) VBB2 = 4 × Vthn,
In other words, the substrate voltage VBB is the predetermined value VBB1.
If it is deeper than Vthn by more than Vthn, MOSFET QN5-5
QN8 is turned on all at once, and internal node n3 is set to a potential lower than the logic threshold level of inverter N6. As a result, the output signal SR of the inverter N6, that is, the data retention substrate voltage sensor VBSR is output.
Is set to a high level, that is, an invalid level, and the large-capacity substrate voltage output circuit VBGL is set to the non-operation state. However,
At this time, the absolute value of the substrate voltage VBB is the predetermined value VBB.
When it is smaller than 2, the MOSFETs QN5 to QN8 are turned off and the internal node n3 is set to a high level like the power supply voltage VCC. Therefore, the output signal SR of the inverter N6, that is, the data retention substrate voltage sensor VBSR is set to the low level, that is, the effective level, and the large capacity substrate voltage output circuit VBGL is activated in response to the low level of the output signal SR.

As a result, in the substrate voltage generating circuit VBBG of this embodiment, as shown in FIG.
When the pseudo static RAM is in the normal operation mode, the potential of BB is controlled to be VBB = −3 × Vthn, that is, a relatively shallow potential close to, for example, −2 V, and the pseudo static RAM is in the data retention mode. Is controlled so that VBB = −4 × Vthn, that is, a relatively deep potential close to −3V. When the substrate voltage VBB is deepened by about 1V, in each part of the pseudo static RAM, an N channel MOS is
The threshold voltage of the FET is increased, for example, by about 0.1 to 0.3V. As is apparent from FIG. 10, this change in the threshold voltage produces an effect of reducing the drain current of the N-channel MOSFET, that is, the subthreshold current by about 1 to 3 digits, and thereby the pseudo static type in the data retention mode. The standby current of the RAM is reduced to, for example, several μA to several hundred pA regardless of the ambient temperature.

Well voltage generating circuit VWBG is not particularly limited, but as shown in FIG. 6, a well voltage sensor VWBS receiving clock signal CP1 and a well potential leak circuit VWBL receiving internal control signal VCL are provided. And a large capacity well voltage output circuit VWGL (first well voltage output circuit) having a relatively large current supply capacity and a small capacity well voltage output circuit VWGS (second well) having a relatively small current supply capacity. Voltage output circuit).

In the large capacity well voltage output circuit VWGL,
The output signal of the NAND gate NAG1 is supplied as a start signal, and the output signal of the NAND gate NAG2 is supplied as a start signal to the small capacity well voltage output circuit VWGS. The clock signal CP2 is supplied to the first input terminals of the NAND gates NAG1 and NAG2, and the internal control signal VCL is supplied to the third input terminal of the NAND gate NAG1 and the second input terminal of the NAND gate NAG2. The output signal SW of the well voltage sensor VWBS is supplied to the second input terminal of the NAND gate NAG1.

As a result, the large capacity well voltage output circuit V
WGL is a well voltage sensor V when the output signal of the NAND gate NAG1 is at a low level, in other words, when the pseudo static RAM is in the data retention mode and the internal control signal VCL is at a high level.
Upon receiving the high level of the output signal SW of WBS, it is selectively brought into an operating state, and the well voltage VWB having a relatively large absolute value is formed by boosting the power supply voltage VCC. In addition, the small-capacity well voltage output circuit VWGS is almost constantly operated when the output signal of the NAND gate NAG2 is at a low level, in other words, when the pseudo static RAM is in the data retention mode, and the power supply is also the same. By boosting the voltage VCC, the well voltage VWB having a relatively large absolute value is formed.

The output signals of the NAND gates NAG1 and NAG2 strobed by the clock signal CP2 are set in one cycle of the clock signal CP2 by the latch circuits provided in the large capacity well voltage output circuit VWGL and the small capacity well voltage output circuit VWGS. Hold for a corresponding period. The well voltage VWB formed by the large-capacity well voltage output circuit VWGL and the small-capacity well voltage output circuit VWGS is supplied to the N-type well region where the P-channel MOSFET is formed, and the well voltage sensor VWBS and the well potential. It is also supplied to the leak circuit VWBL. In this way, the well voltage generation circuit VWB
Since G is composed of the large capacity well voltage output circuit VWGL having a relatively large current supply capacity and the small capacity well voltage output circuit VWGS having a relatively small current supply capacity, the current consumption in the standby state of the pseudo static RAM is reduced. It will be further reduced.

As shown in FIG. 7, the well voltage sensor VWBS includes two P-channel MOSFEs arranged in series between the well voltage VWB and the ground potential VSS.
TQP6 and QP7 and one N-channel MOS
Includes FET QN9. Of these, MOSFET QP6
Is formed into a diode by commonly connecting its gate and drain, and the gate of MOSFET QP7 is
It is coupled to the power supply voltage VCC. In addition, MOSFETQN
The clock signal CP1 is supplied to the gate of
The commonly coupled drains of FETs QP7 and QN9 are
Internal node n4 is coupled to the input terminal of inverter N7. The output signal of the inverter N7 becomes the output signal SW of the well voltage sensor VWBS.

When the clock signal CP1 is at low level, the well voltage sensor VWBS has the MOSFET Q
N9 is turned off. At this time, the internal node n4
Is set to a high level that is higher than the logic threshold level of the inverter N7, which sets the output signal SW of the inverter N7, that is, the well voltage sensor VWBS to a low level. On the other hand, when the clock signal CP1 is set to the high level, the well voltage sensor VWBS has the MOSF
ETQN9 is turned on. At this time, the MOSFE
For TQP6 and QP7, the absolute value of the well voltage VWB is
VWB = VCC + 2 × Vthp, that is, it is selectively turned off under the condition that it is smaller than a relatively large predetermined value such as 6V. As a result, the internal node n4 becomes low level lower than the logic threshold level of the inverter N7, the output signal SW of the inverter N7, that is, the well voltage sensor VWBS becomes high level, and the boosting operation of the large capacity well voltage output circuit VWGL is performed. Be stopped. Note that Vthp in the above equation is P channel MO
It shows the threshold voltage of the SFET.

Next, the well potential leak circuit VWBL is
As shown in FIG. 8, a pair of inverters N9 and N1
A latch circuit in which 0s are cross-coupled, and a P-channel M for receiving the output signal of the latch circuit via two inverters N11 and N12 which are serially connected to their gates.
And OSFET QP8. The inverting output node n5 of the latch circuit, to which the output terminal of the inverter N9 and the input terminal of the inverter N10 are commonly coupled, has an N-channel MOSFET QN10 whose gate receives the internal control signal VCL.
Is coupled to the ground potential VSS via. The non-inverting output node n6, to which the input terminal of the inverter N9 and the output terminal of the inverter N10 are commonly coupled, is connected to the ground potential VSS via the N-channel MOSFET QN11 whose gate receives the inverted signal of the internal control signal VCL by the inverter N8. Be combined. MOSFET QP8 has its source coupled to well voltage supply point VWB and its drain coupled to power supply voltage supply point VCC. The inverter N8 uses the power supply voltage VCC as the operating power supply, while the inverters N9 to N12 use the well voltage VWB as the operating power supply for power supply voltage matching.

As a result of these, the inverters N9 and N10
When the pseudo static RAM is in the data retention mode and the internal control signal VCL is at the high level, the non-inverted output node n6 is at the high level, and the pseudo static RAM is in the normal operation mode. When the internal control signal VCL is set to the low level, the non-inverted output node n6 is selectively latched to bring it to the low level. The pseudo static RAM is set to the data retention mode and the inverter N
Non-inverting output node n of the latch circuit composed of 9 and N10
When 6 is set to the high level, the MOSFET QP8 is turned off, and the well voltage supply point VWB and the power supply voltage supply point VCC are separated. At this time, the large capacity well voltage output circuit VWGL and the small capacity well voltage output circuit V
The WGS is put into an operable state as described above. Therefore, the potential of the well voltage VWB is set to a relatively high level such as VCC + 2Vthp, or + 6V, as shown in FIG. On the other hand, pseudo static type R
AM is in normal operating mode and inverters N9 and N1
When the non-inverting output node n6 of the latch circuit consisting of 0 is set to the low level, the MOSFET QP8 is turned on, whereby the well voltage supply point VWB and the power supply voltage supply point VCC are short-circuited. At this time, the large capacity well voltage output circuit VWGL and the small capacity well voltage output circuit VW
The GS is deactivated, as described above. However, as shown in FIG. 9, the well voltage VWB at a relatively high level such as + 6V is not included in the MOSFET QP.
It is rapidly leaked to the power supply voltage VCC via 8 and has the same potential as the power supply voltage VCC.

That is, the well voltage generation circuit VWBG of this embodiment forms the well voltage VWB corresponding to the power supply voltage VCC and supplies it to the well region when the pseudo static RAM is in the normal operation mode. When the pseudo static RAM is in the data retention mode, a well voltage VWB having a relatively large absolute value such as + 6V is formed and supplied to the well region. At this time, the P-channel MOSFET formed in the well region
The threshold voltage of is increased by, for example, about 0.1 to 0.3 V. Such a change in the threshold voltage of FIG.
As is clear from 1, the effect of reducing the drain current of the P-channel MOSFET, that is, the subthreshold current by about 1 to 2 digits is produced, and thus the consumption current in the data retention mode of the pseudo static RAM depends on the ambient temperature. A few μA to a few hundred p
It will be reduced to about A.

By applying the present invention to a semiconductor device such as a pseudo static RAM having a data retention mode as shown in the above embodiment, the following operational effects can be obtained. That is, (1) a substrate voltage generating circuit for forming a predetermined substrate voltage and supplying it to a semiconductor substrate, and a well voltage generating circuit for forming a predetermined well voltage and supplying it to a well region in a pseudo static RAM having a data retention mode. Circuit, and when the data retention mode is designated, by selectively increasing the absolute values of the substrate voltage and the well voltage, the MOS included in the pseudo static RAM or the like is provided.
The effect that the threshold voltage of the FET can be selectively increased is obtained. (2) According to the above item (1), the subthreshold current of the MOSFET in the data retention mode can be reduced. (3) According to the above items (1) and (2), it is possible to reduce the current consumption of the pseudo static RAM in the data retention mode regardless of the ambient temperature.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the data retention mode of the pseudo static RAM may be designated by setting the chip enable signal CEB to the high level for a predetermined time or longer. Further, the substrate voltage generation circuit VBBG and the well voltage generation circuit VWBG can be divided into a plurality of parts and can be distributed and arranged on the semiconductor substrate. Pseudo-static type R
The AM can include only one of the substrate voltage generating circuit and the well voltage generating circuit. The pseudo-static RAM can have a so-called multi-bit configuration that inputs and outputs a plurality of storage data at the same time, and its block configuration and names and combinations of start control signals and internal control signals have various embodiments. sell.

2, FIG. 4, FIG. 5 and FIG.
Power supply voltage sensor VCCS, substrate voltage sensor V for normal operation
BSN, substrate voltage sensor for data retention VBSR
Also, the discrimination level of the well voltage sensor VWBS can be arbitrarily set by changing the number of MOSFETs in the diode form, and its specific configuration can take various embodiments. The substrate voltage generation circuit V shown in FIG.
The same applies to the block configuration of the BBG, the block configuration of the well voltage generation circuit VWBG shown in FIG. 6, and the specific configuration of the well potential leak circuit VWBL shown in FIG. The polarities and absolute values of the power supply voltage, the substrate voltage, and the well voltage, the conductivity type of the MOSFET, and the like are not limited by each embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the pseudo static RAM which is the field of use as the background has been described, but the present invention is not limited to this and, for example, a normal The present invention can be applied to various memory integrated circuit devices such as static RAM and dynamic RAM, and logic integrated circuit devices such as gate array integrated circuits. The present invention can be widely applied to semiconductor devices having at least a data retention mode.

[0047]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a substrate voltage generating circuit for forming a predetermined substrate voltage and supplying it to a semiconductor substrate in a pseudo static RAM or the like having a data retention mode,
A well voltage generating circuit that forms a predetermined well voltage and supplies it to the well region is provided, and when the data retention mode is specified, by selectively increasing the absolute values of the substrate voltage and the well voltage, a pseudo static type RAM
Since it is possible to selectively increase the threshold voltage of MOSFETs included in the above and to reduce the subthreshold current thereof, it is possible to reduce the current consumption in the data retention mode of the pseudo static RAM.

[Brief description of drawings]

FIG. 1 is a pseudo static RA to which the present invention is applied.
It is a partial block diagram which shows one Example of M.

FIG. 2 is a circuit diagram showing an embodiment of a power supply voltage sensor included in the pseudo static RAM shown in FIG.

3 is a block diagram showing an embodiment of a substrate voltage generating circuit included in the pseudo static RAM shown in FIG.

4 is a circuit diagram showing an embodiment of a normal operation substrate voltage sensor included in the substrate voltage generating circuit of FIG.

5 is a circuit diagram showing an embodiment of a data retention substrate voltage sensor included in the substrate voltage generation circuit of FIG.

6 is a block diagram showing an embodiment of a well voltage generation circuit included in the pseudo static RAM of FIG.

7 is a circuit diagram showing an embodiment of a well voltage sensor included in the well voltage generating circuit of FIG.

8 is a circuit diagram showing an embodiment of a well voltage leak circuit included in the well voltage generation circuit of FIG.

9 is a signal waveform diagram showing an embodiment of a substrate voltage generating circuit and a well voltage generating circuit included in the pseudo static RAM of FIG.

FIG. 10 is a general characteristic diagram showing the relationship between the gate-source voltage and the drain current of an N-channel MOSFET.

FIG. 11 is a general characteristic diagram showing the relationship between the gate-source voltage and the drain current of a P-channel MOSFET.

[Explanation of symbols]

PSRAM: Pseudo static RAM, LC ...
・ Internal logic circuit, TG ... Timing generation circuit, VC
CS ... Power supply voltage sensor, VBBG ... Substrate voltage generation circuit, VWBG ... Well voltage generation circuit. VBSN ... Substrate voltage sensor for normal operation, VBSR
..Substrate voltage sensor for data retention, VBGL
..Large-capacity substrate voltage output circuit, VBGS ... Small-capacity substrate voltage output circuit. VWBS ... Well voltage sensor, VWGL ... Large capacity well voltage output circuit, VWGS ... Small capacity well voltage output circuit, VWBL ... Well voltage leak circuit. QN1 to QN11 ... N-channel MOSFET, Q
P1-QP8 ... P-channel MOSFET, G1-
G2 ... Complementary gate, N1 to N12 ... Inverter,
OG1 ... OR gate, NAG1 to NAG2 ... NAND gate.

Claims (4)

[Claims] 1. A substrate voltage generating circuit for forming a predetermined substrate voltage and supplying it to a semiconductor substrate and / or a well voltage generating circuit for forming a predetermined well voltage and supplying it to a well region, wherein the substrate is in a data retention mode. A semiconductor device characterized in that the potential of a voltage and / or a well voltage is selectively deepened. 2. The semiconductor device comprises:
Alternatively, it includes a plurality of MOSFETs whose threshold voltage is selectively increased by increasing the potential of the well voltage, and the current consumption in the data retention mode is the threshold voltage of the plurality of MOSFETs. 2. The semiconductor device according to claim 1, wherein the semiconductor device is selectively made smaller by increasing. 3. The data retention mode is selectively designated by a combination of start-up control signals or a small absolute value of a power supply voltage. The semiconductor device according to claim 2. 4. The substrate voltage generation circuit is selectively operated in a normal operation mode, and selectively outputs its output signal when the absolute value of the substrate voltage becomes equal to or lower than a first predetermined value. A first substrate voltage sensor, and an output signal when the substrate voltage sensor is selectively operated in the data retention mode and the absolute value of the substrate voltage is less than or equal to a second predetermined value larger than the first predetermined value. And a second substrate voltage sensor for selectively validating an active state and a selectively operating state when the output signal of the first or second substrate voltage sensor having a relatively large current supply capability is valid. And a second substrate voltage output circuit which has a relatively small current supply capability and is in a steady operating state. The well voltage generating circuit comprises: , Data Lite Well mode sensor that is selectively activated in the operation mode and selectively validates its output signal when the absolute value of the well voltage becomes a predetermined value or less, and has a relatively large current supply capability. A first well voltage output circuit that is selectively activated when the output signal of the well voltage sensor is enabled in the data retention mode; and a first well voltage output circuit that has a relatively small current supply capability and is stationary in the data retention mode. And a well voltage leak circuit that selectively short-circuits the well voltage supply point and the power supply voltage supply point in the normal operation mode. The semiconductor device according to claim 1, claim 2, or claim 3.