JPH0628683A - Storage device - Google Patents

Abstract

PURPOSE:To prevent an access error due to the external force or the drop of power source voltage and to improve reliability by testing whether or not access is normally executed on a preliminarily set track and switching driving voltage corresponding to a target value given to a driving means in accordance with the result. CONSTITUTION:When an optical disk is actuated, the gain of a gain controller 18 is set at 1.0 and the access performance test of a track is executed. Data of target speed in address corresponding to the initial value of a track counter 14 is read from an IC memory 16 and a linear motor is driven. For every time when a beam spot crosses the track, the target speed data is read, and the mode is shifted to a tracking mode at the same time when the value of the track counter is zero, then the state of access is discriminated. At the time of abnormality, the set gain of the gain controller is decreased and acceleration at the time of the reduction of speed is decreased. Consequently, the speed of the linear motor can be followed to corresponding to the applying of the external force or the drop of the power source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device such as an optical disk device used as an external storage device of a computer.

[0002]

2. Description of the Related Art FIG.
FIG. 6 is a configuration diagram of an access control system of the conventional optical disc device described in No. 665 to 668 of the publication.

When recording / reproducing information written in the track of the optical disk 2 rotating on the disk motor 1 (hereinafter referred to as "tracking mode"), the light spot 3 which is the tip of the laser beam is positioned at the track center. So that the first switch 4 is turned on and the second switch
The switch 5 is set to the coupling compensation circuit 7 side, and the phase compensation circuit 6 and the coupling compensation circuit 7 control the linear motor 8 for moving the optical head 9 and the objective lens actuator 10 to adjust the position of the objective lens 11.

Next, when retrieving information (hereinafter referred to as "speed control mode"), when an access command is received, the first switch 4 is turned off and the second switch 5 is set to the speed control circuit 12 ₁ side. The speed control circuit 12 ₁ controls the speed of the linear motor 8.

FIG. 9 is a block diagram of a main part of the speed control circuit 12 ₁ . In the figure, 13 ₀ is a target speed generator, 14 is a track counter, 15 is a D / A converter, 16 is a non-volatile IC memory, and 17 ₁ is a CPU for controlling the entire optical disk device.

Data of the target speed corresponding to the number of remaining tracks obtained by subtracting the current track from the desired track is stored in advance in the nonvolatile IC memory 16 in correspondence with the address as shown in Table 1 below. Has been done.

[0007]

[Table 1] The relationship between the number of remaining tracks in Table 1 and the target speed is shown by the following equations (1) and (2).

When N> Nα Vr (N) = (2 × N × Lt × Kα) ^1/2 (1) When N ≦ Nα Vr = Vmax (2) Here, Nα is the deceleration start track and Vr ( N) is the target speed, N is the number of remaining tracks, Lt is the track pitch, Kα is the acceleration during deceleration, and Vmax is the maximum speed. First, C
The PU 17 ₁ sets the number of remaining tracks up to a desired track in the track counter 14 as an initial value, and the data of the address corresponding to this initial value is read from the nonvolatile IC memory 16 and the D / A converter 15 It is converted into an analog signal and output as the target speed.

Further, during speed control, the value of the track counter 14 is decremented by 1 each time one track of the light spot 3 is crossed by the track crossing signal, and the target speed is read from the nonvolatile IC memory 16 each time. Read and D
/ By A converter, the target speed generator 13 _0, for example, as shown in FIG. 10 (A), and outputs the containing constant speed section ramp target speed A.

Further, the speed control circuit 12 ₁ detects the moving speed of the light spot 3 by the linear motor 8 as a detection speed B, and the current amount of the linear motor 8 is set so that the detection speed B follows the target speed A. Is controlled as shown in FIG. 10 (B) to perform constant acceleration / deceleration up to a desired track, thereby shifting to the tracking mode with the linear motor 8 shifting speed to the tracking mode being substantially zero. Is.

The maximum speed Vmax of the above equation (2)
The higher the speed, the faster the access can be made. However, the speed detection of the linear motor 8 and the track crossing detection are limited by the performance of the device, so that the maximum speed that can detect these is not exceeded. It is necessary to set the maximum speed Vmax.

The theoretical current value I _LM of the linear motor 8 during deceleration is expressed by the following equation. I _LM = Kα × M / K _F (3) Here, Kα is the acceleration during deceleration, M is the mass of the linear motor moving part, and K _F is the thrust constant of the linear motor.

Further, the approximate value of the maximum current value I _{MAX that} can flow in the linear motor 8 is expressed by the following equation.

I _MAX ≈Vcc / R _LM (4) Here, Vcc is the power supply voltage, and R _LM is the resistance value of the linear motor 8.

Therefore, the linear motor 8 is set to the target speed A.
In order to follow the detection speed B of 1), it is necessary to set the acceleration Kα during deceleration so that the theoretical current value of the linear motor 8 does not exceed the maximum current value I _LM of the linear motor 8.

[0016]

However, in such a conventional example, in the speed control mode, as shown in FIG. 11 (A), an external force such as vibration or shock is externally applied to the optical disk device at the maximum speed. Is added, the detected speed B of the linear motor 8 deviates from the target speed A and a deviation occurs. When this deviation is large, the detected speed of the linear motor 8 exceeds the limit speed shown by the broken line. Therefore, speed detection and track crossing detection become impossible, and control becomes impossible, resulting in an access error.

When the power supply voltage is lower than usual, the maximum current value I _MAX of the linear motor 8 is decreased and the theoretical current value I during deceleration is decreased, as is clear from the above equation (4). _If it falls below _LM , current saturation will occur and the maximum acceleration of the linear motor 8 will decrease, resulting in
As shown in (A), the detected speed B of the linear motor 8 at the time of deceleration cannot follow the target speed A, and the transition speed to the tracking mode at a desired track point becomes a large value. Since the position of the lens 11 cannot be controlled, an access error will occur.

Therefore, the maximum speed V is set in advance by anticipating a decrease in external force such as external vibration or shock and a decrease in power supply voltage.
_{If the MAX} or the acceleration Kα during deceleration is set to a low value, the access time becomes long even at a normal power supply voltage.

The present invention has been made in view of the above points, and does not deteriorate the access time in a normal state, and does not cause an access error due to a decrease in external force or power supply voltage. With the goal.

[0020]

In order to achieve the above-mentioned object, the present invention is constructed as follows.

That is, the present invention according to claim 1 is
Read-out means for reading out information recorded on a track of a recording medium, drive means for moving the read-out means on the recording medium, and drive voltage applied to the drive means when a desired track of the recording medium is accessed. A speed control circuit for controlling the moving speed of the reading means, wherein the speed control circuit has a memory in which data corresponding to a target value of the moving speed is stored in advance; and the moving of the reading means. In a storage device having a target speed generator that reads out the corresponding data from the memory and outputs the data as the driving voltage in accordance with a track crossing signal obtained with the above, access to a preset track can be performed. Depending on the test means for testing whether or not it is normally performed, and whether the target speed generator It is provided a gain control means for controlling the amplification gain of the drive voltage to be output.

According to a second aspect of the present invention, a reading means for reading information recorded on a track of the recording medium, a driving means for moving the reading means on the recording medium, and a recording medium for the recording medium. And a speed control circuit for controlling a moving speed of the reading means by controlling a driving voltage applied to the driving means when accessing a desired track, the speed control circuit corresponding to a target value of the moving speed. A memory in which data is stored in advance, and a target speed generator for reading the corresponding data from the memory and outputting it as the drive voltage in accordance with a track crossing signal obtained by the movement of the reading means. In a storage device that has, a plurality of types of data corresponding to the target value are stored in the memory, and a preset track is stored. The test means access to test whether carried out correctly provided, the target speed generator,
According to the test result by the test means, any kind of data stored in the memory and corresponding to the plurality of kinds of target values is selected and read.

[0023]

According to the first aspect of the present invention, the test means tests whether or not the normal access is performed, and the test result corresponds to the target value output from the target speed generator. The amplification gain of the drive voltage is controlled, that is, the target value is switched according to the test result, so that the target value is switched when normal access is not performed due to an external force such as vibration or shock or a drop in the power supply voltage. As a result, the speed of the driving means can be controlled so that an access error does not occur.

According to the second aspect of the present invention, it is tested by the test means whether or not the normal access is performed, and the target speed generator is stored in the memory according to the test result. Select any type of data from the data corresponding to the type of target value to set the target value, that is, switch the target value according to the test result. When the normal access is not performed due to the decrease, the speed of the drive unit can be controlled by switching the target value so that the access error does not occur.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Example 1. FIG. 1 is a block diagram of an access control system of an optical disc device according to an embodiment of the present invention, and the portions corresponding to the conventional example of FIG. 8 are designated by the same reference numerals.

In the figure, 1 is a disk motor, 2 is an optical disk which is a recording medium, 3 is a light spot which is the tip of a laser beam, 4 is a first switch, 5 is a second switch, 6 is a phase compensation circuit, Reference numeral 7 is a coupling compensation circuit, 8 is a linear motor as a drive motor, 9 is an optical head as reading means attached to the linear motor 8, 10 is an objective lens actuator provided in the optical head 9, 11
Is an objective lens attached to the actuator 10, and 12 is a speed control circuit of the linear motor 8.

Next, the operation will be described.

When recording / reproducing information written in the track of the optical disc 2 rotating on the disc motor 1, the first switch 4 is turned on and the second switch is placed so that the light spot 3 is located at the center of the track. 5 to the coupling compensation circuit 7 side, and the phase compensation circuit 6 and the coupling compensation circuit 7
The position of the objective lens 11 is controlled by the linear motor 8 and the objective lens actuator 10 by.

Next, when searching for information, when the access command is received, the first switch 4 is turned off, the second switch 5 is set to the speed control circuit 12 side, and the speed of the linear motor 8 is set by the speed control circuit 12. Take control.

FIG. 2 is a block diagram of a main part of the speed control circuit 12, and parts corresponding to the conventional example of FIG. 9 are designated by the same reference numerals.

In the figure, 13 is a target speed generator, 1
4 is a track counter, 15 is a D / A converter, 16
Is a non-volatile IC memory, and 17 is a CPU that controls the entire optical disk device.

In the non-volatile IC memory 16, the data of the target speed corresponding to the number of remaining tracks obtained by subtracting the current track from the desired track is stored in advance corresponding to the address as in the conventional example described above. There is.

In this embodiment, in order to prevent the access time in a normal state from being deteriorated and to prevent an access error due to a decrease in external force or power supply voltage, the following structure is adopted.

That is, the target speed generator 13 has D /
A gain controller 18 that controls the output of the A converter 15, that is, the amplification gain of the drive voltage for the linear motor 8 is provided. Further, the CPU 17 that controls the entire optical disk device has a preset track, which is set when the device is activated. The embodiment has a function as a test means for performing an access performance test of whether or not a track deviated from the current track by 100 tracks is normally accessed, and the gain controller 1 is provided according to the test result.
8 is configured to be controlled. That is, the gain controller 18 and the CPU 17 constitute a gain control means.

Next, the operation of the optical disk device having the above configuration will be described with reference to the flowchart of FIG.

First, when the optical disk device is activated (step n1), the gain G of the gain controller 18 is set to 1.0 (step n2), and then it is determined whether or not 100 tracks are normally accessed. Access performance test is performed (step n3). That is, the CPU 17
The number of remaining tracks 100 is set as an initial value in the track counter 14, and the data of the target speed at the address corresponding to the value of the track counter 14 is stored in the nonvolatile IC memory 16
Is read out from, the D / A converter 15 converts it, and outputs it as a target speed via the gain controller 18. The linear motor 8 is driven according to this target speed.

As a result, every time the light spot 3 moves in the radial direction of the optical disk 2 and crosses a track, a track crossing signal is input to the target speed generator 13 and the value of the track counter 14 is decremented by one. . The target speed generator 13 outputs the target speed by reading the target speed data from the non-volatile IC memory 16 each time and performing D / A conversion.

At the same time when the value of the track counter 14 becomes 0, the mode is shifted to the tracking mode and it is judged whether or not the desired track can be accessed (step n).
4) When the access can be normally performed, the gain G of the gain controller 18 remains 1.0 and the subsequent access is performed with this gain.

On the other hand, when the access cannot be normally performed due to external impact or vibration or a drop in the power supply voltage, the gain G of the gain controller 18 is set to a value less than 1.0, for example, 0.8 (step n5). ), And subsequent access is performed with this gain.

In this way, when the access performance test does not allow normal access, the gain G of the gain controller 18 is changed to change the maximum speed Vmax after the change.
2 and the acceleration Kα2 during deceleration are as follows.

Vmax2 = Vmax × G (5) Kα = Kα × G (6) Therefore, when the gain G of the gain controller 18 is reduced, as shown in FIG. The acceleration of is smaller than that at normal time (G = 1.0) indicated by the one-dot chain line, and as shown by the arrow, even if external force such as vibration or shock is applied from the outside, the limit shown by the broken line There is sufficient margin for speed, and no access error occurs. Further, since the acceleration at the time of deceleration is set to be low even if the power supply voltage is reduced, the detected speed B of the linear motor 8 can be made to follow the target speed A, and an access error does not occur.

Incidentally, FIG. 4B also shows changes in the current of the linear motor 8.

Example 2. Figure 5 is a block diagram of a main part of the speed control circuit 12 ₀ in another embodiment of the present invention, the parts corresponding to the embodiment of FIG. 2, the same reference characters.

In the above-described embodiment, based on the result of the access performance test, the target speed is set with the gain G of the gain controller 18 being 1.0 in the normal state, and in the abnormal case,
While the target speed is set with the gain G of the gain controller 18 being less than 1.0, in this embodiment, the nonvolatile IC memory 16 ₀ has two types, that is, the results of the access performance test. Data of target speeds corresponding to normal and abnormal are stored in advance as tables 1 and 2, and either table is selected according to the result of the access performance test.

This table 1 is the same as the data of the above-mentioned table 1, and the table 2 is the data of the target speed with a reduced acceleration.

In this embodiment, as shown in the flow chart of FIG. 6, the CPU 17 ₀ , when the optical disk device is activated (step n1), as in the above embodiment.
An access performance test is performed (step n2), and as a result of the test, it is determined whether or not the access is normally performed (step n3). When the access is normal, the table 1 is selected (step n4), and subsequent access is performed. This is done based on the target speed data in Table 1. Also, in the event of an abnormality,
The table 2 is selected (step n5), and subsequent accesses are performed based on the target speed data in the table 2.

As described above, when the result of the access performance test is abnormal, since the table 2 which is the data of the target speed with the low acceleration is selected, the maximum acceleration of the linear motor 8 is decreased by the decrease of the power supply voltage or the external force. However, as shown in FIG. 7A, the detected speed B of the linear motor 8 can be made to follow the target speed A, whereby the transition speed to the tracking mode can be made almost zero. It is possible and no access error occurs. In addition, in FIG. 7A, a broken line C indicates a table 1
It shows the target speed by.

In each of the above-described embodiments, the access performance test is configured to be performed at the time of starting the optical disk device, but as another embodiment of the present invention, the access performance test is performed between the track access processing and the data read / write. You may comprise.

[0050]

As described above, according to the present invention, it is tested whether or not the preset track is normally accessed, and the drive corresponding to the target value given to the drive means according to the test result. Since the voltage can be switched, the access time in a normal state is not deteriorated, and an access error due to a decrease in external force or a power supply voltage can be prevented and reliability is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a main part of FIG.

FIG. 3 is a flowchart for explaining the operation.

FIG. 4 is a diagram showing a speed change and a linear motor current change at the time of track access in the embodiment of FIG. 1;

FIG. 5 is a block diagram of an essential part of another embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation.

7 is a diagram showing a speed change and a linear motor current change at the time of track access in the embodiment of FIG.

FIG. 8 is a configuration diagram of a conventional example.

FIG. 9 is a block diagram of a main part of a conventional example.

FIG. 10 is a diagram showing a change in speed and a change in current of a linear motor during track access in a conventional example.

FIG. 11 is a diagram showing a speed change and a current change of a linear motor when an external force is applied.

FIG. 12 is a diagram showing a speed change and a linear motor current change when the power supply voltage is reduced.

[Explanation of symbols]

2 optical disk 8 linear motor 9 optical head 12,12 ₁ speed control circuit 13,13 ₀ target speed generator 16,16 ₀ non-volatile IC memory 17, 17 ₀ , 17 ₁ CPU 18 gain controller

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[Procedure amendment]

[Submission date] November 26, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

When N < Nα Vr (N) = (2 × N × Lt × Kα) ^1/2 (1) When N ≧ Nα Vr = Vmax (2) Here, Nα is a deceleration start track, and Vr ( N) is the target speed, N is the number of remaining tracks, Lt is the track pitch, Kα is the acceleration during deceleration, and Vmax is the maximum speed. First, C
The PU 17 ₁ sets the number of remaining tracks up to a desired track in the track counter 14 as an initial value, and the data of the address corresponding to this initial value is read from the nonvolatile IC memory 16 and the D / A converter 15 It is converted into an analog signal and output as the target speed.

Claims (2)

[Claims] 1. A reading means for reading out information recorded on a track of a recording medium, a driving means for moving the reading means on the recording medium, and a driving means for accessing a desired track of the recording medium. A speed control circuit that controls a drive voltage applied to the reading means to control the moving speed of the reading means, the speed control circuit includes a memory in which data corresponding to a target value of the moving speed is stored in advance, and In a storage device having a target speed generator that reads out the corresponding data from the memory and outputs the data as the drive voltage in accordance with a track crossing signal obtained by the movement of the reading means, Depending on the test means for testing whether or not the track is normally accessed, and the test result by the test means, Storage device for gain control means for controlling an amplification gain of the drive voltage output from the speed generator, characterized in that the provided. 2. A reading means for reading information recorded on a track of a recording medium, a driving means for moving the reading means on the recording medium, and a driving means for accessing a desired track of the recording medium. A speed control circuit for controlling a driving voltage applied to the reading means to control a moving speed of the reading means, wherein the speed control circuit has a memory in which data corresponding to a target value of the moving speed is stored in advance, A memory device having a target speed generator that reads the corresponding data from the memory and outputs the data as the drive voltage in accordance with a track crossing signal obtained by the movement of the reading means. Indicates that multiple types of data corresponding to the target value are stored, and whether the preset track can be accessed normally. A test means for testing whether or not, the target speed generator, the target speed generator, in accordance with the test result by the test means, data of any kind of data corresponding to the plurality of kinds of target values stored in the memory A storage device characterized by being selectively read.