JPH06284337A - Digital clamping circuit for video signal - Google Patents

Abstract

PURPOSE:To accurately provide the reference level of video signals by simple constitution. CONSTITUTION:This clamping circuit 4a(4b) is provided with an OFL (OverFlowLimiter) circuit 31 for limiting signals not required for a clamping operation from the output of an A/D converter, a sampling circuit 32 for sampling the signals of an optical black part, an integrator 33 which is an LPF (Lowpass filter) for integrating and averaging the signals of the optical black part sampled in the sampling circuit 32 and generating error data and a subtractor 34 for turning the signals of the optical black part to '0' by subtracting the output of the integrator 33 and the output of the A/D converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal digital clamp circuit for clamping a signal of an optical black portion of a video signal from an image pickup device or the like.

[0002]

2. Description of the Related Art Conventionally, in a digital clamp circuit of a digital camera for imaging a subject, generating a video signal, A / D converting the video signal and performing digital signal processing,
The signal of the optical black portion of the A / D converted video signal is clamped, and a digital value is set with the clamped value as a reference. That is, in the digital clamp circuit, the digital value is set such that the average value of the signal of the optical black portion of the input video signal is 00h (h indicates a hexadecimal number).

[0003]

However, in the conventional digital camera, as shown in FIG. 11 (a), the noise component generated in the negative direction of the signal of the optical black portion is shown in FIG. 11 (b). As described above, the slice, that is, the signal around the optical black portion is half-wave rectified and A / D-converted, so that the average value of the signal in the optical black portion changes and the video signal is distorted.
In addition, the average value of the signal of the optical black part is 00h
As in the case of D
It is very difficult to control the C value and the reference voltage of the A / D converter.

In order to prevent the half-wave rectification of the noise component of the signal of the optical black portion, it is sufficient to offset the video signal before A / D conversion and then input it to the A / D converter. , There is a problem that the set value for setting the voltage to be offset before the A / D conversion is not uniquely determined due to the variation in the characteristics of the A / D converter. It is also difficult to accurately control the voltage generator that sets the offset voltage before A / D conversion.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital clamp circuit for a video signal capable of accurately obtaining the reference level of the video signal with a simple configuration. .

[0006]

A digital clamp circuit for a video signal according to the present invention comprises a sampling circuit 32 as a sampling means for sampling the signal level of an optical black portion of the video signal, and an optical black sampled by the sampling circuit 32. Integrator 33 as an average value calculating means for calculating error data as an average value of the signal level of the optical part, and a subtracter 34 as a subtracting means for subtracting the error data calculated by the integrator 33 from the signal level of the optical black part. It has and.

The video signal is a plurality of video signals R,
The sample circuit 32 includes R and G video signals.
It is possible to switch and input R and B video signals as at least two video signals of G and B video signals.

[0008]

In the digital clamp circuit for the video signal having the above-mentioned structure, the error data calculated by the integrator 33 by the subtractor 34 can be subtracted from the signal level of the optical black portion. It is possible to obtain the reference level of the video signal.

Since the sample circuit 32 can switch and input the R and B video signals as at least two video signals of the R, G and B video signals, a simpler reference level of the constituent video signal can be obtained. It becomes possible.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 10 relate to an embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of an embodiment of a digital signal processing circuit provided with a digital clamp circuit for video signals of the present invention, and FIG. 2 is a block diagram showing the configuration of the digital clamp circuit of FIG. 3, FIG. 3 is a circuit configuration diagram showing the configuration of the OFL circuit of FIG. 2, FIG. 4 is a circuit configuration diagram showing the configuration of the sample circuit of FIG. 2, and FIG. 6 is a circuit configuration diagram showing the configuration of the converter, FIG. 6 is a characteristic diagram showing the characteristic of the integrator of FIG. 5, FIG. 7 is a circuit diagram showing the configuration of the analog clamp circuit in the A / D conversion circuit of FIG. 1, and FIG. 5 is a circuit diagram showing an example of a concrete circuit of the integrator of FIG. 5, FIG. 9 is a circuit diagram showing an example of a concrete circuit of the G digital clamp circuit of FIG. 1, and FIG.
6 is a circuit diagram showing an example of a specific circuit of a B and C digital clamp circuit. FIG.

As shown in FIG. 1, the digital signal processing circuit provided with the digital clamp circuit for the video signal of the present embodiment is an image pickup signal from a three-plate type image pickup camera for picking up an image of a subject by separating it into RGB by a prism. Offset circuits 1a, 1b, 1c for offsetting a certain R signal, G signal, B signal by a predetermined offset voltage Vo and outputs of the offset circuits 1a, 1b, 1c are buffers 2a, 2
A / D converters 3a, 3b, 3 input via b, 2c
It has c.

The output of the A / D converter 3a is output to the digital clamp circuit 4a which is a digital clamp circuit of the video signal, and the outputs of the A / D converters 3b and 3c are output to the digital clamp clamp circuit 4b. . Further, the digital signal processing circuit performs white balance processing on the respective signals passed through the clamp circuits 4a, 4b, and white balance portions 5a, 5b, 5c, and signals from the white balance portions 5a, 5b, 5c to predetermined signals. Γ correction units 6a, 6b, 6 that perform γ correction with a fixed gamma (hereinafter, γ) characteristic
and c.

Each of the RGB signals that have been gamma-corrected by the gamma correctors 6a, 6b, and 6c is output to a luminance signal generator 7 that produces a luminance signal Y and a color difference signal generator 8 that produces a color difference signal. The color difference signal from the color difference signal generation circuit 8 is output to the hue signal generation circuit 9, and the hue signal generated by the hue signal generation circuit 9 generates a color signal C to be output to a monitor (not shown). Is output to. The brightness signal Y from the brightness signal generation unit 7 is output to the Δγ correction unit 11 that performs Δγ correction, and the brightness signal Y that is Δγ corrected by the Δγ correction unit 11 is output to a monitor brightness signal Y that is output to a monitor (not shown). It is output to the monitor luminance signal generation circuit 12 that generates'.

As shown in FIG. 2, the digital clamp circuit 4a (4b) includes an A / D converter 3a (3b, 3c).
OFL (Over Flow Limiter) circuit 31 for limiting a signal unnecessary for the clamp operation based on the output of the above, and a sample circuit 3 for sampling the signal of the optical black portion.
2, an integrator 33 which is an LPF (Low pass filter) for integrating and averaging signals of the optical black portion sampled by the sampling circuit 32 to generate error data, an output of the integrator 33 and an A / D converter 3a (3b, 3c)
And a subtractor 34 that subtracts the signal of the optical black portion to 0 by subtracting the output of the optical black portion.

Generally, an AGC (Auto Gai) of an image pickup camera is used.
n Contollor) output noise is 100 mV maximum gain
It is said that the signal of the optical black part is floated by about 50 mV and the A / D converter 3a (3b,
3c), noise in the vicinity of the optical black portion can be transmitted. For example, the A / D converter 3
If the specification of a (3b, 3c) is 2V / 10bit,
It becomes 2 mV per bit, and by allocating 20h as the center value of the optical black portion, noise of 3Fh or less in pp becomes unnecessary noise for the clamp operation. That is, when the input data has a word length of 10 bits, the upper 4 bits can be used as the OFL detection bits. Therefore, the OFL circuit 31, as shown in FIG. 3, has the non-polar upper 4 bits b of the word length of 10 bits.
An OR circuit 41 that takes an OR of it6 to bit9 and this O
It is composed of six OR circuits 42 which take the OR of the output of the R circuit 41 and the lower 6 bits bit0 to bit5 of the word length of 10 bits.

As described above, the sampling circuit 32 is provided to sample the signal of the optical black portion. However, as shown in FIG. 4B, the signal of the optical black portion has one horizontal synchronizing cycle. Since the signal is discretely output every (1H), the sampling circuit 32
As shown in FIG. 4 (a), the signal in the optical black portion is sampled and clamped by the clamp pulse during the discrete optical black portion, and the sampled signal is held in other periods with an enable. The latch circuit 51 of FIG.

The integrator 33 is composed of an LPF as described above. As shown in FIG. 5A, the integrator 33 has a delay circuit 61 with a delay amount of 2D (D is a predetermined delay amount) and a multiplier. 62 and a first-order IIR filter (In
finite impulse response digital filter: recursive digital filter 63
The transfer function H (s) of the IR filter 63 is H (s) = 1 / (1-a · Z ⁻¹ ) ... (1), the value of a does not match the digital value, and the DC gain does not become 0 dB. There are drawbacks such as.

Therefore, the integrator 33 of this embodiment has the configuration shown in FIG.
A modified IIR filter 66 including a delay circuit 64 having a delay amount of 2D and a multiplier 65 as shown in (b) is used. At this time, the transfer function H (s) is H (s) = b / {1 -(1-b) · Z ^-1 } ... (2).

Here, the frequency characteristics of the modified IIR filter 66 will be considered. First, the transfer function H of equation (2)
When the numerator of (s) is normalized to 1, H (z) = 1 / {K− (K−1) · Z ⁻¹ } (3) (K = 1 / b). Then,

[0020]

[Equation 1]

From this, the gain | H ^-1 | and the phase ψ can be expressed as follows, and the frequency characteristics thereof are shown in FIG. | H ⁻¹ | ² = 1 + 2K (K−1) (1-cos θ) (5) ψ = tan ⁻¹ [sin θ / {1+ (K−1) ⁻¹ −cos θ}] (6) Therefore, The 3 dB point is 2K (K-1) (1-cos θ) = 1 (7) Here, if θ <0.5, 2 (1-cos θ) ≈θ ²
And if K is sufficiently large, then θ = {K (K-1)} ^−1/2 = 1 / K = b (8)

Here, a quantitative consideration will be given to the analog characteristics of the video signal. The noise spectrum of the signal at the stage of sample-holding the analog video signal and performing AGC (auto gain control) includes a frequency-dependent noise component such as 1 / f and a white noise component such as optical shot noise. . Therefore,
Since the noise is not carried like the sync tip CLP of the VCR, the lower the cutoff of the LPF, the better, and it is preferable to absorb the noise in response to the noise of a certain frequency. Therefore, a method of realizing the above-described cutoff of the clamp circuit at the time of analog will be considered.

The analog clamp circuit 81 is constructed as shown in FIG. 7, and the transfer function H of the clamp circuit 81 is shown.
(S) is H (s) = 1 / {1 + sC (gm) ^-1 } ... (9) When gm = 1 / 260mho is substituted into this and frequency f is calculated, it will be f when C = 0.01u. = 61.2kH
When z, C = 0.1u, f = 6.12kHz, C = 1u
Then f = 612 kHz.

On the other hand, in the case of digital, θ = 2πfT (T
= Sampling period; 1/4 fSC) and θ = b from the equation (8), f θ (rad) b 61.2 kHz 0.026856 2 ⁻⁵ to 2 ⁻⁶ 6.12 kHz 0.0026856 2 ^{-8 to} 2 ^-9 612 kHz 0.00026856 2 ^-12 to 2 ^{-11 From} this result, if b = 2 ^-9 , which is a value according to C = 0.1u to C = 1u, is adopted, in the digital clamp circuit, A desired cutoff can be achieved.

FIG. 8 shows a concrete circuit of the sample circuit 32 and the integrator 33 in consideration of the result of the above quantitative analysis. In FIG. 8, for example, S.M. "S" of 6.0 is S
The sign bit (hereinafter, S bit) indicates that the data has polarity (Signed), and is “6.0”.
Indicates that this data consists of 6 bits (bit0 to bit5) and 0 bits below the decimal point.
It consists of bits. Reference numeral 100 denotes an S.S. signal which is shifted from the sample circuit 32 by 9 bits (indicated by symbols >> 9). 6.
9 is an inverter that inverts the data, and the output from this inverter 100 is input to the adder 101 of the integrator 33, and 1 (= H) is added to the carry in of the adder 101. This makes the polarity of the error data in the whole integrator 33 negative (-) by inverting the output + 1 and taking the complement of 2. This is because adding a negative error to the data of the optical black portion can reduce the circuit scale rather than performing "subtraction" with the data of the optical black portion. Further, in the integrator 33, the process of adding the new error and the circulating error is performed. Since the total of 16 bits, which is 6.9 data, is added, it is difficult to perform arithmetic processing in the 1D period.
In 3, the lower 8 bits are divided and the addition processing is performed by pipeline processing.

FIG. 9 shows a digital clamp circuit 4a having the above-mentioned specific circuit, and FIG. 10 shows a digital clamp circuit 4b. In FIG. 10, the digital clamp circuit 4b for R and B is multiplexed by the sample circuit 32 with bitID and then input to the integrator 33 to obtain error data and then demultiplexed in order to reduce the overall circuit scale. The plexing operation is performed with the data of the optical black portion so that the respective colors are not mixed in the integrator 33. Further, the G digital clamp circuit 4a is composed of one circuit, but the frequency characteristic of this circuit is equal to the frequency characteristic of the R / B digital clamp circuit 4b for multiplexing / demultiplexing. Is configured to be.

As described above, according to the digital clamp circuit of the video signal of the present embodiment, since the error of the signal of the optical black portion sampled by the sample circuit 32 is integrated by the integrator 33, it is calculated. The signal of the optical black part is not rectified by half wave like
An accurate average value of the optical black portion can be obtained, and deviation of the carry balance can be suppressed. Moreover, since the average value of the obtained optical black portion can be set to 00h, the arithmetic processing becomes easy. In addition, the analog video signal DC section and A / D converters 3a, 3b,
Since the average value of the optical black portion can be accurately obtained even with respect to the variation of the reference voltage of 3c, the circuit of the analog processing portion can be realized with a simple configuration.

[0028]

As described above, according to the digital clamp circuit for video signals of the present invention, the average value calculated by the average value calculating means by the subtracting means can be subtracted from the signal level of the optical black portion. With a simple configuration, there is an effect that the reference level of the video signal can be accurately obtained.

Since the sampling means can switch and input at least two video signals of the plurality of video signals, it is possible to obtain a simpler reference level of the constituent video signals.

[0030]

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital signal processing circuit including a digital clamp circuit for video signals according to the present invention.

FIG. 2 is a block diagram showing the configuration of the digital clamp circuit of FIG.

FIG. 3 is a circuit configuration diagram showing a configuration of the OFL circuit of FIG.

FIG. 4 is a circuit configuration diagram showing a configuration of the sample circuit of FIG.

5 is a circuit configuration diagram showing a configuration of the integrator of FIG.

6 is a characteristic diagram showing characteristics of the integrator of FIG.

FIG. 7 is a circuit diagram showing a configuration of an analog clamp circuit for explaining characteristics of the integrator shown in FIG.

8 is a circuit diagram showing an example of a specific circuit of the integrator of FIG.

9 is a circuit diagram showing an example of a specific circuit of the G digital clamp circuit of FIG. 1. FIG.

10 is a circuit diagram showing an example of a specific circuit of the R and B digital clamp circuits of FIG.

FIG. 11 is an explanatory diagram illustrating signal level detection of an optical black portion in a conventional example.

[Explanation of symbols]

 1a, 1b, 1c Offset circuit 2a, 2b, 2c Buffer 3a, 3b, 3c A / D converter 4a, 4b Digital clamp circuit 31 OFL 32 Sample circuit 33 Integrator 34 Subtractor

Claims (2)

[Claims] 1. A sampling means for sampling a signal level of an optical black portion of a video signal, an average value calculating means for calculating an average value of signal levels of the optical black portion sampled by the sampling means, and the average value. A digital clamp circuit for a video signal, comprising: a subtracting unit that subtracts the average value calculated by the calculating unit from the signal level of the optical black portion. 2. The video according to claim 1, wherein the video signal comprises a plurality of video signals, and the sampling means switches and inputs at least two video signals of the plurality of video signals. Signal digital clamp circuit.