JPH06284149A - Status sense system packet multiplexer - Google Patents

Abstract

PURPOSE:To allow the multiplexer to provide a function applying multiplex processing to input data on a virtual channel so as to discriminate the flexibility and priority. CONSTITUTION:The multiplexer is provided with an input RAM 1 storing inputted packet data and bit stream data, an output RAM 2 storing multiplexed output data, a RAM control section 3 controlling the input output RAM 1, and signal processor 4 monitoring the multiplexed performance of data of the input RAM 1 and an operation of RAM control, and also with a means setting a flag as soon as the write to the input RAM 1 is finished when data are multiplexed, a means resetting flags by the maximum number of input channels to report the end of write of the input RAM 1 to the signal processor 4, and a means processing data for the input RAM 1 whose flag is set with higher priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a status-sensing packet signal multiplexer using a single processor, and more particularly to CCSDS (to standardize the data transmission format between a spacecraft and a ground station using the packet system, It is a committee organized by major space development organizations, and a recommendation for standardization has been issued by this committee.) Corresponding transfer frame generators and other packet multiplexers.

[0002]

2. Description of the Related Art Heretofore, this type of apparatus has been configured only with hardware, and a dedicated circuit has been designed in accordance with specifications such as a data format and a data rate.

[0003]

In the conventional apparatus, when the multiplexing processing to the virtual channel is performed, the processing timing is determined for each type of data, so that the processing has flexibility. Was difficult. Further, it is difficult to change the data format, the bit rate, and the number of input signals because the design is hardened.

Further, since there is no circuit for judging the priority of data processing, the data rate of the output signal is set higher than the data rate of the input signal, so that the input at the critical timing is performed. , It was necessary to set it so that no data was missed. Therefore, inevitably, dummy data (Fill data; when data to be output has not been input yet, all 0s are used as a kind of dummy data that is inserted to maintain the output bit rate). However, there is a drawback that the transmission efficiency is reduced.

[0005]

A status sense packet multiplexer using a single processor according to the present invention includes an input RAM for holding input data and an output RAM for holding multiplexed output data. An input RAM, a RAM control unit that controls the output RAM, and a single processor that monitors the operation of the RAM control unit and the data multiplexing of the input RAM.

Further, in the present invention, when data is multiplexed, means for setting a flag at the same time when the writing of the input RAM is completed, and notifying the signal processor that the writing of the input RAM is completed. A means for setting a flag to be output for the purpose of the maximum number of input channels, and an input RAM in which a flag processor is set to identify this state by software.
And a means for processing the data in order from the highest priority.

According to the present invention, there is no omission of data,
It is possible to realize high transmission efficiency while suppressing the insertion of dummy data. Further, since the change in the number of input signals, the data format, the bit rate and the like can be dealt with by changing the software inside the signal processor, it is possible to design with flexibility.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a system diagram of an embodiment of the present invention. Four data with different data rates are asynchronously input from the external interface. Of these, the PCM telemetry signal 1 and the PCM telemetry signal 2 are input as bit stream data. The CCSDS source packet 1 and the CCSDS source packet 2 are input as packet data. The four data are written into the input RAM 1 via the input buffer 7 and the register 8 provided for each input. Two input RAMs 1 are provided for each data. This is because one RAM is
This is because the other RAM is in a data transfer state.
However, in the case of CCSDS source packet 2 (image data), three RAMs 1 are provided. This is because the image data is input at a very high speed, and therefore it is necessary to secure a sufficient time for the single processor 4 to process the data (time for the input RAM 1 to enter the data transfer state).

When the writing of data to the input RAM 1 is completed, the input RAM control section 3 sets a flag for notifying the single processor 4 that the writing of the input RAM 1 is completed, and at the same time outputs a control signal. And input R
The AM1 is switched (switching between the write mode and the transfer mode). The single processor 4 receives the processing request from the output RAM control unit 9 and monitors the write completion state of the input RAM 1. At this time, the single processor 4 has the flag set (in the write completion state) for the input RAM
In order to transfer the data No. 1 to the output RAM 2, a data transfer start signal is sent to the RAM control unit 3 via the function select bus 5. Upon receiving this signal, input R
While the data transfer from the AM1 to the output RAM2 is being performed via the data bus 6, the signal processor 4 creates an ID for multiplexing to the virtual channel, and at the same time when the data transfer is completed, the data is transferred to the output RAM2. The ID is transferred via the bus 6 and multiplexed on the virtual channel.

The output data written in the output RAM 2 receives the control signal from the output RAM control unit 9 and is output to the external interface as a packet signal multiplexed on the virtual channel. At the same time, the output RAM control unit 9
In response to the control signal from, the output RAM 2 is switched (switching between the write mode and the transfer mode).

The above description is an example of the simplest processing.
If a plurality of flags in the input RAM 1 are set, the single processor 4 performs the processing sequentially from the one with the highest priority. Therefore, it is possible to realize high transmission efficiency without missing data. When the number of input signals increases (eg, 4CH → NCH), the data multiplexing process can be handled by changing the software inside the signal processor.
The register 8 and the input RAM 1 can be easily expanded by adding (N-4) CH.

[0012]

As described above, since the present invention employs the signal processor, the flexibility of the multiplexing process to the virtual channel, the change of the data format, the change of the bit rate, and the change of the number of input signals are realized. It is designed to be flexible to changes. Further, by adopting the signal processor, there is an effect that a high transmission efficiency can be realized even when handling a plurality of data.

[Brief description of drawings]

FIG. 1 is a system diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Input RAM 2 Output RAM 3 Input RAM Control Unit 4 Signal Processor 5 Function Select Bus 6 Data Bus 7 Input Buffer 8 Register 9 Output RAM Control Unit 10 Timing Signal Generation Unit 11 SYNC Generation Unit 12 Register 13 Output Buffer

Front page continuation (72) Inventor Kihiko Sakamaki 2-4-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa NEC Electric Aerospace Systems Co., Ltd. (72) Inventor Tatsu Narita 4-4-1 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa No. 18 inside NEC Aerospace Systems Co., Ltd.

Claims (2)

[Claims] 1. By adopting a signal processor and adding an ID as a label for identifying the input data to a plurality of types of digital data from different sources such as input packet data and bit stream data. In a status-sensing packet multiplexer that multiplexes into a virtual channel, which is a method of sending different data through one transmission channel, holds an input RAM that holds input data and a multiplexed output data Output RAM and input RA
A status-sensing packet multiplexer including a RAM controller that controls M and an output RAM, and a signal processor that multiplexes data read from an input RAM and monitors the operation of the RAM controller. 2. When multiplexing data, a means for setting a flag at the same time when the writing of the input RAM is completed, and a flag for notifying a single processor that the writing of the input RAM is completed 2. The apparatus according to claim 1, further comprising means for setting the number of input channels, and means for recognizing this state by software inside the single processor and processing the data of the input RAM in which the flag is set from the highest priority. Status-based packet multiplexer.