JPH06276516A - Data processor - Google Patents

Abstract

PURPOSE:To allow the unskillful user to use the processing unit easily by switching the display of an input picture after awaiting a reply from a talking object after display switching data are sent to the talking object so as to avoid unmatching between the input picture and a line drawing. CONSTITUTION:A system controller of a video conference equipment sends a document control request command REQA to a talking object AI when the user commands document picture display changeover to await the entry of a reply command ACK to the command REQA from the talking object AI. Then the controller revises picture data based on line drawing data entered from the talking object AI for a wait time T1 and displays it onto a document picture. Then the controller receives the command ACK and switches the display of the input picture. Thus, dissidence between the input picture and the line drawing when the input picture is switched is avoided and the use of the unskillful user is facilitated.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. BACKGROUND OF THE INVENTION Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1, 2, 5, 6 and 9) Action (FIGS. 1, 2, 5, 5) 6 and FIG. 9) Embodiment (1) Overall configuration (FIG. 1) (1-1) Processor (FIG. 2) (1-2) Bus controller (FIGS. 7 to 9) (1-3) Telelighting control ( 2, 5, 6, 10 to 15) (1-4) Image data processing (FIGS. 16 to 30) (1-5) Data transmission (FIGS. 31 to 52) (2) Embodiment Effects (3) Other Examples Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
For example, the present invention can be applied to a video conference device that compresses image data and transmits the data together with audio data.

[0003]

2. Description of the Related Art Conventionally, in a video conference apparatus, by transmitting and receiving audio data, image data and the like with a desired transmission target, it is possible to achieve communication with a communication target at a remote place. Has been done
-245889 publication).

That is, this type of video conference apparatus obtains a picked-up image of a person who attends a conference through a predetermined image pickup apparatus, fetches the picked-up image, compresses the data, and then sends the image to a call target. Further, the video conference device sends the voice signal of the attendee together to the call target, and at the same time, expands the image data coming from the call target and displays it on a predetermined display device.

Further, the video conference apparatus sends line drawing data input via a tablet or the like to a call target in response to a user's operation, and instead, a still image input via an image scanner or the like is sent. Send to the call target. For this reason, the conventional video conferencing apparatus is installed in a dedicated video conferencing room or the like and is used by connecting a line such as an optical fiber with a call target so that a large amount of data can be transmitted and received. Was there.

[0006]

By the way, if this type of video conference apparatus can be carried as needed and used freely in a place other than the video conference room, the usability of this type of video conference apparatus can be improved. Profitable and considered convenient. Further, the field of application of this type of video conference apparatus can be expanded.

For this purpose, this type of video conferencing apparatus is used not only for a dedicated optical fiber line but also, for example, a popularized service integrated digital communication network (ISDN: integrated).
service digital network). Further, not only can this type of line be connected, but the overall configuration must be simplified. Furthermore, the operation of the device itself is simplified, and not only a dedicated operator,
It is necessary that even a user unfamiliar with the operation can easily perform the operation.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a data processing device such as a video conference device which can be easily carried by being carried outside the video conference room.

[0009]

In order to solve such a problem, in the present invention, in a data processing apparatus 1 for displaying the same input image with a predetermined call target AI and displaying a line drawing together with the input image, A screen storage unit 40 for storing the call target AI or an input image input through a predetermined image input unit 15, and line drawing data DW from the call target AI.
To display the line image together with the input image, the image switching information input unit 6 for inputting the display switching data REQA for switching the display of the input image, and the display switching data REQA for the call target. A switching data transmitting means 48 for transmitting and display switching means 41, 46 for switching the display of the input image based on the image switching data REQA are provided, and the display switching means 41, 46 set the display switching data REQA to the call target AI. After the transmission, when the response ACK is obtained from the call target AI, the display of the input image is switched.

Further, in the second invention, in the data processing apparatus 1 for displaying the same input image with a predetermined call target AI and displaying a line drawing together with the input image, the call target AI or predetermined image input means. An image display unit 4 for inputting line drawing data DW from a predetermined line drawing data input unit 17, 46 and a screen storage unit 40 for storing an input image input via 15.
2, 43, 44, line drawing data sending means 46, 48 for sending the line drawing data DW to the call target AI, and the call target A
Display switching means 4 for switching the display of the input image based on the display switching data REQA input from I.
1, 46, and the line drawing data sending means 46, 48,
When the display switching data REQA is input from the call target AI, the transmission of the line drawing data DW to the call target AI is stopped, and the data A that responds to the display switch data REQA.
Send CK.

Further, in the third aspect of the invention, the line drawing data inputting means 17, 46 stops the line drawing data sending means 46, 48 from sending the line drawing data DW, and then the line drawing data D.
The input of W is stopped, and the line drawing data sending means 46, 48
After the transmission of the line drawing data DW is stopped, the transmission of the line drawing data DW is resumed when a predetermined period T2 has elapsed, and the line drawing data inputting means 17 and 46 are the line drawing data transmitting means 46 and 48.
When the transmission of the line drawing data DW is restarted, the input of the line drawing data DW is restarted.

Further, in the fourth invention, the display switching means 41, 46 switches the display of the input image by enlarging, reducing, scrolling or rotating the input image based on the display switching data REQA.

[0013]

When the response ACK is obtained from the call target AI after the display switching data REQA is sent to the call target AI, the display of the input image is switched so that the original ACK is obtained until the response ACK is obtained. A line drawing image can be correctly displayed on the input image.

Further, when the display switching data REQA is input from the call target AI, the transmission of the line drawing data DW to the call target AI is stopped and the display switch data REQA is stopped.
By sending the data ACK in response to, the line drawing image can be correctly displayed on the original input image in the call target AI.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall Configuration In FIG. 1, reference numeral 1 denotes a video conference apparatus as a whole,
The processor 3 is stored in a predetermined storage base 2, the monitor device 4 is disposed on the storage base 2, and the imaging unit 5 is disposed on the monitor device 4. As a result, the video conference apparatus 1 images the attendees of the conference lined up in front of the monitor apparatus 4 by the image pickup unit 5, processes the video signal obtained by the image pickup by the processor 3, and sends the video signal to the call target in the form of a moving image. Further, the image data of the moving image transmitted from the call target is received by the processor 3 and displayed on the monitor device 4.

Further, the video conferencing apparatus 1 includes a processor 3
A printer is connected to the printer so as to be able to output the image transmitted from the call target, and the image scanner and the document image pickup device are further connected to the processor 3 to input a binary image (hereinafter referred to as a binary image). A document image) and a color still image (hereinafter referred to as a natural image) can be sent to the call target. Further, as in the case of image data, the video conference device 1 modulates / demodulates an audio signal via the processor 3 and transmits / receives it to / from a call target,
The audio signal is directly input / output to / from an external device, and the audio signal is transmitted / received between the image pickup unit 5 and the remote commander 6.

The audio signal transmitted / received between the image pickup section 5 and the remote commander 6 is transmitted / received via the infrared ray L1.
A microphone 8 is connected to the microphone 8 to collect the voice of the attendees of the conference, and the voice of the call target can be monitored via the speaker provided in the remote commander 6. Further, the video conference device 1 transmits and receives a remote control signal for the processor 3 and the image pickup unit 5 between the image pickup unit 5 and the remote commander 6 in addition to this audio signal, thereby operating the remote commander 6 to operate the monitor unit 4. By selecting the menu displayed on the lower part of the display screen, the entire operation mode, the magnification of the image pickup unit 5, and the like can be switched. As a result, the video conference apparatus 1 can switch the operation mode and the like by a simple operation, and can improve the overall usability.

Further, in this embodiment, the remote commander 6 is adapted to be able to connect a tablet, and sends the two-dimensional coordinate data inputted via this tablet to the image pickup section 5, and the image pickup section 5 receives this coordinate data. Is output to the processor 3. As a result, the video conference device 1 can send the line drawing data input by operating the tablet to the call target and can monitor the line drawing data as needed.

(1-1) Processor As shown in FIG. 2, the processor 3 inputs the video signal SV input through the image pickup section 5 to the image input / output section 10,
Here, the video signal SV is converted into a digital signal to generate a digital video signal, and the digital video signal is compressed by the encoder / decoder unit 11. In this process, the encoder / decoder unit 11 uses the CCIT
T (comite consultaif international telegraphique
et telephoniqe), H. This digital video signal is data-compressed according to the format specified in H.261.
The image data D1 obtained as a result is output to the main processing unit 12. As a result, the video conference apparatus 1 can efficiently transmit the image pickup result of the image pickup unit 5 in the form of a moving image.

On the other hand, among the image data transmitted from the call target through the line L, CCITT, H. 261
The image data D1 of the moving image compressed according to the format specified in the
The data is input to the decoder unit 11, subjected to data decompression processing here, converted into a video signal SVO by the image input / output unit 10, and output to the monitor device 4.

On the other hand, when a document image is captured by the document image capturing device 13 and the captured image is transmitted, the processor 3
After the video signal output from the document image pickup device 13 is converted into a digital video signal by the image input / output unit 10, the image data processing unit 14 compresses the data and sends it from the main processing unit 12 to the call target. As a result, the video conference device 1 can input a natural image through the document image capturing device 13 and can transmit the natural image to the call target as necessary.

At this time, the image data processing unit 14 compresses the natural image captured by applying the data compression method of a predetermined format (JPEG: joint photgraphic experts group) defined for the still image, and the result is obtained. The image data D2 is sent to the call target via the main processing unit 12.

On the other hand, the processor 3 inputs the image data of the document image to the image data processing unit 14 when transmitting the document image input via the image scanner 15 to the object of communication, and here, regarding the facsimile, Data compression is performed according to the specified processing procedure.
Furthermore, the video conference apparatus 1 sends the compressed image data D2 to the call target through the main processing unit 12, so that the video conference apparatus 1 can efficiently transmit the document image as well. There is.

On the other hand, the image data processing unit 14 receives the image data D2 via the main processing unit 12 when the image data of the natural image and the document image is transmitted from the communication object and decompresses the original data. After reproducing the image, the image is output to the printer 16 in response to the user's operation, and is also converted into a digital video signal and output to the image input / output unit 10, where it is converted into a video signal and output to the monitor device 4. To do. As a result, the video conference device 1 can monitor the natural image and the document image transmitted in the form of a still image from the call target on the monitor device 4 instead of or in addition to the video of the call target, Further, it can be outputted to the printer 16 as required.

In a series of processing in which the natural image and the document image are further captured and data is compressed, the image data processing unit 14 monitors the natural image and the document image via the image input / output unit 10 in a series of processes. The video conferencing apparatus 1 can monitor the natural image and the document image captured as needed. Further, when the monitor device 4 monitors the natural image and the document image transmitted / received to / from the call target, the image data processing unit 14
The image of the line drawing input via the tablet 17 can be displayed so as to be superimposed on the natural image and the document image, whereby processing such as drawing can be executed on the display screen of the document image and the natural image. ing.

That is, the main processing unit 12 connects the tablet 17 to the remote commander 6 so that the transmitting / receiving unit 1
The coordinate data can be taken in through 9. Further, the main processing unit 12 sends this coordinate data to the call target in the form of line drawing data DW. Furthermore, the main processing unit 1
2 reproduces the image of the line drawing input by the user on the tablet 17 based on this line drawing data DW, and then outputs this image data from the image data processing unit 14 to the image input / output unit 10 in the form of a digital video signal, Here, it is superimposed on the natural image and the document image and displayed on the monitor device 4.

As a result, the video conference apparatus 1 can monitor the same document image or natural image as the call target and input line drawings or the like on the document image or natural image to perform communication. (That is, telewriting)

Further, in the processor 3, the audio processing unit 18 processes an audio signal directly input / output with an external device and an audio signal input / output with the transmission / reception unit 19. That is, the video conference apparatus 1 receives the infrared ray L1 transmitted from the remote commander 6 by the transmission / reception unit 19 built in the imaging unit 5, and demodulates the audio signal and the control command here.
The audio processing unit 18 inputs the audio signal SA received by the transmitting / receiving unit 19 and the audio signal directly input from the external device in the digital signal format, and the CCITT, G. 7
11 and G.I. The data is compressed according to the format defined in 722 and then output to the main processing unit 12.

Further, the audio processing section 18 receives the audio data transmitted from the callee side via the main processing section 12, decompresses the audio data and outputs it to the transmitting / receiving section 19 and directly to an external device. As a result, in the video conference apparatus 1, the microphone 8 can be simply connected to the remote commander 6 to talk with the call target without connecting a cable to the processor 3 one by one.

The main processing unit 12 receives the image data and audio data input in this way as CCITT, H.264, and H.264 data. Two
The data transmitted according to the format specified in No. 21 to the call object and the data transmitted from the call object according to the format are separated into image data, audio data, etc., and output to each circuit block. That is, in this embodiment, the processor 3 has a connector for optical fiber connection and a connector for connection of the integrated service digital communication network on the back surface, which allows 384 [kb] through the optical fiber.
ps] lines (ie, consisting of H ₀ channels) up to 2
Connected to a line, and a line of 1536 [kbps] or 1920 [kbps] (that is, H ₁₁ and H ₁₂ channels)
INS network 64 (information network system net 64)
) 64 [kbps] lines can be connected at the same time within a range from 2 lines to a maximum of 6 lines to make a call.

The main processing section 12 inputs / outputs data to / from a communication object via the line L, and at the same time, the transmission / reception section 19
A control command is output to the bus BUS in response to a control command input from the control unit and a control command DC transmitted from the call target, whereby the operation of each circuit block can be switched as needed. That is, the encoder / decoder unit 11, the image data processing unit 14, and the audio processing unit 18 switch their operations in response to a control command output from the main processing unit 12 via the bus BUS, whereby the video conference apparatus 1 is The display image on the monitor device 4 can be switched as necessary, and the type of data to be transmitted to the call target can be switched.

In response to the transmission of this control command, the processor 3 includes the main processing unit 12 and the encoder / decoder unit 1.
1. Image data and audio data input / output to / from the image data processing unit 14 and the audio processing unit 18 are input / output via a dedicated connection line, thereby performing a series of data compression at a high speed. It can be processed.

(1-1-1) Image Input / Output Unit As shown in FIG. 3, the image input / output unit 10 inputs the NTSC video signal SVI from the image pickup unit 5 and the document image pickup device 13 to the decoder 20. Here, it is converted into a luminance signal and a color difference signal. Analog digital conversion circuit (A / D) 2
1 converts the luminance signal and the color difference signal into a digital signal, and then, through a matrix circuit 22, an encoder /
It is output to the decoder unit 11 or the image data processing unit 14.
As a result, the image input / output unit 10 causes the image pickup unit 5 to operate as necessary.
The image data of a moving image can be captured from the image capturing device 13 and the image data of a natural image can be captured from the document image capturing device 13.

Further, the image input / output unit 10 receives from the encoder / decoder unit 11 the matrix circuit 22 the moving image data D _V transmitted from the call target and the menu image data D _ME to be displayed on the monitor device 4, and The image data D _MA output from the image data processing unit 14 is received by the matrix circuit 22, and the output data of this matrix circuit 22 is converted into a digital analog conversion circuit (D / A) 2
Output to 3. In this case the matrix circuit 22, the image data D _V in response to operation of the user, D _ME, and selects and outputs the D _MA, and these image data D _V, D _ME, selectively synthesized to output D _MA To do.

The digital / analog conversion circuit 23 converts the image data into a luminance signal and a color difference signal which are analog signals, and the luminance signal and the color difference signal are encoded by the encoder 25.
Then, it is converted into an NTSC video signal SVO and output to the monitor device 4. Accordingly, the image input / output unit 10 can display attendees and the like of the call together with the menu when the image data D _{V of the} moving image and the image data D _{ME of the} menu transmitted by the matrix circuit 22 are selected. It is done like this.

Alternatively, in the matrix circuit 22, when the image data D _MA output from the image data processing unit 14 is selected together with the image data D _ME , the image input / output unit 10 causes the image input / output unit 10 to transmit the natural data transmitted from the call target. The image, the document image, and the natural image and the document image captured by the video conference apparatus 1 can be displayed together with the menu, and the document image can be displayed together with the line drawing image as required. .

Further, when the user selects the sub-screen display mode, the matrix circuit 22 outputs the image data selected for the sub-screen to the digital / analog conversion circuit 23 via the sub-screen creating circuit (PINP) 24. As a result, the video conference apparatus 1 can display a small child screen on the main display screen as needed to monitor, for example, a moving image and a document image, or a moving image and a natural image at the same time. .

Alternatively, the image input / output unit 10 selects the image data D _ME by the matrix circuit 22 at the time of rising after the power is turned on, so that the initial screen is displayed and the selectable menu is displayed. Has been done. In this embodiment, the image input / output unit 10 includes the decoder 2
The video signal input to 0 can be directly output to the monitor device 4, so that the imaging result of the imaging unit 5 can also be monitored.

(1-1-2) Encoder / Decoder Unit and Audio Processing Unit As shown in FIG. 4, the audio processing unit 18 uses the echo canceller 27 to process the audio signal SA input from the transmitting / receiving unit 19 or an external device. After being converted into a digital signal, the audio data processing circuit 28 performs CCITT, G.D. 711 and G.I. The data is compressed according to the format defined in 722 and output to the main processing unit 12. Further, the audio processing unit 18 receives the audio data DA output from the main processing unit 12 in the audio data processing circuit 28, where the audio data DA is decompressed to restore the original audio data, and the echo data DA is restored. The signal is converted into an analog signal via the cera 27 and output.

At this time, the echo canceller 27 temporarily stores the audio data to be transmitted to the call target in a predetermined data storage means, delays it, and subtracts it from the audio data coming from the call target. As a result, the echo generated when transmitting and receiving a voice signal using a geostationary satellite is reduced.

On the other hand, the encoder / decoder section 11
Receives the image data D _V of the moving image picked up by the image pickup unit 5 into the image conversion circuit 29 via the image input / output unit 10, and performs image conversion processing here. In this image conversion processing, the image conversion circuit 29 converts the image data D _V formed in the format of the luminance signal and the color difference signal at the horizontal scanning line number and frame frequency of NTSC format into the horizontal scanning line number 280.
Book, image data D whose basic frame frequency is 30 [Hz]
_It is converted to _CIF, and _H.264 The image data D _CIF to be processed defined by _H.261 is generated. On the other hand, the encoder / decoder 30 sends this image data D _CIF to H.264.
Data is compressed according to the format defined by H.261, and the resulting image data is output to the error correction circuit 31 to which an error correction code is added and then output to the main processing unit 12.

As a result, the video conference unit 1 has the image pickup unit 5
CCI for moving image data input via
The H.264 standard specified in the TT recommendation. Data is compressed according to the H.261 format. Further, the error correction circuit 31 receives the image data D1 sent from the call target from the main processing unit 12, performs error correction processing, and outputs it to the encoder / decoder 30, and the encoder / decoder 30 outputs this image data D _CIF as data. Image conversion circuit 29 by expanding
Output to.

The image conversion circuit 29 receives the image data D
By interpolating the _CIF , the number of horizontal scanning lines and the frame frequency of this image data D _CIF is set to N contrary to the time of transmission.
The number of horizontal scanning lines and the frame frequency of the TSC format are converted and output to the image input / output unit 10. As a result, the video conference device 1 is set to H.264. Image data of a moving image transmitted according to the H.261 format can be monitored.

The menu plane 32 is formed by a memory circuit that stores image data, and is connected from the main processing unit 12 to the bus B.
The stored image data D _ME is selectively output to the image input / output unit 10 in response to a control command input via the US, whereby the video conference device 1 displays the display screen of the monitor device 4 as necessary. A selectable menu can be displayed on the remote commander 6.

(1-1-3) Image Data Processing Unit As shown in FIG. 5, the image data processing unit 14 connects the local bus LBU to the bus BUS via the bus controller 35.
S is connected, and the processor 3 connects the main processing unit 12 to this bus BUS. On the other hand, the image data processing unit 14
On the local bus LBUS, a still image processing circuit 36, a binary image processing circuit 37, an image interface circuit (image I
The F circuit) 38 and the interface circuit (IF) 39 are connected.

As a result, when the control command is input to the local bus LBUS from the main processing unit 12 via the bus controller 35, the image data processing unit 14 disconnects the local bus LBUS from the bus BUS, and thereby the still image processing is performed. Circuit 36, binary image processing circuit 37, image interface circuit 38, interface circuit 39
Can independently access the arithmetic memory 40 and execute predetermined data processing.

That is, the interface circuit 39 uses the S
The data input / output circuit is a CSI (small computer system interface) system, and image data of a document image input via the image scanner 15 is sequentially input and stored in the arithmetic memory 40 and stored in the arithmetic memory 40. Image data such as a document image is output to the printer 16.

The binary image processing circuit 37 includes the controller 4
By driving 1 to access the arithmetic memory 40, the image data of the document image stored in the arithmetic memory 40 is data-compressed according to the format specified for the facsimile and the resulting image data is the image interface circuit. Output to 38.

On the contrary, the binary image processing circuit 37
Sequentially fetches the image data of the call target side output from the image interface circuit 38 and decompresses the data, thereby decompressing the image data of the document image that is data-compressed and transmitted, and calculates the decompressed image data. It is stored in the memory 40.

On the other hand, the still image processing circuit 36 compresses the image data of the natural image stored in the arithmetic memory 40 by applying the data compression method defined for the natural image, and the result is obtained. The image data is output to the image interface circuit 38. On the contrary, the still image processing circuit 36 takes in the image data of the call target from the image interface circuit 38, decompresses the data, and thereby restores the compressed image data of the transmitted natural image and calculates it. It is stored in the memory 40.

As a result, the video conference apparatus 1 uses the arithmetic memory 40 by switching between the natural image and the document image, and compresses and decompresses the natural image and the document image.

The image interface circuit 38 inputs and outputs the image data D2 of the natural image and the document image between the still image processing circuit 36, the binary image processing circuit 37 and the main processing section 12, and at this time, the communication procedure By inputting / outputting the image data D2 according to the protocol, the image data D2 is retransmitted in response to the retransmission request sent from the call target. Further, the image interface circuit 38 adds the restart marker code or the like necessary for the determination of the resend request to the main processing unit 12 with the image data D2 added, and further, regarding the image data D2 coming from the call target, This restart marker code is detected and a retransmission request is output if necessary.

The controller 41 includes the still image processing circuit 3
6, the operation memory 4 according to the request of the binary image processing circuit 37
0 is controlled so that desired image data can be input / output between the still image processing circuit 36, the binary image processing circuit 37 and the arithmetic memory 40. Further, the controller 41 switches the operation in response to a control command input from the main processing unit 12 via the bus BUS, whereby the image data of the arithmetic memory 40 is converted into an image FIFO (first in first out) 42 formed by a memory circuit. A natural image, a document image or the like, which is output to the image input / output unit 10 via the, and stored in the arithmetic memory 40, can be monitored.

The image input / output unit 1 receives this document image and the like.
When outputting to 0, the memory controller 41 switches the address data in response to the control command output from the main processing unit 12 to generate the desired data such as the document image stored in the arithmetic memory 40. Is displayed at a magnification of 1, and further scrolled and rotated to be displayed on the monitor device 4. As a result, the video conference apparatus 1 can freely switch the display of the document image and the like in response to the control command transmitted from the call target and further in response to the operation of the remote commander 6 by the user.

The image input / output unit 1 receives this document image and the like.
When outputting to 0, the image FIFO 42 outputs image data via the matrix circuit 43, and the matrix circuit 43 outputs the image data of the line drawing stored in the drawing plane 44 in the operation mode of telewriting and the image FIFO 42 from this image FIFO 42. The output image data is added and output. As a result, the video conference apparatus 1 can display a line drawing image on a natural image and a document image together.

That is, this drawing plane 44
Is based on the line drawing data input via the tablet and the line drawing data transmitted from the call target.
2 writes the image data to store the line drawing image. As a result, the video conference device 1 can perform telewriting on the document image and the natural image.

Further, the controller 41 uses the image FIFO.
By switching the operation of 42, the image input / output unit 10
Captured by the document image capturing device 13 via the image FIFO 42 sequentially into the arithmetic memory 40,
As a result, this image data can be compressed by the still image processing circuit 36 and transmitted.

(1-1-4) Main Processing Unit As shown in FIG. 6, the main processing unit 12 controls the overall operation of the video conference apparatus 1 by executing the processing procedure stored in the memory circuit 45 by the system controller 46. To do. That is, the system controller 46 uses the interface circuit (I
F) By detecting the operation of the remote commander 6 via 47, the line interface circuit (line IF) 48 is driven in response to the user's selection operation, and thereby the line to the desired call target is established. Connecting.

That is, the line interface circuit 48
Is connected to a connector arranged on the back surface of the processor 3 so that desired data can be transmitted and received to and from the call target. Further, in this state, the system controller 46 sets a format of data to be transmitted by executing a predetermined communication protocol with the call target, and subsequently, the encoder / decoder unit 11, the image data processing unit 14, and the audio processing unit 18 Etc. to issue a control command to start a call.

At this time, the system controller 46 activates the multiplexing circuit 49, whereby the image data D1 and D2 output from the encoder / decoder section 11, the image data processing section 14, and the audio processing section 18 are set.
The audio data DA is converted into H.264 by the multiplexing circuit 49. 221 is multiplexed according to the format of 221 to generate multiplexed data DMU, and this multiplexed data DMU is sent to the call target via the line interface circuit 48. On the contrary, the multiplexing circuit 49 inputs the multiplexed data DMU transmitted from the communication object via the line interface circuit 48, separates the multiplexed data DMU into the image data D1, D2, and the audio data DA. Output to circuit block.

Further, the system controller 46, when the user specifies the switching of the operation mode during the call with the call target, the multiplexed data D coming from the call target again.
When the operation mode is switched on the call target side by monitoring the MU, the encoder / decoder unit 1 responds to this switching.
1. The operations of the image data processing unit 14 and the audio processing unit 18 are switched so that a natural image or the like can be transmitted instead of a moving image, and line drawing data or the like can be transmitted and received as necessary. Has been done.

Therefore, the system controller 46 controls the entire operation and takes in the two-dimensional coordinate data input by operating the tablet 17 in a predetermined cycle, so that the coordinate data is continuously drawn as a line drawing. The line drawing data DW is output to the image data processing unit 14 to be displayed on the monitor device 4 and output to the multiplexing circuit 49. As a result, the video conference device 1
The line drawing data DW can be assigned to a part of the multiplexed data DMU and can be transmitted and received.

In this embodiment, the main processing unit 12
Is an external bus interface circuit (external bus IF) 5
By connecting an external device of RS232C interface via 0, the whole operation can be controlled via this external device, whereby the video conferencing apparatus 1 connects a separate controller as necessary. The whole operation can be controlled.

(1-2) Bus Controller By the way, as a method of controlling the whole operation by one system controller 46 as described above, for example, as shown in FIG. 7, a still image processing circuit 36, a binary image processing circuit 37 and the like are used. A method is conceivable in which the direct memory access controllers (DMAC) 54 and 55 are connected to the processing circuit, and the central processing unit (CPU) 56, which is a system controller, and the direct memory access controllers 54 and 55 are connected (Japanese Patent Laid-Open No. Sho 62-62) -67653). That is, the central processing unit 56 is connected to the common bus with the direct memory access controllers 54 and 55, and the direct memory access controllers 54 and 55 issue bus use requests HOLD1 and HOLD2 to the central processing unit 56 to permit bus occupation. Ask.

Direct memory access controller 5
4 and 55 are bus use requests HOLD1 and HOLD2.
Is temporarily stored in the register circuits (R) 57 and 58 and output via the OR circuits 59A and 59B.
9B sets the bus use requests HOLD1 and HOLD2 to 1
The two bus use requests are collectively output to the central processing unit 56. The central processing unit 56 uses this bus use request H
When the bus occupancy is acknowledged in response to OLD1 and HOLD2, the bus use permission signal H is sent through a predetermined delay circuit (that is, a daisy chain circuit (D)) D1 and D2.
OLDA direct memory access controller 5
Output to 4, 55.

However, even if this method is applied, the system controller 46 and the circuit blocks such as the still image processing circuit 36 eventually operate by alternately occupying the bus BUS in a time-division manner, and as a result, as a whole. Processing time will be delayed. That is, for example, while the still image processing circuit 36 processes a natural image, the system controller 46 causes the bus BU to
Since S cannot be accessed, for example, when the system controller 46 processes the coordinate data input from the tablet 17, it takes time to process the coordinate data.

As a method of solving this problem, a method of separately allocating a dedicated central processing unit to the local bus LBUS can be considered, but in this case, the central processing unit becomes 2 chips, and the entire structure becomes complicated accordingly. Upsizing.

Therefore, in this embodiment, as shown in FIG. 8, the local bus L is connected between the system controller 46 and the still image processing circuit 36 and the binary image processing circuit 37.
One central processing unit (ie system controller 46) by switching BUS occupancy
To be able to control the whole operation.

That is, the still image processing circuit 36, the binary image processing circuit 37, the image interface circuit 38, and the interface circuit 39 each have a direct memory access controller, which allows the arithmetic memory 40 via the local bus LBUS. It is designed so that you can access it directly. As a result, the still image processing circuit 3
When the control command is input from the system controller 46 and the binary image processing circuit 37, the image interface circuit 38, and the interface circuit 39 are activated, the arithmetic memory 40 is independently accessed to the control command. The data processing responded to can be executed.

The bus controller 35 is statically connected to the system controller 46 when none of the still image processing circuit 36, the binary image processing circuit 37, the image interface circuit 38, and the interface circuit 39 uses the local bus LBUS. Image processing circuit 36, binary image processing circuit 3
7. The local bus LBUS and the bus BUS are held in a connected state so that any of the image interface circuit 38, the image interface circuit 38, and the interface circuit 39 can use the local bus LBUS. In this state, the still image processing circuits 36, 2
A value image processing circuit 37, an image interface circuit 38,
When an access request ACS for accessing any of the interface circuits 39 is input from the system controller 46, the bus controller 35 outputs hold act signals HOLDACK1 to HOLDACK4, whereby the still image processing circuit 36 corresponding to the access request. Circuit blocks other than the binary image processing circuit 37, the image interface circuit 38, or the interface circuit 39 are set to the standby state.

In this state, the circuit block designated by the access request ACS is activated in response to a control command, and the local block LB is output from this circuit block.
When the US occupancy requests HOLD1 to HOLD4 are output, the bus controller 35 disconnects the connection between the bus BUS and the local bus LBUS, and thereby causes the circuit block which has been activated to occupy the local bus LBUS. As a result, the system controller 46 issues a command to the still image processing circuit 36 to start the processing of a natural image, or issues a command to the binary image processing circuit 37 to start the processing of a document image. Interface circuit 38 and interface circuit 3
When 9 starts input / output of image data, the connection between the bus BUS and the local bus LBUS is cut off,
Various processes can be separately executed in parallel with these processes.

Accordingly, the video conference apparatus 1 simplifies the overall configuration by controlling the overall operation with one central processing unit.
The size can be reduced, and the delay in processing speed can be prevented. Further, the system controller 46 can freely execute various kinds of processing without being restricted by the operation of the still image processing circuit 36, etc.
The memory map allocation can be freely selected, and the degree of freedom in design can be improved.

By the way, in this type of processing, it is necessary for the system controller 46 to monitor the processing status of each circuit block as required. However, if the local block LBUS is allowed to be occupied until the circuit block which has risen to the operating state completes a series of processes, it becomes difficult to monitor the processing status. Incidentally, when processing a natural image, data transfer of about 500 [Kbyte] is required, and the local bus LBUS is allowed to be occupied until a series of processing is completed. Etc. cannot be accessed.

Therefore, as shown in FIG. 9, each of the circuit blocks 36 to 39 has a local bus LBU in units of 1 [byte].
S (FIG. 9 (A)) is occupied to process data,
When the access request ACS is input from the system controller 46 to the bus controller 35 (FIG. 9B),
A wait WAIT signal is sent to the system controller 46 (FIG. 9C), and the system controller 46 is held in a standby state.

In this state, each circuit block 36 to 39 has 1
When the data processing in units of [byte] is completed, the circuit blocks 36 to 39 make the hold signals HOLD1 to 4 fall, and the bus controller 35 makes the hold signal HOLD.
When D1 to D4 fall, the wait WAIT signal is raised to allow the system controller 46 to access. At the same time, the bus controller 35 raises the hold act signal HOLDACK to set the circuit block in operation to the standby state (FIG. 9D), and connects the bus BUS and the local bus LBUS.

As a result, the system controller 46
For example, the still image processing circuit 36 can be accessed to determine to what extent the data processing has been completed, whether it is operating normally, etc. When the access is completed, the access request ACS is started. As a result, the bus controller 35
Lowers the hold act signal HOLDACK to release the waiting state of the operating circuit block, and this circuit block restarts the subsequent processing.

(1-3) Control of Telelighting In this embodiment, the system controller 46 operates the mouse connected to the remote commander 6 by the user,
Move the cursor to the drawing menu on the display screen and click to switch the entire operation mode to the drawing mode. When switching to this drawing mode, the system controller 46 switches to the telewriting operation mode when the same document image or natural image as the call target is being displayed on the monitor device 4, and then to the call target. The line drawing data mutually input to and from is displayed on the document image or the natural image, so that the line image can be drawn on the document image or the natural image to be discussed with the call target. .

That is, when the system controller 46 transmits and receives a document image or a natural image to and from the communication target in response to the user's selection operation and stores the common document image or natural image in the arithmetic memory 40, The image data stored in advance in the arithmetic memory 40 is converted into the image FIFO 42.
To display a document image or a natural image on the monitor device 4. The display of the document image or the natural image is performed in response to the operation of the user who is the call target, in response to the control command sent from the video conference device that is the call target, and in response to the operation of the remote commander 6, and the system controller. 46 is executed by issuing a control command to the controller 41.

Further, after displaying the document image or the natural image, the system controller 46 issues a control command to the menu plane 32 to simultaneously display the menu screen. If the document image is being displayed at this time, enlargement / reduction is performed. Allows you to choose between scrolling, rotating and rotating menus. This allows the system controller 46
When this enlargement, reduction, scrolling, or rotation menu is selected as a call target or on the side of the video conference apparatus 1, the control command is issued to the controller 41 to switch the address data to access the arithmetic memory 40. The image data in the arithmetic memory 40 is transferred to the image FIFO 42 again, and the document image which is enlarged, reduced, scrolled, or rotated corresponding to the selected menu is stored in the image FIFO 42. As a result, the video conference apparatus 1 can switch the display of the document image as needed to improve the usability.

On the other hand, in the drawing mode, the system controller 46 takes in coordinate data input via the tablet 17 at a predetermined cycle (for example, at a cycle of 20 samplings per second),
The user inputs a line drawing such as a straight line drawn on the tablet 17 in a sequence of point coordinates. Further system controller 46
Adds a predetermined control code to the fetched coordinate data, converts it into line drawing data DW, and outputs this line drawing data DW to the multiplexing circuit 49. As a result, the system controller 46 is adapted to transmit this line drawing data DW to the call target.

Further, the system controller 46, based on the line drawing data DW, draws the drawing plane 44.
The image data of the line drawing input by the user is displayed on the monitor device 4. Thereby, the video conference apparatus 1 can display a line drawing on the document image and the natural image when the document image or the natural image is displayed in advance.

Further, the system controller 46 inputs the line drawing data DW coming from the call target through the multiplexing circuit 49, and the line drawing data DW coming from the call target like the line drawing data DW inputted through the tablet 17. An image of a line drawing is formed on the basis of the DW so that the line drawing can be input and displayed on the same document image and the natural image, and telewriting can be performed. At this time, the display of the document image can be enlarged, reduced, rotated, or scrolled, so that the display of the document image can be switched and telelighted as necessary, which makes the video conference apparatus 1 more convenient than ever. Is designed to be able to improve.

By the way, when the document image can be enlarged or rotated in the telewriting as described above, when the user on the video conference apparatus 1 side is inputting a line drawing, the display of the document image on the callee side is switched. Can be considered. For example, when the document image is scrolled on the call target side while the document image having the circuit diagram shown in FIG. 10 is displayed, the video conference device 1 side indicates the transistor on the document image. Despite inputting the arrow, as shown in FIG. 11, on the callee side, line drawing data representing this arrow may arrive after scrolling the document image. In this case, the callee is not a transistor. The arrow specifies the output end of the capacitor.

Further, in this case, a similar state occurs on the side of the video conference apparatus 1, and the same state occurs not only when the screen is scrolled but also when the document image is enlarged, reduced or rotated. That is, if the document image is made to be able to be enlarged, reduced, rotated, or the like in the telewriting as described above, a state occurs in which the document image does not match the line image input by the user. This makes it impossible for a user unfamiliar with the operation to use the video conference apparatus 1 freely.

Therefore, in this embodiment, as shown in FIG. 12, when the user instructs the switching of the display of the document image, the system controller 46 does not immediately switch the display of the document image but requests the switching of the document image. Of the document control request command REQA (FIG. 12 (A)), and waits for the response command ACK in response to the device control request command REQA to be input from the call target AI (FIG. 12 (B)). .

Further, a document control request command RE
Period T from QA to input of response command ACK
During 1, the line drawing data DW etc. (hereinafter referred to as telewriting information) input from the call target AI is the call target AI.
By the telewriting information input on the original document image on the side, the system controller 46
Determines that the telewriting information coming from the call target AI is valid during this period T1, updates the image data of the drawing plane 44 based on this telewriting information, and transmits the call from the call target AI. The line drawing data is displayed on the document image before switching the display.

As a result, when switching the display of the document image, the video conference apparatus 1 displays the original document image until confirmation is obtained from the call target AI, and the telewriting information input from the call target AI during this period is changed to the original one. The document image is displayed on the document image so that the discrepancy between the document image and the line drawing input by the user can be effectively avoided.

Further, during this period T1, the system controller 46 interrupts the input of the coordinate data to stop the input of the telewriting information from the tablet 17, and when the response command ACK is transmitted from the call target AI side, The display of the document image is switched in the subsequent period T3 so as to correspond to the device control request command REQA. As a result, the system controller 46 switches the display of the document image in response to the user's operation, and then restarts the input of the telewriting information to restart the call target A.
Send to I.

As a result, on the side of the video conference apparatus 1, even when the display of the document image is switched, the discrepancy between the document image and the line image input by the user can be effectively avoided. Further, during the period T3 for switching the display of the document image, the system controller 46 temporarily stores and holds the telewriting information transmitted from the AI side of the call in the buffer memory, and when the switching of the display is completed, the temporarily held telewriting information is held. The image data of the drawing plane 44 is updated based on the writing information, so that the line drawing data transmitted from the call target AI is displayed on the document image after switching.

That is, after the response command ACK is input, the telewriting information that is subsequently input from the call target can be determined to be the telewriting information that was input on the document image whose display was switched. The controller 46 can superimpose the image of the line drawing on the document image after the display switching, and effectively avoid the discrepancy between the document image and the line image input by the user.

On the other hand, when the document control request command REQ is input from the call target (in this case, FIG.
2 is the case where the video conference apparatus 1 is on the call target AI side), the system controller 46 interrupts the input of the coordinate data to stop the input of the telewriting information after issuing the response command ACK. Then, the display of the document image is switched so as to correspond to the document control request command REQA, and then the input of the telewriting information is restarted and sent to the call target.

That is, when the display is switched in this way,
It is possible that the display of the document image may suddenly switch while the user is inputting a line drawing, and a user who is unfamiliar with the operation may mistakenly input the line drawing.
Therefore, in this embodiment, the system controller 4
Numeral 6 stops inputting the line drawing data DW for a predetermined period T2 after switching the display of the document image, thereby preventing useless input of the erroneously operated data DW even if the user makes an erroneous operation. It is designed to be able to do.

This document control request command REQ
During the period T2 until A is input and the display switching of the document image is completed, the system controller 46
When the telewriting information transmitted from the callee side is temporarily stored and held in the buffer memory and the switching of the display of the document image is completed, the image data of the drawing plane 44 is updated based on the temporarily held telewriting information. The line drawing data transmitted from the call target AI is displayed.

That is, the document control request command R
After the EQA has been input, the telewriting information that is subsequently input can be determined to be the telewriting information that has been input on the document image whose display has been switched, so that the system controller 46 inputs the device control request command REQA. Then, after the display is switched, the telewriting information is displayed on this display image, and the discrepancy between the document image and the line drawing input by the user can be effectively avoided.

Thus, the video conference device can be freely carried and used by a user who is not accustomed to the operation. Furthermore, by temporarily storing the telewriting information in the buffer memory when switching this document image, even if it takes time to switch the display, it is possible to perform telewriting without interrupting the conversation with the call target.
The usability can be improved accordingly.

In this way, when performing telewriting with the call target, the system controller 46 operates as shown in FIG.
The processing procedure shown in FIG. 3 is executed to control the entire operation. That is, when the power is turned on, the system controller 46 moves from step SP1 to step SP2 and displays the main menu which is the initial screen here.

This main menu displays a list of call targets registered in advance to select a call target. When the user selects a call target and clicks the mouse, the system controller 46 connects to the line interface. The circuit 48 is driven to connect the line L to the communication target, and then the menu for selecting the operation mode is displayed. When the user or the call target specifies the operation mode in this state, the system controller 46 switches the entire operation mode to the specified operation mode.

As a result, the system controller 46
When the user or the call target selects the transmission display of the document image or the natural image, after the document image or the natural image is loaded into the arithmetic memory 40, the image data of the document image or the natural image is transmitted to the call target, and Instead, the image data of the document image or the natural image transmitted from the call target is stored in the arithmetic memory 40.

Further, the system controller 46 outputs a control command to the controller 41 to display this document image or natural image on the monitor device 4, and then moves to step SP3 where the user makes a drawing (represented by DRAW). It is determined whether the operation mode is selected. If a negative result is obtained here, the system controller 46 repeats step SP3, and when the user selects an operation mode such as moving image transmission at this time, the overall operation is switched to the corresponding operation mode.

On the other hand, when the user selects the drawing menu, the system controller 46 moves to step SP4 when a positive result is obtained in step SP3, and the menu screen of the monitor device 4 is changed to the drawing menu screen. After switching to step SP5, the process proceeds to step SP5.

Here, the system controller 46 determines whether the user has selected a menu such as straight line input, curved line input, line drawing deletion, etc., and in response to this, whether or not a drawing drawing request has been input from the remote commander 6, If a negative result is obtained here, the process directly proceeds to step SP6, whereas if a positive result is obtained here, the process proceeds to step SP7. In step SP7, the system controller 46 adds the control code to the coordinate data sequentially input according to the menu selected by the user to generate the telewriting information DW, and sends the telewriting information DW to the call target. The image data of the drawing plane is updated based on the DW based on this telewriting information.

As a result, the system controller 46
A drawing drawing process is executed, and when the document control request command REQA is input from the communication target at the time of this process, the communication procedure described above with reference to FIG. 12 is executed, whereby a mismatch between the document image and the line drawing input by the user is detected. Avoid effectively. Subsequently, when the user stops inputting the line drawing, the system controller 46 moves to the following step SP6, where the user to be called inputs a straight line,
A menu such as curve input or line drawing deletion is selected, and it is determined whether or not a drawing drawing request is input from the call target.

If a negative result is obtained here, the system controller 46 directly proceeds to step SP8, whereas if a positive result is obtained here, the system controller 46 proceeds to step SP9. In step SP9, the system controller 46 updates the image data of the drawing plane based on the telewriting information DW that is subsequently input from the call target, and thereby executes the remote drawing drawing process controlled by the call target. Then move to step SP8.

Subsequently, the system controller 46 determines whether or not a screen control key of menus such as enlargement, scroll, rotation, etc. is selected, and if a negative result is obtained here, the process directly proceeds to step SP10. If a positive result is obtained here, the routine proceeds to Step SP11. In this step SP11, the system controller 46
The screen control key processing shown in FIG. 14 is executed, and thereby the communication procedure described above with reference to FIG. 12 is executed.

That is, the system controller 46 moves from step SP12 to step SP13, sends the device control request command REQA to the call target here, and then moves to step SP14, where a drawing drawing request is input from the call target. To determine. If a negative result is obtained here, the system controller 46
Directly goes to step SP15, whereas if a positive result is obtained here, it goes to step SP16 to execute the drawing drawing process of the remote control.

That is, the system controller 46 determines that the telewriting information coming from the call target AI is valid, updates the image data of the drawing plane 44 based on this telewriting information, and transmits it from the call target AI. The selected line drawing data is displayed on the document image before switching the display. As a result, during the period T1, after processing the telewriting information coming from the call target, the system controller 46 moves to step SP15 where the response command A from the call target is sent.
It is determined whether or not CK is input.

If a negative result is obtained here, the system controller 46 returns to step SP14, while
If an affirmative result is obtained here, the process proceeds to step SP17, the display of the document image is switched in response to the operation of the screen control key, and this processing procedure is completed at subsequent step SP18.

When this screen control key processing is completed, the system controller 46 proceeds to step SP10 to judge whether or not the device control request command REQA has been inputted from the communication object, and if a negative result is obtained here.
In contrast to step SP19, if a positive result is obtained here, the process moves to step SP20. This step SP
At 20, the system controller 46 executes the screen control request process shown in FIG. 15, thereby executing the communication procedure described above with reference to FIG.

That is, the system controller 46 shifts from step SP21 to step SP22, sends a response command ACK to the communication target here, and then switches the display of the document image in response to the device control request command REQA at the subsequent step SP23. After that, the process proceeds to step SP24 to end this processing procedure. This causes the system controller 46 to continue to step SP1.
End with 9 to end this drawing mode (E
XIT) menu is selected, and if a negative result is obtained here, the process proceeds to step SP7.
When a positive result is obtained, the process returns to step SP2.

(1-4) Processing of Image Data (1-4-1) Arithmetic Memory In this embodiment, the image data processing unit 14 shares the arithmetic memory 40 with the natural image and the document image, thereby forming the entire structure. Is designed to be simplified.
That is, as shown in FIG. 16, the arithmetic memory 40 is formed using eight 8-bit 128 [kbite] memories 40A to 40H, and the address generation circuits 41A and 41B forming the memory controller 41 switch the address data. This allows the storage of natural images and document images.

That is, as shown in FIG. 17, when storing a luminance signal of the NTSC system, the arithmetic memory 40 needs an area for storing image data of 704 pixels in the horizontal direction and 480 pixels in the vertical direction. . On the other hand, in the case of storing a PAL luminance signal, the arithmetic memory 40 needs an area for storing image data of 704 pixels in the horizontal direction and 576 pixels in the vertical direction. On the other hand, the color difference signal is
Since the deterioration of the resolution is not visually recognized as compared with the luminance signal, an area for storing the image data is required for each of the U and V components by the number of pixels that is 1/2 of the number of pixels obtained by the luminance signal. Become.

That is, when storing the natural images of the NTSC system and the PAL system, the arithmetic memory 40 stores 8 bits × 704 × 576 × for the luminance signal Y and the color difference signals U and V, respectively.
A memory capacity of 2 is required. On the other hand, in the case of this embodiment, the document image is A at a resolution of 8 [lines / mm].
A memory capacity of 2376 dots in the horizontal direction x 1728 dots in the vertical direction is required by loading up to the size of 4 plates.

Therefore, in this embodiment, when storing a natural image, the arithmetic memory 40 allocates a memory space of 1024 × 480 so as to correspond to the horizontal direction and the vertical direction of the natural image. A memory space is formed, and image data of a luminance signal and a color difference signal is taken in. Further, as shown by an arrow a, the memory space that is additionally allocated in the horizontal direction is allocated to the memory space in the vertical direction that is insufficient due to the allocation of the memory space in this way.
Image data of both the L system and the NTSC system can be stored.

On the other hand, as shown in FIG. 18, in the case of storing a document image, the arithmetic memory 40 forms a memory space such that eight memories are arranged in a plane with a depth of 1 bit. Stores binary image data of up to 4096 x 2048 pixels. As a result, the video conference device 1
Is designed to store the natural image and the document image by switching the address data of the arithmetic memory 40, and the operation memory 40 can be shared by the natural image and the document image.

Therefore, the address generation circuits 41A and 41A
B sequentially generates the address data corresponding to the odd field and the even field of the display image, respectively, and at this time switches the address data between the natural image and the document image to store the image data corresponding to the preset memory space. To do. That is, in the natural image, as shown in FIG. 19, in the natural image, the address generation circuits 41A and 41B have the first and second odd-numbered fields with respect to the image data input in the sequential raster scanning order for the luminance signal Y. The address data of the memories 40A to 40H is generated so that the memories 40A and 40B alternately and consecutively store the image data, and the fifth and sixth memories 40E and 40F alternately and consecutively generate the image data at an even field. The address data of the memories 40A to 40H is generated so as to store

On the other hand, the address generation circuits 41A and 41B use the odd number field for the color difference signals for the image data input in the sequential raster scanning order.
Memory 40 to store the component and V component image data in the third and fourth memories 40C and 40D, respectively.
The address data of the memories 40A to 40H is generated so that the address data of A to 40H is generated and the image data of the U component and the image data of the V component are stored in the seventh and eighth memories 40G and 40H with an even field, respectively. As a result, the address generation circuits 41A and 41B cause the image FIFO
42 to transfer the image data to form a display image, to transfer the image data to the still image processing circuit 36 to compress the data, and further to the image FIFO 42 or the still image processing circuit 3
When the image data is taken in via 6, the address data can be easily generated.

On the other hand, in the case of the document image, the address generation circuits 41A and 41B sequentially cyclically cycle through each line of the document image as shown in FIG.
Address data is generated so as to allocate the eighth memories 40A to 40H. As a result, the address generation circuit 41
A and 41B transfer image data to / from the binary image processing circuit 37, transfer image data to the image FIFO 42 to form a display image, and further transfer the image data via the image scanner 15. The address data can be easily generated when loading.

Further, address generation circuits 41A and 41B
Has two systems of address generation circuits respectively corresponding to the vertical direction and the horizontal direction of the display image, whereby the address generation circuits are complementarily switched to generate the address data, so that the image data is transferred to the image FIFO 42. When transferring and forming a display image, it is possible to easily form a display image that is rotated 90 degrees vertically and horizontally.

On the other hand, the image FIFO 42 is a FIFO for odd and even fields of the luminance signal.
42Y1 and 42Y2 and FIFOs 42C1 and 42C2 for odd and even fields of the color difference signal
These four FIFOs are used to display natural images.
Image data corresponding to 42Y1 to 42C2 is transferred from the arithmetic memory 40 and stored therein, and further transferred from the analog digital conversion circuit 21 to be stored therein, and the stored image data is transferred via the controllers 41Y and 41C to the matrix circuit. It is adapted to output to 43 to form a display image.

On the other hand, when displaying a document image, the image FIFO 42 converts the corresponding binary image data into 8-bit image data by the controller 41Y and stores it in the luminance signal FIFOs 42Y1 to 42Y2. Further, when displaying a document image, the image FI
The FO 42 stores the image data in the remaining color difference signal FIFOs 42C1 and 42C2 with a delay of one line, thereby storing the image data stored in the color difference signal FIFOs 42C1 and 42C2 in the luminance signal FIFOs 42Y1 and 42Y2. The image data is sequentially output at a timing delayed by one line from the corresponding image data.
The image data of three consecutive lines can be output simultaneously.

Accordingly, the image data processing section 14 can reduce the flickering of the display image by adding and outputting the image data of the three lines by the flickering reduction circuit (built in the controller 41). Has been done. Therefore, the controllers 42Y and 42C, which form a part of the controller 41, have FIFOs 42Y1, 42Y2 and 42C for luminance signals and color difference signals, respectively.
1, 42C2 can be controlled.

Further, the controllers 42Y and 42C are
The output data of the FIFOs 42Y1, 42Y2 and 42C1, 42C2 is fed back to the input side, and the built-in data processing circuit can perform arithmetic processing with the output data of the arithmetic memory 40 and store the data again. N
Natural images transmitted by the TSC system are converted to the NTSC system or PA.
The display image can be formed by converting to the L system.

Further, the controllers 42Y and 42C are
By performing the feedback process and the addition process on the document image, the vertical and horizontal magnifications of the display image can be maintained at a constant value regardless of whether the monitor device 4 of the PAL system or the NTSC system is connected. . That is, the teleconference device 1 of this type uses a PAL system monitor device for a call target during telelighting.
On this side, there is a case where the monitor device 4 of the NTSC system is used.

In this case, the video conference apparatus 1 needs to maintain the same vertical and horizontal magnification of the display image as that of the call target and form the same display image. Therefore, in this embodiment, the video conference apparatus 1 is connected to the NT when the communication target is a PAL type monitor device to form a display image.
The display of the display image is switched so that the same display image as that of the call target is formed on the SC type monitor device 4, whereby the aspect ratio of the call target and that of the display screen are kept the same.

Similarly, by utilizing this conversion processing, the video conference apparatus 1 makes a call when the PAL system monitor device 4 is connected while the display target image is formed by the NTSC system monitor device. The aspect ratio of the display image is held at a constant value so that the same display image as the target is formed.
Thus, the video conferencing device 1 is thus able to
Since the FO 42 can execute the image conversion processing of the NTSC system and the PAL system, the operation mode of the image conversion circuit 29 is switched and the circuit board of the image input / output unit 10 is replaced to easily perform the PAL system and the NTSC system. The monitor device 4 and the imaging unit 5 can be freely connected,
The usability is improved accordingly.

(1-4-2) Processing of Document Image As shown in FIG. 21, the arithmetic memory 40 sequentially inputs the image data input line-sequentially from the image scanner 15 via the interface circuit 39. After storing the image data, the image data stored in a predetermined order is output to the binary image processing circuit 37, whereby the document image is data-compressed and sent to the call target. Further, the image data of the document image transmitted from the call target is decompressed by the binary image processing circuit 37 and sequentially stored, and output to the interface circuit 39 at a predetermined timing, thereby outputting this document image to the printer 16. To do.

On the other hand, in the case of displaying this document image, the arithmetic memory 40 has the address generation circuit 41A.
And 41B, the image data is sequentially output to the image FIFO 42 based on the address data. At this time, the address generation circuits 41A and 41B are adapted to display the document image at a predetermined magnification by switching the address data to be generated, and to rotate and scroll to display.

At this time, since the number of pixels of the monitor device 4 is smaller than that of the document image, the calculation memory 40
Stores the image data in the FIFO 42 with the number of pixels reduced by the data conversion circuit 41D.
Binary data is converted into multi-valued data in 1D so that a display image with no discomfort can be formed.
That is, when forming a display image by reducing the number of pixels in this way, a method of thinning out image data to compensate for the insufficient resolution may be considered, but in this case, diagonal straight lines are displayed jaggedly and the display image is unnatural. There is a drawback displayed in.

For this reason, in this embodiment, the resolution that deteriorates due to the decrease in the number of pixels is compensated for by gradations, so that straight lines and the like can be displayed smoothly and a natural display image can be displayed.

That is, when displaying a document image, the address generation circuits 41A and 41B sequentially generate address data in accordance with the display mode such as the magnification selected by the user, and thereby the image data is transmitted to the FIFO 42 in real time. Forward. At this time, the data conversion circuit 41
D converts the 16 binary image data into one multi-valued image data so that 16 pixels of the document image are assigned to one pixel of the display screen, and the display screen fills A4 size.
Displays a size document image, which gives a magnification of 1
Double display image is formed.

On the other hand, as shown in FIG. 22, when the user selects the display mode with the magnification of 2 times, the data conversion circuit 41D assigns 4 pixels of the document image to 1 pixel of the display screen. Each binary image data is converted into one multi-valued image data, whereby a part of the document image is displayed on the monitor device 4 and a display image with a magnification of 2 is formed. Further, when the user selects the display mode with the magnification of 4 times, the data conversion circuit 41D converts one input binary image data into one so that one pixel of the document image corresponds to one pixel of the display screen. This is converted into individual multi-valued image data, whereby a part of the document image is displayed on the display screen to form a display image with a magnification of 4 times.

At this time, as shown in FIG. 23 corresponding to FIG. 22, when a display image is formed at a magnification of, for example, 2 times, the data conversion circuit 41D converts the display image into one pixel on the display screen.
Binary image data for pixels are added to detect how many white level pixels are present in the four pixels. Further, the data conversion circuit 41D normalizes the addition result, and when all four pixels are at the white level, the brightness level of the corresponding multi-valued image data is the white level (that is, the brightness level of 100 [%]). (FIG. 23 (A)).

On the other hand, the data conversion circuit 41D has 4
When three of the pixels have a white level (FIG. 23B), the brightness level of the corresponding multi-valued image data is set to a brightness of 75% so as to correspond to the number of white level pixels with respect to the total number of pixels. When the level is set and 2 out of 4 pixels are the white level (FIG. 23C), similarly, the brightness level of the corresponding multi-valued image data is set to the brightness level of 50%. Further, when one of the four pixels has a white level (FIG. 23 (D)),
Furthermore, when all four pixels have a black level, the brightness levels of the corresponding multi-valued image data are set to 25 [%] and 0 [%], respectively, and the binary image data is converted into multi-valued image data. Process and output.

Further, in the case of the display mode of 1 time, 16 2
By converting the value image data into one multi-valued image data, the data conversion circuit 41D adds and normalizes the 16 pieces of image data to convert the 16 binary image data into a multi-valued image of 16 gradations. Convert to data. Further, when a display image is formed at a magnification of 4 times, one binary image data is converted into one multi-valued image data, so that the data conversion circuit 41
When the binary image data has a white level and a black level, the corresponding multi-valued image data is 100 [%] and 0.
Set the brightness level to [%].

Thus, the image data processing unit 14 can form a smoothly continuous display image by adding and normalizing the image data corresponding to one pixel of the display screen when displaying the document image. Therefore, the resolution of the monitor device, which is insufficient, is compensated for by the gradation so that a natural display image can be displayed.

By the way, as described above with reference to FIG.
In the case of this embodiment, the image data of the document image is sequentially and cyclically allocated to the eight memories 40A to 40H in a line unit, so that the address generation circuits 41A and 41B allocate the eight memories 40A to 40H. By selecting and outputting common address data, it is possible to read consecutive 8 lines of image data at the same time. Further, in the case of a document image, since the image data is formed of binary data, the 8-bit memory 40
Image data for 8 pixels can be read from A to 40H at a time.

As a result, as shown in FIG. 24, the arithmetic memory 40 can simultaneously output image data for 64 pixels of the rectangular partial area of the document image. In FIG. 24, each represent a pixel corresponding to the memory 40A~40H by symbols A to H, it represents the pixels corresponding to the bits that are output by the symbol D ₀ to D _7.

As a result, the address generation circuits 41A and 41A
1B collectively outputs image data for 64 pixels at a time to the data conversion circuit 41D, and the data conversion circuit 41D forms these 64 pixels by 16 pixels × 4 blocks according to the magnification selected by the user. Image data is converted into multi-valued image data of 4 pixels × 4 blocks and multi-valued image data of 1 pixel × 4 blocks and output. That is, the data conversion circuit 41D
When the user selects the display mode with the magnification of 4 times, the one-block 16-pixel binary image data is assigned to the multi-value image data with 16 pixels, whereas the user selects the display mode with the double-magnification , A block of 16 pixels is divided into an area of 4 pixels × 4 blocks, and binary image data of 4 pixels of each block is assigned to 1 pixel of the display screen. Further, when the user selects a display mode with a magnification of 1, one block of 16 pixels is assigned to one pixel of the display screen.

As a result, the address generation circuits 41A and 41A
1B can switch the area of the document image to be assigned to the display screen by simply switching the start value of the address data, and can further switch the start value in order to scroll the display screen, and the data conversion circuit 41D.
The document image can be displayed at a desired magnification simply by sequentially updating the address data in accordance with the processing speed of. On the other hand, the data conversion circuit 41D can form a display image with a desired magnification simply by selectively inputting sequentially input image data and converting the image data into multi-valued data.

As a result, the image data processing unit 14 causes the address generation circuits 41A and 41B and the data conversion circuit 4 to operate.
1D can be easily formed by a logic circuit, whereby binary image data can be converted into multi-valued image data in real time for processing, and in the video conference apparatus 1, the desired configuration can be obtained with a simple configuration as a whole. Document images can be displayed. When the image data of the document image is input / output between the binary image processing circuit 37 and the interface circuit 39, the address generation circuits 41A and 41B are used.
Is adapted to sequentially generate the address data by sequentially selecting the first to eighth memories 40A to 40H and cyclically generating the address data so that the image data can be sequentially input and output line-sequentially. ing.

(1-4-3) Image Conversion By the way, as described above, in this type of video conference apparatus 1, there are cases where the call target is displaying the document image on the display screen of the PAL system. In
In order to display the same display image as this call target on the monitor device 4, the data interpolation circuit 41E executes interpolation calculation processing. That is, in the PAL system and the NTSC system,
By forming an effective screen with the number of vertical lines of 576 lines and 480 lines, respectively, a display image of 6 lines in the PAL system is displayed in 5 lines of the NTSC system.

Therefore, when the same document image as the call target is monitored, and the call target and the video conference apparatus 1 are monitoring the document image by the PAL and NTSC monitor devices, respectively, the interpolation calculation method is used. The image data of 6 lines output from the arithmetic memory 40 is converted into image data of 5 lines by applying
By storing in O42, a display screen can be formed with the same aspect ratio as the call target. On the contrary, when the call target and the video conference device 1 are monitoring the same document image with the monitor devices of NTSC system and PAL system, respectively, the image data for 5 lines output from the arithmetic memory 40 is 6 lines. Minute image data converted to FIFO
By storing in 42, a display screen can be formed with the same aspect ratio as the call target.

As described above, if the display image can be formed with the same aspect ratio even when the call target and the system of the monitor device are different from each other, it is possible to display the painting data separately transmitted at the time of telelighting with the displayed document image. It is possible to smoothly interact with each other without worrying about the position, and to improve the usability of the video conference device 1.

That is, when converting the binary image data into multi-valued image data by applying the above-mentioned method, the data conversion circuit 41D simultaneously converts adjacent two lines of image data into multi-valued image data and outputs it. .

In FIG. 25, as indicated by arrows indicating changes in image data from the NTSC system to the PAL system and from the PAL system to the NTSC system, the interpolator 41E is a monitor device of the NTSC system or the PAL system, and the video conference. When a PAL-type or NTSC-type monitor device is connected to the device 1, weighting coefficients are switched to perform weighted addition of image data of adjacent two lines so that the same screen as the call target can be displayed. Image data of PAL system or NTSC system is generated.

That is, when the call target is an NTSC system monitor device and a PAL system monitor device is connected to the video conference apparatus 1, the interpolation circuit 41E determines that the first field of the odd field (represented by the symbol O) is , The output data of the data conversion circuit 41D is stored in the FIFO 42 as it is, while the subsequent even field (represented by the symbol E)
As for the first line, the image data of the odd field first line and the even field first line is 0.125: 0.87.
Image data is generated by weighted addition with a weighted addition ratio of 5.

On the contrary, when the call target is a PAL system monitor device and the video conference device 1 is connected to the NTSC system monitor device, the interpolation circuit 41E determines that the data of the odd field first line is data. Conversion circuit 41D
The output data of is stored in the FIFO 42 as it is, whereas for the subsequent even field first line, the image data of the even field first line and the odd field second line are weighted and added at a weighting addition ratio of 0.750: 0.250. Generate image data.

When the weighted addition is performed in this way to generate the image data and the image data is stored in the FIFO 42, as shown in FIG. 26, the interpolation circuit 41E causes the odd-field image data only during the first one-field period. Is generated and this image data is stored in the FIFO 42 (FIG. 26 (A)).
On the other hand, during the following one field period, the interpolation circuit 4
1E is generated by subjecting even-numbered image data to interpolation calculation processing, and stores this image data in the FIFO 42 (FIG. 26 (B)). Corresponding to this, the FIFO 42 sequentially stores the image data of odd fields output from the interpolation circuit 41E during the first one field period, and the subsequent 1 field.
During the field period, the even field image data output from the interpolation circuit 41E is sequentially input, and the stored odd field image data is fed back to the input side to be sequentially stored again.

As a result, the image data processing section 14 converts the number of lines of the image data and stores the resulting image data in the FIFO 42 for one field period, whereby the sequential operation memory 40 is operated.
The image data output from E can be processed in real time to easily convert the number of lines. That is, by reading 64 image data at a time from the arithmetic memory 40, the data conversion circuit 41D can simultaneously generate multi-valued image data for two lines in synchronization with the writing timing of the FIFO 42.

Thus, the interpolation circuit 41E inputs the multi-valued image data for two lines in parallel and performs an interpolation process, thereby synchronizing the image data of even and odd fields with 1 in synchronization with the writing timing of the FIFO 42. It can be generated alternately in units of fields.

On the other hand, as for the image data output from the FIFO 42, the image data of each line is formed by alternately outputting the image data of the odd field and the even field at the interlace timing to form the display image. And FIF alternately with even fields
The display image can be formed in the same waiting time as when the processing of this method conversion is not executed by writing in O42.

By the way, when the system conversion processing is not executed in this way, the interpolation circuit 41E determines the data conversion circuit 41D.
The image data of two lines that are simultaneously output in parallel from the image FIFO 42 are directly output to the image FIFO 42.
The two lines of image data are input and output simultaneously in parallel and selectively output by the flickering reduction circuit 41F, whereby even-numbered field image data and odd-numbered field image data can be selectively output.

Further, the weighted addition processing of this kind can be easily formed by forming a logic circuit, and thus the interpolation circuit 41E can be formed by the logic circuit to transfer the output data of the arithmetic memory 40 to the FIFO 42 in real time. As a result, it is possible to improve the usability of the entire video conference apparatus 1 with a simple configuration.

When the conversion of the number of lines is completed, the image data processing unit 14 interrupts the writing from the arithmetic memory 40, while continuing to output the image data of the FIFO 42 sequentially, and at this time, the output data of the FIFO 42 is output. Is returned to the input side and stored again, so that the display image can be continuously displayed. As a result, the video conference apparatus 1 returns the image data of the FIFO 42 and sequentially and cyclically outputs the image data, unless the user inputs a display switching instruction such as scrolling again. Thus, the arithmetic memory 40 can be used for other processing.

By the way, when the output data of the FIFO 42 is fed back to the input side and stored again in this way, the FIFO 42
The image data stored in the arithmetic memory 40 for only a partial area of the display image among the image data stored in
The image data of O42 can be updated. Using this principle, the controllers 41Y and 41C feed back only the image data of the area designated by the user and store it in the FIFO 42 again when the user selects the window display mode, and the remaining area of the arithmetic memory 40 is stored. Rewrite with image data.

As a result, the image data processing unit 14
The conversion means of the L-NTSC system is diverted, and only a partial area of the document image is enlarged and displayed as necessary. Further, at this time, by sequentially re-loading the document images into the arithmetic memory 40 and sequentially updating a partial area of the FIFO 42, it is possible to display a plurality of document images in an index form like a multi-screen, which makes it easy to perform. The configuration is designed to further improve usability.

By the way, as described above, the PAL system and the NTS
In the case of converting the number of lines between the C format and the C format, a method of generating an image defined by CIF, which is an intermediate format, like the image conversion circuit 29, and converting this image into an image of the PAL system and the NTSC system is considered. . However, this method is characterized in that once the image of the intermediate format is formed, the image quality is deteriorated accordingly. Thus, in the case of this embodiment, the image data processing unit 14 converts the number of lines directly between the PAL system and the NTSC system without forming such an image of the intermediate format, thereby effectively deteriorating the image quality. It is designed to be avoided.

(1-4-4) Reduction of flickering By the way, when displaying a document image in this way,
There is a case where one line of an odd field is displayed in black and a line of an even field adjacent thereto is displayed in white, in which case flickering occurs. Especially, in the PAL system, the flickers are conspicuous because the frame frequency is lower than that in the NTSC system. Further, this type of document image has a feature that the brightness level is drastically changed between adjacent lines due to the extremely high resolution, and flickering is noticeable.

Therefore, in this embodiment, the image data processing unit 14 is adapted to reduce this flickering by the flickering reduction circuit 41F. As shown in FIG. 27, the principle of this flickering reduction is to add two consecutive vertically adjacent image data by weighting and adding three consecutive lines of image data.
The luminance component of the line is mixed into the center line, thereby reducing abrupt luminance level changes between even and odd fields.

For this reason, the interpolation circuit 41E outputs the image data to the luminance signal FIFOs 42Y1 and Y2,
Image data DL delayed by one line is generated in addition to continuous two lines of image data, and the image data DL is stored in the color difference signal FIFOs 42C1 and 42C2. As a result, the FIFO 42 simultaneously outputs the image data stored with a delay of one line and the image data of two consecutive lines of odd and even fields to the flickering reduction circuit 41F, and the image data of three consecutive lines. Are sequentially output in the order of raster scanning.

The flickering reduction circuit 41F adds the luminance components of the upper and lower lines by 25 [%] to the luminance components of the central line by weighting and adding the image data of the three lines at a ratio of 1: 2: 1. Image data of the center line is generated and the image data of the center line is output. By generating the image data of the central line, when the conversion processing of the number of lines is not executed, the image data output from the FIFO 42 are simultaneously selected in parallel and output.

On the other hand, when the conversion processing of the number of lines is executed, the flickering reduction circuit 41F interrupts the flickering reduction processing for the first field.
Image data of odd fields is selectively output from the output data of the FIFO 42, and the flickering reduction processing is executed from the subsequent fields. As a result, the image data processing unit 14 can reduce abrupt changes in luminance level between adjacent lines and effectively reduce flickering even when displaying a document image.

By the way, as one of the methods of reducing the abrupt luminance change between the adjacent lines in this way, as shown in FIG. 28, a method of mixing the luminance components between the two adjacent lines can be considered. In the case of the method, the resolution is 1/2
It is inevitable to fall to. Thus, as in this embodiment, the luminance component is mixed between the adjacent three lines to reduce the flickers, so that it is possible to effectively avoid the reduction of the vertical resolution and reduce the flickers.

(1-4-5) Recording of Line Drawing By the way, at the time of telelighting as in this embodiment, when the image of the drawing plane 44 and the image of the FIFO 42 are displayed in an overlapping manner, the video conference device 1 or the callee side When the magnification of the display image is switched, or when the display screen is further scrolled, there is a drawback that the line image input so far does not match the display of the document image.

As one method for solving this problem, there is a method in which the same memory space as the document image is formed in the drawing plane 44 and the image of the drawing plane 44 is enlarged and scrolled in accordance with the enlargement and scroll of the document image. Although conceivable, in this case, the construction of the drawing plane 44 becomes large, and the peripheral circuit of the drawing plane 44 becomes complicated. Therefore, in this embodiment, when the user switches the magnification of the display screen while the line drawing image is input to the drawing plane 44, the system controller 46 further scrolls and rotates the display screen. As shown, the image data of the line drawing stored in the drawing plane 44 is output to the arithmetic memory 40, and the line drawing is overwritten on the document image.

That is, the system controller 46 sequentially reads out image data such as a line drawing from the drawing plane 44 and controls the address generation circuit 41H (FIG. 16) according to the document image display magnification and display position. When the coordinates are converted and stored in the arithmetic memory 40 and all the images are stored in the arithmetic memory 40, the contents of the drawing plane 44 are cleared. As a result, the video conference apparatus 1 can display the line drawing input so far at the display position on the original document image as it is, even if the document image is enlarged, scrolled, or rotated, thereby improving usability. .

Further, by holding the image data of the line drawing in the drawing plane 44 until the document image is enlarged, scrolled, or rotated in this way, the contents of the drawing plane 44 are updated as necessary to erase the line drawing freely. , Can be rewritten and the usability can be improved accordingly.

(1-4-6) Processing of Natural Image On the other hand, when processing a natural image, as shown in FIG. 29, the image data processing unit 14 uses the digital video input from the analog digital conversion circuit 21. The signals are sequentially input to the FIFO 42 via the interpolation circuit 41E. At this time, the FIFO 42 feeds back the output data to the interpolation circuit 41E, and the interpolation circuit 41E sequentially adds and averages the fed-back image data and the image data output from the analog digital conversion circuit 21. Then, image data is generated, and the image data obtained by the addition and averaging is sequentially output to the FIFO 42.

As a result, the FIFO 42 can remove a noise component whose signal level changes between fields when a natural image is picked up, and can repeat this feedback process to store the noise-reduced image data. Has been done.

Thus, the image data processing unit 14
The image data stored in the IFO 42 is transferred to the controller 41Y.
And 41C to output to the digital analog conversion circuit 23 so that the captured natural image can be monitored, and further output to the still image processing circuit 36 via the operation memory 40 to be sent to the call target. It is done like this. On the other hand, in the case of the image data of the natural image sent from the call target, the image data processing unit 14 once outputs this image data via the still image processing circuit 36 to the arithmetic memory 4
After being stored in 0, it can be transferred to the FIFO 42 in real time to form a display image as in the case of the document image.

The still image processing circuit 36 of this type applies the orthogonal transformation method to cut out the image data in units of 8 pixels × 8 pixels and process it. Therefore, in this embodiment, the address generation circuits 41A and 41B alternately select the first and second memories 40A and 40B in the horizontal direction when transferring the image data of the natural image to the still image processing circuit 36. After the image data of the luminance signal for 8 pixels is transferred to the still image processing circuit 36, the fifth and sixth memories 40 are continuously operated.
E and 40F are alternately selected, and the image data of the luminance signal for 8 pixels in the horizontal direction of the following line is processed by the still image processing circuit 36.
(FIG. 19).

When the transfer of the image data in units of 8 pixels is repeated for 8 lines in the vertical direction, the address generation circuit 41 continues.
A and 41B select the third memory 40C and horizontally transfer four pieces of image data (corresponding to 8 pixels of the luminance signal) to the still image processing circuit 36, and subsequently, the seventh memory 40G. Is selected to transfer four pieces of image data in the horizontal direction to the still image processing circuit 36. When the third and seventh memories 40C and 40G are alternately switched to transfer the image data of eight lines in the vertical direction, the fourth and eighth memories 40D and 40H are also alternately switched to each other for eight lines in the vertical direction. Image data is transferred to the still image processing circuit 36.

As a result, the image data processing unit 14 can easily generate address data even when switching and processing the address data between the natural image and the document image.
Image data of a natural image can be output to the still image processing circuit 36 in units of pixels × 8 pixels. As a result, the still image processing circuit 36 can take in and process the sequentially input image data in a time series, and the configuration can be simplified accordingly, and the image data processing unit 14 as a whole can easily receive the address data. Since it can be generated, the configuration can be simplified accordingly.

On the other hand, when the image data output from the still image processing circuit 36 is input, the address generation circuit 4
1A and 41B generate address data in the same manner as when outputting image data to the still image processing circuit 36, whereby the image data processing unit 14 time-series the image data sequentially demodulated by the still image processing circuit 36. Can be stored in the arithmetic memory 40, and the entire configuration can be simplified accordingly.

On the other hand, as shown in FIG. 30, when displaying the image data sent from the call target and stored in the arithmetic memory 40, the image data processing unit 14 performs continuous 2
The line image data is simultaneously selected and output to the interpolation circuit 41E. Here, if the image data of the natural image transmitted from the call target is different from the system of the monitor device 4, the system controller 46 PAL-displays the document image.
Similar to the case where the NTSC image conversion process is executed, these two image data are weighted and added.

The FIFO 42 similarly processes this image data for each odd field and even field in the same manner as when the PAL-NTSC system image conversion process is executed for the document image. As a result, the video conference apparatus 1 can perform conversion processing on the PAL-NTSC system image for the natural image, similarly to the case where the number of lines of the document image is converted and displayed, thereby further simplifying the overall configuration. You can

Further, the video conference apparatus 1 is also adapted to feed back the output data of the FIFO 42 and store it again for natural images as well, thereby displaying multi-screens and windows for natural images as in the case of document images. A screen can be formed, and an image of a line drawing is stored in the arithmetic memory 40 from the system controller 46 so that the line drawing can be overwritten on the natural image.
Therefore, even a user who is unfamiliar with the operation can operate without distinguishing between the natural image and the document image, and the user can easily transport the image and improve the usability.

(1-5) Data Transmission (1-5-1) Format of Transmission Data CCITT applied to this video conference apparatus 1,
H. The format defined in 221 is defined according to the transmission rate, and all transmit audio data or the like in units of 125 [μsec] continuous frames. In other words, this format defines the channel of each line as B channel when using multiple lines of transmission speed 64 [kbps], and defines the channel of H ₀ channel when using multiple lines of transmission speed 384 [kbps]. Transmission rate 1536
When a line of [kbps] or 1920 [kbps] is used, it is defined as H ₁₁ channel and H ₁₂ channel, respectively.

In this format, in each channel, 16 frames continuously form one multi-frame, and further two multi-frames continuously form a sub-multi-frame, and this sub-multi-frame is a unit of eight. To form one channel continuously and cyclically. Of these, as shown in FIG. 31, in the B channel, serial data of 8 bits is continuously formed for 10 [msec] at a period of 125 [μsec], and one frame of data is formed. On the other hand, each 8-bit sequence is represented by a sub-channel.

Of these, the eighth sub-channel is called a service channel (SC), and when transmitting image data of a moving picture and audio data, a frame synchronization signal (F) is used.
AS), bit rate allocation signal (BAS), encryption control signal (ECS), and remaining capacity. Of these, the encrypted control signal is assigned to the 17th to 24th bits of the service channel as required so that it can be used as the control code when transmitting the encrypted data.

On the other hand, the bit rate allocation signal is allocated to the 9th to 16th bits of the service channel,
It is designed to represent the structuring when data is transmitted using multiple channels, so that a data transmission device that transmits this kind of data can reliably receive the transmitted data on the basis of this bit rate allocation signal. It is designed to be able to do. The bit rate allocation signal can also be used for control and notification.
On the other hand, the frame synchronization signal is assigned to the first to eighth bits of the service channel, the multi-frame,
It is assigned to sub-multi-frame and frame identification data and line identification data, so that it is possible to correct the time lag between channels when data is transmitted using multiple channels, and the data in each frame is also corrected. The bit boundary is correctly detected.

Thus, when data is transmitted using the B channel, the video conference apparatus 1 connects as many lines as desired within a range of up to 6 lines, and 64 [[ [kbps] data is transmitted, and as a whole, it can be easily connected to an ISDN line or the like to easily perform data transmission at various transmission speeds.

On the other hand, as shown in FIG. 32, the H ₀ channel is formed so that one frame corresponds to 6 frames of the B channel, and is 48 bits (8 bits × 6) in a period of 125 [μsec]. ) Serial data is 10 [mse
c] One frame of data is continuously formed, and each 48 bit × 6 bit string is represented by a sub-channel. Further, the H ₀ channel allocates the 8th sub-channel to the service channel, and allocates the frame sync signal from the 1st bit to the 8th bit of this service channel and the bit rate allocation signal from the 9th bit to the 16th bit. .

As a result, the H ₀ channel can be connected to a plurality of lines to transmit desired data as in the case of the B channel, and in the case of the video conference apparatus 1 of this embodiment, a maximum of 2 lines can be connected. It is designed to get you. On the other hand, H ₁₁ channel and H ₁₂ channel are H ₀
As in the case of the channel, one frame is formed so as to correspond to 24 frames and 30 frames of the B channel, respectively, and serial data of 192 bits and 240 bits at 125 [μsec] cycles are consecutively formed for 1 [msec]. Frame data is formed, and 1536 [kbps] and 1920 [kb
The data can be transmitted at a transmission rate of [ps].

For each frame, the video conference device 1
Allocates areas for moving image data, audio data, low-speed transfer data (hereinafter referred to as LSD data), and high-speed transfer data (hereinafter referred to as HSD data), and switches this area according to the operation mode. The image data of a natural image, a document image, line drawing data, and the like are transmitted by. That is, the video conference apparatus 1 allocates the natural image, the document image, and the line drawing data to the HSD data for transmission, and allocates the data of the personal computer or the like input via the external bus IF circuit 50 to the LSD data. Note that the video conference apparatus 1 is adapted to transmit control commands for drawing, control commands for switching operation modes, etc. using bits below the bit rate allocation signal of the eighth sub-channel.

As shown in FIG. 33, this data area switching is performed by H.264 when data is transmitted using two B channels. Areas for audio data and moving picture image data (represented by video) are allocated according to the format defined by 221 and the remaining areas are switched according to user operations and control commands sent from the call target. In this case, the symbol CPU represents data transmitted and received between the system controller 46 and the system controller of the call target (FIGS. 33A to 33C). On the other hand, as shown in FIG. 34, when data is transmitted by using three B channels, the H.264 standard is used. According to the format specified in 221, audio data and moving image data are assigned to the first and second lines (represented by 1B and 2B), and the remaining lines (represented by 3B) are image data or HSD data. (FIGS. 34 (A) and (B)).

Further, as shown in FIG. 35, when data is transmitted using 6 channels of the B channel, H.264 / AVC is used. The first and second lines 1B according to the format specified in 221
And 2B are assigned audio data and moving image data, and HSD data is assigned to the remaining lines (see FIG. 35).
(A) and (B)), and in the case of H ₀ channel, H ₁₁ channel, and H ₁₂ channel, data is similarly assigned. As a result, the video conference apparatus 1 can switch the operation mode as necessary and can transmit various data.

By the way, when a plurality of data communication lines of this type are used, the lines may be connected to the call target via different routes when the lines are congested. That is, one of the plurality of lines may be connected via a submarine cable, and the other line may be connected via a geostationary satellite. Even if a line is connected between the two, there are also cases where the geostationary satellite on the Indian Ocean and the geostationary satellite on the Atlantic Ocean are sequentially connected. Therefore, when data is transmitted using a plurality of lines, the data transmitted from the call target may have a large phase shift between the lines.

On the other hand, H.264. The 221 can correct a phase shift between channels using a frame synchronization signal when transmitting image data of a moving image and audio data. However, when transmitting data other than moving image data and audio data, it is premised that independent data is transmitted for each line, and thus there is a feature that the frame synchronization signal and the like are not specified.

Therefore, when the image data of the document image is assigned to the HSD data and transmitted through a plurality of lines as in the video conference apparatus 1 of this embodiment, it becomes difficult to correct the phase shift, and the line itself is changed. It may be difficult to identify, and the correct document image may not be reproduced. Therefore, in this embodiment, even when transmitting data other than moving image data and audio data, a frame synchronization signal, a bit rate allocation signal, an encryption control signal are transmitted as in the case of transmitting moving image data and audio data. To form a frame.

As a result, even when various data other than moving image data and audio data are transmitted using a plurality of lines, the phase shift can be corrected with certainty, and the transmitted lines can be identified to make the correct data. Can be restored.

(1-5-2) Multiplexing Circuit (1-5-2-1) Generation of Multiplexed Data By the way, when various lines are connected in this way, the video conference apparatus 1 responds to the line to be connected. Therefore, it is necessary to switch the transmission rate of the data to be transmitted in the range of 64 [kbps] to a maximum of 1920 [kbps]. On the other hand, the video conference device 1
It is necessary to switch the data mapping of each frame according to the operation mode to multiplex image data, audio data and the like. In this case, if the frequency of the clock of the multiplexing process is switched according to this transmission speed,
Therefore, the configuration becomes complicated and the time required for processing increases.

Therefore, in this embodiment, the video conference apparatus 1 can multiplex image data and the like using a single frequency clock by forming a time slot and multiplexing the data to be transmitted. Therefore, the overall configuration can be simplified.
That is, as shown in FIG. 36, the multiplexing circuit 49 applies the bit clock and the octet clock CK1 from the line interface circuit 48 to the reference clock switching circuit (reference CLK switching) 60, where the address decoder 6
The operation of the reference clock switching circuit 60 is switched by the output data of 1.

As a result, the multiplexing circuit 49 drives the PLL circuit 62 with the output signal of the reference clock switching circuit 60, whereby even when a line of various transmission speeds is connected, a predetermined frequency synchronized with the bit clock of this line. Generates the clock CK. Here, in the case of this embodiment, the frequency of this clock CK is selected to be 2048 [kHz], which is 32 times the bit channel 64 [kHz] of the B channel.
To maintain the clock frequency required for the multiplexing process at a single frequency.

That is, as shown in FIG. 37, the multiplexing circuit 49 operates by using this clock CK as a reference, so that 32 time slots TS1 to TS32 are continuously arranged so as to be continuous for 125 [μsec]. 8 bits of data corresponding to one octet of each frame of the B channel is allocated to each of the time slots TS1 to TS32. As a result, when the B-channel is connected to six lines, the multiplexing circuit 49 makes the time slot TS1.
First to sixth time slots TS1 to TS6 of TS32
Image data or the like is mapped to the TS 6 in units of 8 bits and multiplexed to generate one serial data, and the serial data is sequentially switched to each line to be output, whereby the image data and the like subjected to the multiplexing process are predetermined. Switch to the line and output.

On the other hand, in the case of H ₀ channel, FIG.
As shown in FIG. 8, the multiplexing circuit 49 assigns the first to sixth time slots TS1 to TS6 to the first channel by sending 48 bits of data for a period of 125 [μsec]. , And the subsequent seventh to twelfth time slots TS7 to TS12 are allocated to the second channel. In this case, the multiplexing circuit 49 uses the time slot T
Data is serially mapped to S1 to TS12 in 8-bit units to generate one serial data, and this serial data is sequentially switched to each line and output in the same manner as in the case of the B channel, whereby the multiplexed image is obtained. Outputs data etc. to a predetermined line. Further H ₁₁ Channel and H
_In the case of ₁₂ channels, the multiplexing circuits 49 are respectively the first
~ 24th time slot TS1 to TS24 and 1st to 1st
30 time slots TS1 to TS30 are assigned to the lines to generate serial data by mapping the image data and the like, and the serial data is output to the line to output the multiplexed image data and the like.

That is, the multiplexing circuit 49 is 125 [μsec.
] Time slots TS1 to TS3 during the period
2 is formed, and the data transfer rate of the data output to the line is switched by allocating the data to the time slots TS1 to TS32 in units of 8 bits in accordance with the transmission rate of the data output to the line and generating one serial data. In this case, the time slot occupied by the data is switched to switch the data transfer rate, whereby the data transfer rate can be easily switched by driving with a single clock CK. Therefore, in the video conference apparatus 1, the entire configuration can be simplified and downsized accordingly.

Therefore, the timing generation circuit 63 generates a reference signal for fetching data in each time slot with reference to the clock CK having the frequency of 2048 [kHz], and based on this reference signal, the speed conversion circuit 64, It controls the operations of the data time division circuit 65 and the CRC calculation circuit 68. On the other hand, the data time division circuit 65 has a memory space for forming the above-mentioned time slot, and sequentially captures image data and the like based on the mapping data DMAP output from the mapping memory 66 to perform a mapping process. As a result, moving image data or the like is sequentially assigned to the time slot to generate multiplexed serial data.

At this time, the mapping memory 66 switches the mapping data DMAP based on the control data output from the address decoder 61, whereas the address decoder 61 responds to the control command output from the system controller 46. Switches lever control data. As a result, the multiplexing circuit 49 switches the mapping of the data time division circuit 65 according to the connected line and in response to the operation mode of the video conference apparatus 1.

The data generation circuit 67 inputs the data of the frame synchronization signal and the bit rate allocation signal from the system controller 46 and outputs the data to the data time division circuit 65 at a predetermined timing, whereby the data is generated at a predetermined position corresponding to the service channel. Map the frame synchronization signal and bit rate allocation signal. The data time division circuit 65 is
The clock CLK is sent to the audio data processing section 18 and the encoder / decoder section 11 at the timing of mipping audio data and image data, respectively.
The audio data processing unit 18 and the encoder / decoder unit 11 output the audio data and the image data to the data time division circuit 65 on the basis of this clock CLK.

On the other hand, the speed conversion circuit 64 is composed of a random access memory circuit, and the image data processing unit 1
4. Line drawing data DW input from the external bus interface circuit 50, image data D2 of natural images and document images, etc. are input as HSD data and LSD data, the transmission speed is converted, and mapping of the data time division circuit 65 is performed. Output at the timing of. At this time, the timing generation circuit 63 switches the operation of the speed conversion circuit 64 based on the output data of the address decoder 61, thereby mapping output of the HSD data and the LSD data to the corresponding time slot.

The data time division circuit 65 maps the data necessary for the time slot in this way, and at the same time, the data output from the clock output from the timing generation circuit 63 is used as a reference for the 1st to 32nd octet numbers. The data mapped in the order of time slots are sequentially output cyclically. The CRC calculation circuit 68 takes in the output data and generates a CRC error correction code which is a cyclic code, outputs the error correction code to the data generation circuit 67 via the bus BUS and the system controller 46, and the data generation circuit 67. When the data of the frame synchronization signal and the bit rate allocation signal are mapped to the data time division circuit 65, the error correction code is also mapped.

Thus, the multiplexing circuit 49 can switch the operation timing of the CRC calculation circuit 68 according to the line to generate the error correction code, and can drive the CRC calculation circuit 68 at a single frequency. The entire configuration can be simplified accordingly. Incidentally, this CRC error correction code is generated and processed by utilizing the free time of the time slot to which the data is not assigned.

As a result, the video conference apparatus 1 is configured to form 32 time slots for a maximum of 30 necessary time slots to secure a vacant time, and to effectively use this vacant time. Even when a CRC error correction code is generated and the transmission rate is switched, data processing can be performed with a simple configuration as a whole. The channel separation circuit 70 switches the output data of the data time division circuit 65 to a channel corresponding to the line and outputs it. The channel switching circuit 71 switches the output data of the channel separation circuit 70 to the channel set by the user. At this time, the transmission rate of the output data is converted into the transmission rate of each channel and output.

As a result, the multiplexing circuit 49 multiplexes the image data and the like at a predetermined bit boundary to generate multiplexed data DMU, and outputs this multiplexed data DMU from the line interface circuit 48. At this time, the multiplexing circuit 49 is configured to switch the mapping by switching the mapping data DMAP output from the mapping memory 66, whereby the mapping of moving image data, HSD data, etc. is switched according to the operation mode. It is designed to get you.

Further, the mapping memory 66 has first and second memory spaces so that the mapping can be switched quickly in accordance with the switching of the operation mode. By switching and switching the output of the mapping data DMAP, the mapping can be switched.

(1-5-2-2) Separation of Multiplexed Data On the other hand, the multiplexed circuit 49 transmits the multiplexed data transmitted from the call target and input through the line interface circuit 48. Contrary to the time, this multiplexed data is assigned to a time slot to generate one serial data, which is then separated into each circuit block and output, whereby even when the multiplexed data DMU is separated, a single frequency is generated. It is designed so that it can operate with the clock and simplify the overall configuration. Note that the multiplexing circuit 49 forms a time slot in the same manner as in the case described above with reference to FIGS. 37 and 38 when 6 lines of B channel are connected, and when 2 lines of H ₀ channel are connected.

Thus, as shown in FIGS. 39 and 40, when one line is connected to the B channel and the H ₀ channel, respectively, the first time slot TS1 and the first to sixth time slots TS1 to TS6 are multiplexed. As shown in FIGS. 41 and 42, when the H ₁₁ channel and the H ₁₂ channel are connected as shown in FIGS. 41 and 42, the first to 24th time slot TS1 are respectively assigned. ~ TS24 and first
~ Multiplexed data DMU is allocated to the thirtieth time slots TS1 to TS30 and separated into image data and the like.

(1-5-2-3) Principle of phase shift detection By the way, when data is transmitted using a plurality of lines, it is necessary to correct the phase of the data transmitted from the call target with a large shift between the lines. There is. For this purpose, a method may be considered in which a predetermined reference is provided, the phase shift between this reference and each line is detected, and the phase shift is corrected, but this method complicates the overall configuration.

Therefore, as shown in FIG. 43, the multiplexing circuit 49 corrects this kind of phase shift in the phase shift correction circuit 80, and then forms a time slot in the mapping circuit 81 to separate the data.

Here, as shown in FIG. The frame synchronization signal defined by reference numeral 221 is the second frame of the even frame.
It is specified that the data of the value "0011011" is assigned to the eighth octet, whereby a continuous data string is sampled at a cycle of 8 bits and the value "001101" is sampled.
By detecting the bit pattern of "1", it is possible to detect the timing of the frame synchronization signal of the even frame. As a result, H. The frame synchronization signal 221 is adapted to detect the byte boundary of the data in each frame based on this timing detection result. Further, for example, this timing detection result is obtained between two lines, and this timing detection signal is detected. Based on the result, the phase is corrected so that the maximum phase deviation of 10 [msec] can be corrected.

Further, as shown in FIG. 45, when the frame synchronization signals are arranged in units of multi-frames, H.264. 221
The frame synchronization signal defined by the
The octet has the value "00" from the first sub-multiframe.
1011 ", so that the first octet of the service channel is sampled between consecutive frames to detect this value" 001011 "so that the timing of each frame in the multiframe can be detected. Has been done.

Accordingly, H. The frame synchronization signal defined by reference numeral 221 is adapted to obtain the timing detection result between, for example, two lines, and perform phase correction based on the timing detection result to correct a phase shift of up to 80 [msec]. There is. Furthermore, H. In the frame synchronization signal 221 specified, the first octet of the even frame continues from "N1, N2, N3, N4" from the first sub-multiframe, and the value specified by the data of 5 bits is the multiframe. It is regulated to switch in a cyclical manner every time.

As a result, the H. The frame synchronization signal defined by reference numeral 221 is made to be able to detect the timing of the multi-frame among 16 multi-frames by detecting the value by detecting the first octet of this even-numbered frame, and thereby the maximum It is designed to be able to correct the phase shift of 1, 28 [sec]. In fact, in this type of data communication, if the phase shift of 1,28 [sec] at the maximum can be corrected, the phase shift can be surely corrected.

Based on this phase shift detection principle, the multiplexing circuit 49 detects the phase shift between a plurality of lines and corrects the phase shift. Note that, hereinafter, the phase shift detection data assigned to this frame synchronization signal is called FAW.

(1-5-2-4) Correction of Phase Shift In FIG. 43, the multiplexing circuit 49 inputs the multiplexed data DMU output from the line interface circuit 48 to the data conversion circuit 82, where it is predetermined. Output the channel data of 8 bits so that they continue in a predetermined order in units of 8 bits.
This forms a time slot and converts the input data of each line into serial data. At this time, when a plurality of lines are connected, the data conversion circuit 82 forms a clock with a duty ratio of 50% based on one of the lines, and samples the remaining lines based on this clock. As a result, the data of each line is fetched with this clock as a reference.

Further, at this time, the conversion circuit 82 detects the timing at which the logical levels of the remaining lines switch and the timing at which the data of each line is sampled. If this timing is close, the clock falls. The sampling timing is switched between the rising edge and the rising edge so that the transmitted data can be surely taken in. That is, the data transmitted via this type of line is not out of sync between the lines,
There is a characteristic that the phases are deviated. By thus switching the timing between the falling edge and the rising edge of the clock and capturing the data, it is possible to set the timing once and reliably capture the data.

Incidentally, in the case of correcting such a phase shift, it is possible to
Although it is possible to match the phase of the data of each line to one clock, this method has a drawback that the overall configuration becomes complicated. Thus, in the case of this embodiment, it is possible to reliably capture the data of each line with a simple configuration. it can. Further, when this data is taken in, the conversion circuit 82 detects the byte boundary when the line for taking in the data is an ISDN line, so that the bit sequence is corrected beforehand and taken in here.

On the other hand, the FAW detection circuit 83 detects FAW from the continuous data string in units of 8 bits,
The counter 84 drives a predetermined ring counter for each line based on the FAW detection result. As a result, the multiplexing circuit 49 detects the octet number and bit boundary of the data input through each line in this counter circuit.

The bit switching circuit 85 corrects and corrects the output data of the data conversion circuit 82 based on the detection result of the bit boundary so that the data of the same protect number for each line will continue in units of 8 bits. The data is stored in the buffer memory 86. At this time, the buffer memory 86 sequentially inputs the data based on the detection result of the opt number, and outputs the sequentially stored data with reference to the reference data input through the selector 87. , The data of the same opt number is output continuously in units of 8 bits, and the phase shift between the channels is further corrected.

At this time, the buffer memory 86 inputs / outputs data in time slot units to correct the phase shift in the form of 8-bit parallel data, and the parallel / serial conversion circuit (P / S) 88 converts the original serial data. Convert to format. The error correction circuit 89 performs error correction processing on the bit rate allocation signal and the like, and the CRC error correction circuit 9
0 performs error correction processing on the entire data based on the error correction code added at the time of transmission.

At this time, the error correction circuit 90 performs the error correction processing by using the idle time of the time slot to which the data is not allocated, whereby the video conference apparatus 1 switches the transmission speed and transmits / receives the data. Even when it does, the error correction processing can be performed with a simple configuration. The BAS detection circuit 91 detects the bit rate allocation signal and outputs it to the system controller 46, so that the system controller 46 can receive the control command and the like sent from the call target.

The mapping circuit 81 selectively outputs the output data of the parallel-serial conversion circuit 88 based on the mapping data output from the system controller 46, whereby the multiplexing circuit 49 transmits the multiplexed data. The audio data and the like are separated and output to the corresponding circuit blocks. At this time, the multiplexing circuit 49 converts the transmission speed of the user data output via the external bus interface circuit 50 or the like via the speed adjustment circuit 92 and outputs the converted data.

As shown in FIG. 46, the FAW detection circuit 83
Receives the output data DT of the data conversion circuit 82 in a serial / parallel conversion circuit (S / P) 95, and first receives the first data.
The 8-bit data assigned to the time slot is converted into parallel data and output. Register (R) 9
6A to 96F are connected in series, and 8 bits of parallel data are sequentially transferred in a cycle in which the first time slot is repeated. The pattern detection circuit 97 outputs the output data of the serial / parallel conversion circuit 95 and the register 96A to 96F.
Output data of 96F is input in parallel.

As a result, the pattern detection circuit 97 has the first
7 bytes of continuous 8-bit data are cut out from the data assigned to the channel and input, and it is detected whether or not each of the 7-byte bits is continuous with the value "00110101". That is, the pattern detection circuit 97, after cutting out the data string of 8 bits × 7 bytes, detects the timing that coincides with the value “0011011” of the second to eighth octets of the even frame assigned to the frame synchronization signal.

When the pattern detection circuit 97 detects this timing, the pattern parallel to the serial-parallel conversion circuit 95 and the register 96A is applied to the mask of 8 systems of the value "0011011"
By inputting the output data of ~ 96F for each bit string and obtaining the comparison result, FAW can be simultaneously performed by 8 systems.
Is detected, and the output data of 8 bits is fallen so as to correspond to the matched bit, and the detection result DF
Output AW. As a result, the pattern detection circuit 97
FAWs are detected simultaneously in parallel for each of the first to eighth bits of one time slot, and the FAWs can be detected easily and reliably in a short time.

By the way, in this kind of image data and audio data, when a frame is formed as described above with reference to FIG. 44, 7-bit data arranged in the vertical direction may be continuous with the same value as the FAW pattern. Therefore, there is a feature that it is not possible to determine whether or not a correct FAW can be detected by simply detecting the bit pattern of this value "00110101". Therefore, in this embodiment, the pattern detection circuit 97 outputs the 8-bit output data, which is the detection result, to the FAW determination circuits 98A to 98H, one bit at a time, and determines whether or not the FAW detection result is correct.

As shown in FIG. 47, the FAW determination circuit 98
A to 98H are formed with eight circuits with the same circuit configuration so as to correspond to the detection result DFAW. The respective bits DFAW1 to DFAW8 of the FAW detection result DFAW are input to the 80-ary counter 99, and these bits DFAW1 to DFAW are input.
In order to correspond to No. 8, each bit FAW8 (FAW81 to FAW88) of the output data of the latch circuit 95F is input to the selector 100. The 80-adic counter 99 is formed of an 80-adic ring counter.
When the logic level of FAW8 falls, a clock CK with a frequency of 8 [kHz] synchronized with the time slot formation cycle.
The counting of 80 is started, and when the count value reaches the value 80, the carry signal CARRY is raised.

As a result, the 80-ary counter 99 is set to FAW.
When the detection result DFAW is obtained, the data of the same time slot is counted from the corresponding input data in units of 80 bits, and the count result is output as the carrier signal CARRY. The binary counter 101
It is formed by a binary counter that operates on the basis of the clock CK80, and by counting the carry signal CARRY, the logical level of the output rises when the period of two frames elapses from the timing when the FAW detection result DFAW is obtained. As a result, FAW decision circuits 98A to 98
When the FAW detection result DFAW1 is correct, H can obtain the FAW detection result DFAW1 again at the timing when the logical level of the binary counter 101 rises, and also at the timing when the logical level of the carrier signal CARRY rises, an odd frame, a service channel, Data of octet number 2 can be detected.

Here, H. According to the regulation of 221, the data of the odd number frame, the service channel, and the octet number 2 are regulated to be always held at the value "1" (FIG. 45). Therefore, when the FAW detection result DFAW1 is correct, the carrier signal is output. When the logic level of CARRY rises, the input data FAW81 to FA of the selector 100
W82 will also stand up at the same time. As a result, the selector 100 alternately outputs the FAW detection result DFAW1 and the input data FAW81 to FAW82 of the selector 100 at the timing when the logical level of the binary counter 101 is switched, whereby the correct FAW detection result DFAW1 is output.
Is obtained, the selection result in which the logic level is continuously held at the value “1” is output.

When the logic level of the selection result is held at the value "1" 6 times in succession, the 6-stage protection circuit 103 judges that the correct FAW detection result DFAW1 is obtained and detects it by the system controller 46. Output the result. In fact, H. When the FAW bit pattern defined by 221 is continuous for 6 frames, it can be determined that a correct pattern can be reliably detected, and thus the frame synchronization signal can be reliably detected.

On the other hand, when the logic level of the selection result does not rise 6 times in succession, the 6-stage protection circuit 103
A reset signal is output to the 80-ary counter 99 and the counter 101, whereby the FAW detection circuit 83 restarts the FAW detection process for this bit again. Thus, in the case of this embodiment, 8 systems F are simultaneously connected in parallel.
AW is detected and FAW determination circuits 98A to 98 are provided for each system.
By judging whether the FAW detection result is correct with H,
One FAW detection result DFAW1 (DFAW2-DFA
Even if W8) is wrong, it is simultaneously judged in parallel whether or not the correct FAW detection result is obtained for another bit string, which makes it possible to easily and surely detect FA in a short time.
W can be detected.

When the FAW detection result is obtained in this way, the system controller 46 activates the operation of the counter 84. Here, the counter 84 has six systems having the configuration shown in FIG. 48, and detects the octet number of each line in each system.

That is, the six-system counter 84 receives the carrier signals CARRY1 from the eight-system FAW detection circuits 83.
8 to 8 are received by the selector 105, and the carrier signal C output from the FAW detection circuit 83 of one system is output based on the selection signal output via the system controller 46.
Select and input ARRY1-8. For this reason, when the correct FAW detection result is obtained for the first time slot, the system controller 46 selects and inputs the carrier signal CARRY from the FAW detection circuit 83 which has obtained the correct detection result to the first counter 84. , And outputs a selection signal SEL via a predetermined reference signal generation circuit.

In this way, the carrier signal CARRY1
When is selected, the counter 84 operates the clock CK80 having a frequency of 8 [kHz], which is a hexadecimal ring counter 10.
6 is loaded with this carrier signal CARRY1. As a result, the counter 84 is configured to generate a count value corresponding to the octet number in sub-multiframe units by the ring counter 106.

The serial / parallel conversion circuit 107 converts the time slotted serial data DT, which is the output data of the data conversion circuit 82, into parallel data and outputs it. The selector 108 starts its operation in response to the selection signal SEL, and selectively outputs one time slot data from this parallel data so as to correspond to the time slot for which the FAW detection result is obtained.

The detection circuit 109 is the ring counter 106.
Based on the count result of 1), 1-bit data for each frame is selectively input from the output data of the selector 108, whereby the data of octet number 1 of the service channel is selectively input (FIG. 44). Further, the detection circuit 109 monitors the data of this octet number 1 obtained from the odd-numbered frame, and the value "00101" is detected here.
1 "is detected, sub-multiframe (SM
F) Reset the counter 110 (FIG. 45).

The sub-multi-frame counter 110 is formed of a hexadecimal ring counter for counting the count result of the counter 106, thereby incrementing the count value in frame units and resetting the count value in a multi-frame cycle. Accordingly, the sub multi-frame counter 110 outputs the count value of each frame in units of multi-frame.

Further, the detection circuit 109 detects the data of octet number 1 in the first to fifth sub-multiframes and even frames, and outputs this detection result in M at a predetermined timing.
Output to the F counter 111. The MF counter 111
It is formed by a hexadecimal ring counter that operates based on the count result of the sub-multiframe counter 110,
By loading and operating the detection result of the detection circuit 109, the data "N" of an even frame and octet number 1
The count value corresponding to "1, N2, N3, N4" is output.

As a result, the counter 84 detects the octet number detection result BWN in units of 16 multiframes for the line to be detected, based on the FAW detection result.
It is designed to output. Further detection circuit 109
Detects the data of octet number 1 in the sixth sub-multiframe and even frame and the data "L1, L2, L3" of octet number 1 in the seventh sub-multiframe, even frame and odd frame (FIG. 45). The detection result is output to the CH number detection circuit 112 formed by the latch circuit at a predetermined timing.

Here, H. The format 221 allocates the channel number of the line to the data “L1, L2, L3” and transmits the data.
In addition to holding the channel detection result, the channel number detection result is output together with the count values of the counters 106 to 112.

Further, the detection circuit 109 includes a counter 106
Based on the bit allocation detected at, even frame, service channel, octet number 2-8
Data is output to the front / rear protection circuit 113, and the front / rear protection circuit 113 outputs this data as the value “001101”.
It is determined whether it is "1". If a negative result is obtained here, it is considered that the synchronization is lost in this case, and therefore the front-rear protection circuit 113 outputs the out-of-synchronization signal IS to the system controller 46.

That is, the system controller 46, once the counters 106 to 111 and the CH number detection circuit 112 start outputting the detection result BWN of the octet number in units of 16 multiframes, the selection signal SE.
The L is switched to disconnect the counter 84 from the FAW detection circuit 83. As a result, the system controller 46
The detection target of the AW detection circuit 83 is switched to the subsequent second time slot, and at the same time, the FAW is set to the counter 84 of the second system.
The selection signal SEL is output to the counter 84 of the second system so that the detection result can be output.

On the other hand, the first-system counter 84 from which the FAW detection circuit 83 is separated starts to operate at the timing which is once synchronized and continues to count the clock CK80 which is synchronized with the time slot forming cycle (that is, The counters 106 to 111 are self-propelled), and the detection result BWN of the octet number can be continuously output. As a result, the video conference device 1 is
The detection target of the AW detection circuit 83 is sequentially switched to obtain the FAW detection result, and the entire structure can be simplified accordingly.

That is, the video conference apparatus 1 has a maximum number of 6 by connecting the largest number of lines in the B channel.
The phase shift may be corrected for each of the two time slots. By the way, in the H ₀ channel, when two lines are connected, the phase shift can be detected for two time slots, and all the phase shifts can be corrected based on this detection result. In the H ₁₁ and H ₁₂ channels, respectively, It can be seen that there is no need to correct the phase shift due to the transmission by one line. From this, it is understood that the phase shift can be detected only by preparing the counter circuits of 6 systems.

By the way, in this kind of line, bit deviation may occur during communication due to an abnormality of the transmitting side device, and in this case, the self-running counters 106-111.
It will be out of synchronization with the count value of. For this reason, the phase shift correction circuit 80 detects this synchronization shift in the front-back protection circuit 113, and when the synchronization is lost, switches the detection target of the FAW detection circuit 83 and outputs the FAW detection result to the counter 84 which is out of synchronization. Output the selection signal SEL so that the FAW can be detected again to resynchronize, and the octet number detection result BWN can be obtained.
It is designed to output.

As shown in FIGS. 49 and 50, the bit switching circuit 85 is formed by six systems of bit shift correction circuits 115A to 115F corresponding to the systems of the counter 84, and these bit shift correction circuits 115A to 115F are provided.
The output data DT of the data conversion circuit 82 is input to (FIG. 50 (A)). Bit shift correction circuits 115A to 115F
Are formed by two 8-bit latch circuits,
8-bit data D of the corresponding time slot
T is alternately latched by two systems of 8-bit latch circuits, and the latch result is cut out and output at a predetermined timing based on the output data of the system controller 46.

Here, when the counter 84 obtains the octet number detection result BWN, the system controller 46 inputs the FAW detection result DFAW of the corresponding line,
The FAW detection result DFAW is output to the corresponding bit shift correction circuits 115A to 115F. As a result, the bit shift correction circuits 115A to 115F cut out the latch results based on the detection results of the counter 84 and the FAW detection circuit 83 and output them, whereby the data of consecutive same octets from the sequentially input output data DT are output. The array of the data DT is converted and output so as to be continuous within the time slot (FIG. 50 (B)). For example, in this case, the data "1" and "2" of the fifth channel and the data "3" to "8" of the fifth channel of the subsequent time slot are combined to form one time slot. Recognize.

As a result, in the video conference apparatus 1,
By connecting up to 6 lines, the phase shift correction circuit 8
0 is a 6-system bit shift correction circuit 115A to 115F.
Then, the phase shift of each line is corrected so that the data of the same octet continues in each time slot. The bit shift correction circuits 115A to 115F output the output data of the latch circuit in the form of parallel data at a timing synchronized with the input data DT. In FIG. 50 (B), the input data DT is output. The output data DT1 is represented in the form of serial data in a substantially linear form in order to show the correspondence with.

Bit shift correction circuits 115A to 115F
Outputs the output data DT1 to the buffer memory 86, and the address selector 116 outputs the output data DT1.
The corresponding octet number detection result BWN and channel number detection result are synchronized with the buffer memory 8
Output to 6. As a result, the buffer memory 86 sequentially stores the input data DT1 by using the octet number detection result BWN and the channel number detection result as address data.

On the other hand, the system controller 46
Inputs the octet number detection result BWN via the latch circuit 117 and detects a time slot serving as a reference for correcting the phase shift. Here, in the case of correcting the phase shift for the six lines, the most delayed time slot is detected and the time slot is set as a reference.

However, when the most delayed time slot is detected from the six time slots based on the octet number detection result BWN in which the values sequentially and cyclically change in this way, the processing becomes complicated. Therefore, in this embodiment, the system controller 46 inputs the octet number detection result BWN of two systems via the latch circuit (R) 117, and detects the comparison result of the octet number detection result BWN. As a result, the system controller 46 detects the delayed line from these two time slots, and then inputs the octet number detection result BWN for this delayed line and one of the remaining four lines and outputs the comparison result. To detect.

Thus, the system controller 46
By sequentially fetching the octet number detection results BWN of the two systems and detecting the comparison result, this processing is repeated up to 5 times to detect the most delayed line. Thus, the latch circuit 117 is adapted to be able to take in the two octet number detection results BWN simultaneously. Further, the system controller 46 outputs a switching signal to the selector 118, and selectively outputs the octet number detection result BWN of the most delayed line to the address selector 116.

As a result, the address selector 116 outputs the most delayed octet number detection result BWN as a read address to the buffer memory 86, whereby the buffer memory 86 sequentially outputs the stored data and corrects the phase shift. At this time, address selector 1
16 outputs the data of the channel numbers in which the sequential values circulate to the buffer memory 86 as the address data so that the channel numbers are consecutive.

As a result, the phase shift correction circuit 80 corrects the phase shift between the lines and rearranges and outputs the array of the data DT so that the channel numbers are consecutive (FIG. 50 (C)), and the parallel serial data is output. The conversion circuit 88 converts it to the original serial data format and outputs it. Thus, by allocating the data of each line to the time slot for processing, the processing can be simplified even when the phase shift is corrected.

Further, by assigning a frame synchronization signal or the like to the HSD data and transmitting the same, it is possible to correct the phase shift even for a document image or the like and receive it in a correct channel arrangement, and thereby the document image can also be correctly reproduced. You can

(1-5-2-5) Updating of mapping memory By the way, the mapping memory 66 and the mapping circuit 81 are updated.
By updating the mapping data respectively,
The data assigned to each frame is switched so that the video conference apparatus 1 can switch and transmit various data according to the operation mode. In order to switch this data, it is necessary to update the mapping memory 66. If this updating process can be simplified, the system controller 46 can shorten the time required for this updating process, and the entire configuration can be reduced accordingly. It can be simplified.

Further, when the data is mapped to the time slot, or when the data is separated and output to each circuit block, the multiplexing circuit 47 refers to the mapping memory 66, and the reference work is simplified. If it can be realized, the entire processing time can be shortened by that amount, and the configuration can be simplified.

Therefore, as shown in FIG. 51, the mapping memory 66 includes the first and second mapping RAMs 120.
And 121, a memory space corresponding to the time slot is formed, an address space corresponding to the data array of each frame is formed in this memory space, and the mapping data is stored in this address space. As a result, as shown in FIG. 52, the mapping memory 66, in the case of transmitting data using two B channel lines, stores data indicating the type of data to be stored corresponding to the frames of the first channel and the second channel. Is stored as mapping data, and the data time division circuit 65 is configured to sequentially input audio data, moving image data, etc. designated by the mapping data data.

In FIG. 52, audio data is represented by the symbol A, moving image data is represented by the symbol V, and frame sync signal and bit identification signal data are represented by the symbols F and B, respectively. Further, the mapping memory 66 complementarily switches the switching circuits 122 and 123 at a predetermined timing, and sets the mapping RAMs 120 and 121 to the system controller 46 or the data time division circuit 65, respectively.
Thus, while the data time division circuit 65 is accessing one of the mapping RAMs 120 or 121 to refer to the mapping data DMAP, the mapping time DMAP of the other mapping RAM 121 or 120 is connected. Is being updated. As a result, the video conferencing apparatus 1 can switch the switching circuit 12
Switching the connection of 2 and 123 at a predetermined timing,
The operation mode can be easily switched.

As shown in FIG. 53, the mapping data DMAP is made up of 8-bit data, and the lower 6-bit data specifies the type of moving image data, audio data, or the like. That is, in the mapping data DMAP, when allocating audio data, only the least significant bit among these 6 bits is raised to the value 1, whereas when allocating moving image data,
Only the second bit that follows is raised to a value of 1.

In response to this, the data time division circuit 65
Select and input audio data, moving image data, HSB data, etc. based on the data of the lower 6 bits.
As a result, preset data is sequentially assigned to the time slot and output. Further mapping data DMA
P assigns the identification data BM to the highest bit D7,
This identification data BM switches the mapping data access operation of the data time division circuit 65.

That is, in the case of this embodiment, each frame is a subframe (FIG. 5) to which the same type of data is assigned.
2 corresponds to the first to seventh subframes)
And a subframe to which different data is assigned (corresponding to the eighth subframe in FIG. 52). As a result, the system controller 46 allocates the same type of data to the sub-frames to be subsequently read (that is, in this case, by accessing the mapping data so as to perform raster scanning, each of the first to the first).
This corresponds to the mapping data of the sixth sub-frame and the eighth sub-frame), and this identification data BM is raised to the value 1.

In response to this, the data time division circuit 65
Among the accessed mapping data DMAP, the mapping data DMAP corresponding to the octet number 1 is held. Further, the data time division circuit 65 detects the identification data BM when mapping the designated data, and when the identification data BM rises to the value 1, stops the access of the following mapping data DMAP, The data specified by the held mapping data DMAP is mapped.

In this way, the mapping memory 66
The number of times of access can be reduced step by step, the processing time can be shortened accordingly, and the capacity of the mapping memory 66 can be reduced, which simplifies and downsizes the entire configuration of the video conference apparatus 1. You can Further, if this is done, the mapping data DMAP that cancels this access.
With respect to the above, since it is not necessary to write to the mapping memory 66, the system controller 46 can complete the updating process of the mapping memory 66 in a short time, and the load on the system controller 46 can be reduced accordingly. .

On the other hand, the mapping circuit 81 (see FIG.
3), contrary to the data time division circuit 65, accesses the mapping memory to obtain the mapping data, separates the multiplexed data DT on the basis of the mapping data, and outputs to the corresponding circuit blocks 11, 18 and the like. Output the separated data. As a result, even when the received data is separated, it is possible to surely separate the original data with a simple configuration.

(2) Effects of the Embodiments According to the above configuration, when the display of the document image is switched, the command for switching the display of the document image is input and the command for switching the display of the document image is input from the target of the call. By responding to this command, the discrepancy between the document image and the line drawing input by the user can be effectively avoided, and thus even a user unfamiliar with the operation can easily perform the operation.

(3) Other Embodiments In the above-described embodiments, the case where line drawings are input while displaying the same document image with the call target has been described, but the present invention is not limited to this. For example, when data can be input and output between the main video conference device and its terminal device, when the document image can be input only from the main video conference device, the document image can be input only from the main video conference device. It can be widely applied when the display of images cannot be switched.

[0270]

As described above, according to the present invention, after the display switching data is transmitted to the call target, the display of the input image is switched in response to the response of the call target, and the display switch data is input from the call target. Then, by sending the response data, it is possible to effectively avoid the inconsistency of the line drawing input by the user displayed together with the input image, which simplifies and downsizes the overall shape and makes it unfamiliar to the operation. It is possible to obtain a data processing device that can be easily operated by the user.

[Brief description of drawings]

FIG. 1 is a front view showing a video conference apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration.

FIG. 3 is a block diagram showing an image input / output unit.

FIG. 4 is a block diagram showing an encoder / decoder unit.

FIG. 5 is a block diagram showing an image data processing unit.

FIG. 6 is a block diagram showing a main processing unit.

FIG. 7 is a block diagram for explaining the processing of the central processing unit.

FIG. 8 is a block diagram for explaining switching of buses.

FIG. 9 is a signal waveform diagram for explaining the operation.

FIG. 10 is a schematic diagram used to explain a telewriting operation.

FIG. 11 is a schematic diagram showing a mismatched state between the document image and the line drawing.

FIG. 12 is a schematic diagram showing a communication procedure for eliminating a mismatch between a document image and a line drawing.

FIG. 13 is a flow chart showing a processing procedure therefor.

FIG. 14 is a flowchart for explaining the screen control key processing.

FIG. 15 is a flowchart for explaining the screen control request processing.

FIG. 16 is a block diagram showing a peripheral circuit of an arithmetic memory.

FIG. 17 is a schematic diagram for explaining allocation of memory space in the case of a natural image.

FIG. 18 is a schematic diagram for explaining allocation of memory space in the case of a document image.

FIG. 19 is a schematic diagram for explaining memory allocation of a natural image.

FIG. 20 is a schematic diagram for explaining allocation of a memory of a document image.

FIG. 21 is a block diagram for explaining processing of a document image.

FIG. 22 is a schematic diagram for explaining the display of a document image.

FIG. 23 is a schematic diagram for explaining the conversion of binary data into multivalued data.

FIG. 24 is a schematic diagram for explaining enlarged display of a document image.

[Fig. 25] Fig. 25 is a schematic diagram for explaining PAL-NTSC image conversion.

FIG. 26 is a schematic diagram for explaining storage of image data of the FIFO.

FIG. 27 is a schematic diagram for explaining flickering reduction.

FIG. 28 is a schematic diagram for explaining the case where the flickering reduction is executed in two lines.

FIG. 29 is a block diagram for explaining input / output of a natural image.

FIG. 30 is a block diagram provided for explaining the display of a natural image.

FIG. 31 is a schematic diagram showing a structure of a B channel.

FIG. 32 is a schematic diagram showing a structure of an H ₀ channel.

FIG. 33 is a schematic diagram for explaining data transmission when two channels are used for the B channel.

FIG. 34 is a schematic diagram used for explaining data transmission when three B channels are used.

[Fig. 35] Fig. 35 is a schematic diagram for explaining data transmission when six channels are used for the B channel.

FIG. 36 is a block diagram showing the transmitting side of the multiplexing circuit.

[Fig. 37] Fig. 37 is a schematic diagram for explaining a time slot in the case of using 6 channels of the B channel.

FIG. 38 is a schematic diagram for explaining a time slot when two lines of H ₀ channel are used.

FIG. 39 is a schematic diagram for explaining a time slot when one channel of B channel is used.

FIG. 40 is a schematic diagram for explaining a time slot when one line of H ₀ channel is used.

FIG. 41 is a schematic diagram for explaining a time slot in the case of using an H ₁₁ channel.

FIG. 42 is a schematic diagram for explaining a time slot when using an H ₁₂ channel.

FIG. 43 is a block diagram showing the receiving side of the multiplexing circuit.

FIG. 44 is a schematic diagram used for explaining FAS.

FIG. 45 is a schematic diagram used for explaining FAS between the frames.

FIG. 46 is a block diagram showing a FAW detection circuit.

FIG. 47 is a block diagram showing a FAW determination circuit.

FIG. 48 is a block diagram showing a counter circuit.

FIG. 49 is a block diagram showing a bit switching circuit.

FIG. 50 is a schematic diagram for explaining a phase shift correction.

FIG. 51 is a block diagram showing a mapping memory.

FIG. 52 is a schematic diagram used for the description.

FIG. 53 is a schematic diagram showing mapping data.

[Explanation of symbols]

1 ... Video conferencing device, 3 ... Processor, 4 ... Monitor device, 6 ... Remote commander, 10 ... Image input / output unit, 11 ... Encoder / decoder unit, 12 ... Main processing unit, 14 ... Image data processing unit, 18 ... Audio processing unit, encoder / decoder, 35 ... Bus controller, 36 ... Still image processing circuit, 37 ... Binary image processing circuit, 38 ... Image interface circuit, 40 ... Arithmetic memory, 42 ... Image FIFO, 44 ... Drawing plane, 46 ... System controller, 49 ... Multiplexing circuit.

Claims (4)

[Claims] 1. A data processing device for displaying the same input image with a predetermined call target and displaying a line drawing together with the input image, wherein the call target or the predetermined image input means is used. Screen storage means for storing an input image, image display means for inputting the line drawing data from the call target and displaying the line drawing together with the input image, and image for inputting display switching data for switching the display of the input image The display switching means comprises switching information input means, switching data sending means for sending the display switching data to the call target, and display switching means for switching the display of the input image based on the display switching data. , After sending the display switching data to the call target, if a response is obtained from the call target, the input The data processing apparatus characterized by switching the display image. 2. A data processing device for displaying the same input image with a predetermined call target and displaying a line drawing together with the input image, wherein an input input through the call target or a predetermined image input means. Input the line drawing data from the screen storage means for storing the image and the predetermined line drawing data input means,
An image display means for displaying the line drawing together with the input image, a line drawing data sending means for sending the line drawing data to the call target, and a display of the input image based on display switching data input from the call target. When the display switching data is input from the call target, the line drawing data sending means stops sending the line drawing data to the call target and changes the display switching data to the display switching data. A data processing device, which sends out data to respond. 3. The line drawing data input means stops inputting the line drawing data when the line drawing data sending means stops sending the line drawing data, and the line drawing data sending means outputs the line drawing data. After the transmission is stopped, the line drawing data is restarted when a predetermined period of time has passed, and the line drawing data input means inputs the line drawing data when the line drawing data sending means restarts the line drawing data. The data processing device according to claim 2, wherein the data processing device is restarted. 4. The display switching means switches the display of the input image by enlarging, reducing, scrolling or rotating the input image based on the display switching data. The data processing device according to claim 2 or claim 3.