JPH06276407A - External synchronization device - Google Patents

Abstract

PURPOSE:To provide the external synchronization device configured inexpensively with less number of PLL circuits in which no out of synchronism takes place even when a phase of a horizontal synchronizing signal separated from a video signal is subject to fluctuation. CONSTITUTION:When a phase of a frequency signal DH2 outputted from a frequency divider 26 is dissident with a phase of a horizontal synchronizing signal DH1 separated from a video signal SV, a switch 54 is closed to allow switches 51, 55 to be thrown to the position (a). An oscillated frequency from an oscillator 52 is lower than a frequency 4fsc and the phase of the signal DH2 with respect to the phase of the synchronizing signal DH1 is being changed. After the phase of the signal DH2 is coincident with the phase of the synchronizing signal DH1, the switch 54 is opened to allow the switches 51, 55 to be thrown to the position (b). Since an oscillating signal from an oscillator 6 of a PLL circuit is frequency-divided to obtain the signal DH2, the state of the coincidence between the phase of the signal DH2 and the phase of the synchronizing signal DH1 is maintained even without use of an exclusive PLL circuit, and since the phase of the signal DH2 is not compared with the phase of the synchronizing signal DH1 after the coincidence between the phases, even when the phase of the synchronizing signal DH1 is fluctuated due to any cause, it does not give effect on the phase of the signal DH2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external synchronizing apparatus suitable for application when a karaoke character signal reproduced from CD-G software is inserted into a video signal for a background image.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a video system for inserting a karaoke character signal reproduced from CD-G software into a video signal for a background image to superimpose the karaoke character on the background image. At input terminal 1
The NTSC video signal SV supplied to the switch 2 is supplied to the fixed terminal on the a side of the changeover switch 2. Further, the video signal SV supplied to the input terminal 1 is supplied to the color burst separation circuit 3, and the color burst signal separated by this separation circuit 3 is supplied to the AND circuit 4 constituting the phase comparator.

An output signal of the AND circuit 4 is an amplifier and a low-pass filter (hereinafter referred to as "low-pass amplifier") 5
Is supplied as a control signal to the voltage controlled oscillator 6 via. The center oscillation frequency of this oscillator 6 is 4 fsc = 910 f
h (fsc is a color subcarrier frequency and fh is a horizontal frequency). The oscillation signal output from the oscillator 6 is frequency-divided by the frequency divider 7 and supplied to the AND circuit 4. The AND circuit 4, the low-pass amplifier 5, the oscillator 6 and the frequency divider 7 constitute a PLL circuit.

In this case, the pulse width of the output signal of the AND circuit 4 changes according to the phase difference between the color burst signal separated by the separation circuit 3 and the output signal of the frequency divider 7, and the oscillation frequency of the oscillator 6 is accordingly changed. Since it is controlled according to the phase difference, the frequency signal SSC1 of the same frequency is obtained from the frequency divider 7 in phase synchronization with the color burst signal.

The video signal SV supplied to the input terminal 1 is supplied to the sync separation circuit 8, and the composite sync signal separated by the sync separation circuit 8 is supplied to the horizontal / vertical sync separation circuit 9. The horizontal sync signal DH1 output from the sync separation circuit 9 is supplied to an AND circuit 10 which constitutes a phase comparator. The output signal of the AND circuit 10 is supplied as a control signal to the voltage controlled oscillator 12 via the low pass amplifier 11.

Reference numeral 21 is a CD (compact disc) as well-known CD-G software, and 22 is an optical pickup. The signal reproduced from the CD 21 by the optical pickup 22 is supplied to a conventionally known CD digital signal processing circuit 23. Reference numerals 23L and 23R are audio signal output terminals, and 23S is a data output terminal for outputting data of subcode channels P to W.

The data output terminal 23S of the signal processing circuit 23
The data of the sub-code channels P to W of each frame are supplied to the CD-G decoder 24 and processed by a signal processing unit (not shown) to form red, green, and blue data (R , G, B data) are formed.

The frequency signal output from the above-mentioned oscillator 12 is 1/45 in the frequency divider 25 constituting the decoder 24.
The frequency is divided by 5, and further divided by 1/2 by the frequency divider 26. Then, the frequency signal DH2 output from the frequency divider 26 is supplied to the AND circuit 10. The AND circuit 10, the low-pass amplifier 11, the oscillator 12, and the frequency dividers 25 and 26 form a PLL circuit.

In this case, the pulse width of the output signal of the AND circuit 10 changes according to the phase difference between the horizontal synchronizing signal DH1 separated by the separating circuit 9 and the frequency signal DH2 output from the frequency divider 26, and therefore the oscillator. Since the oscillation frequency of 12 is controlled according to the phase difference, the horizontal synchronization signal DH1
A frequency signal DH2 having the same frequency is obtained. Further, the frequency signal DH (2) which is phase-synchronized with the horizontal synchronizing signal DH1 and has a double frequency is obtained from the frequency divider 25.

The vertical synchronizing signal DV1 separated by the separating circuit 9 is supplied to a vertical reset circuit 28, and the reset circuit 28 supplies a reset signal to a frequency divider (frequency dividing counter) 29. The frequency signal DH (2) output from the frequency divider 25 is divided by 1/525 by the frequency divider 29, and the frequency signal DV2 of the same frequency is phase-synchronized with the vertical synchronizing signal DV1 from the frequency divider 29. Is obtained.

The frequency signals DH2 and DH (2) output from the frequency dividers 25 and 26 and the frequency signal DV2 output from the frequency divider 29 are supplied to the counter 27. In the counter 27, the composite sync signal C · SYNC is formed based on the frequency signals DH2, DH (2), and DV2.

The R, G, B data output from the decoder 24 is supplied to a matrix circuit 31 which constitutes an RGB encoder 30. The luminance signal Y output from the matrix circuit 31 is supplied to the synchronization adding circuit 32. A composite synchronizing signal C.SYNC output from the counter 27 of the decoder 24 is supplied to the synchronization adding circuit 32, and the composite synchronizing signal C.SYNC is added to the luminance signal Y.

The luminance signal Y added with the synchronizing signal output from the synchronizing adding circuit 32 is band-limited by the low-pass filter 33 and then supplied to the synthesizing circuit 34.

The red color difference signal RY output from the matrix circuit 31 is also supplied to the balanced modulator 35. The frequency signal SSC1 (color subcarrier signal SSC) output from the frequency divider 7 is applied to the modulator 35 by the phase shifter 36.
It is supplied after being advanced by 0 ° and is balanced-modulated by the signal R-Y. The balanced modulation signal output from the modulator 35 is supplied to the adder 37. The blue color difference signal BY output from the matrix circuit 31 is supplied to the balanced modulator 38. The frequency signal SSC1 output from the frequency divider 7 is supplied to the modulator 38 and is balanced-modulated by the signal BY. The balanced modulation signal output from the modulator 38 is the adder 3
7 is supplied. These modulators 35 and 38, phase shifter 3
6, the quadrature two-phase modulation is performed by the adder 37 as well known in the art, and the carrier color signal C is formed.

The carrier color signal C output from the adder 37 is band-limited by the bandpass filter 39 and then supplied to the synthesizing circuit 34. In the synthesizing circuit 34, the luminance signal Y to which the synchronizing signal is added and the carrier color signal C are synthesized to form a video signal SVCA which constitutes a karaoke character signal.

The video signal SVCA output from the synthesizing circuit 34 of the encoder 30 is transmitted via the video output circuit 40.
It is supplied to the fixed terminal on the b side of the changeover switch 2 and the character extracting circuit 41. In the character sampling circuit 41, a sampling signal SSE corresponding to a portion related to the display of characters for karaoke is formed from the video signal SVCA.
SE is supplied to the changeover switch 2 as a changeover control signal.

The changeover switch 2 is connected to the b side during the period when the sampling signal SSE is supplied, and is connected to the a side during the other periods. Therefore, the changeover switch 2 outputs the video signal SVout in which the karaoke character signal is inserted into the video signal SV supplied to the input terminal 1, and the video signal SVout is led to the output terminal 42. By supplying this video signal SVout to a monitor (not shown), it is possible to superimpose karaoke characters on the background image of the video signal SV.

[0018]

By the way, in the example of FIG. 4, the frequency signal S synchronized with the color burst signal is generated.
PLL circuits 4 to 7 for obtaining SC1 and horizontal synchronizing signal DH
PL for obtaining frequency signals DH2 and DH (2) synchronized with 1
L circuits 10 to 12, 25 and 26,
There was a problem that it was expensive as a whole.

In the example of FIG. 4, the frequency signals DH2 and DH (2) are phase-synchronized with the horizontal synchronizing signal DH1 by constantly comparing the phases of the horizontal synchronizing signal DH1 and the frequency signal DH2.
If the phase of the horizontal synchronizing signal DH1 changes due to some reason, there is a problem that the frequency signals DH2 and DH (2) are out of synchronization.

Therefore, in the present invention, the required PLL
(EN) An external synchronizer capable of reducing the number of circuits to be constructed at low cost and preventing loss of synchronization even if a horizontal synchronizing signal separated from a video signal fluctuates.

[0021]

The present invention provides a color burst separation circuit for separating a color burst signal from an input video signal, a horizontal synchronization separation circuit for separating a horizontal synchronization signal from an input video signal, and a color burst separation circuit. A PLL circuit that outputs a first frequency signal of the same frequency in synchronization with the separated color burst signal, and this PLL
A second oscillator that outputs a frequency signal having a frequency different from the oscillation frequency of the first oscillator that forms the circuit, and a first switch circuit that selectively switches the frequency signals output from the first and second oscillators. And a second frequency signal which outputs the second frequency signal by dividing the frequency signal output from the first switch circuit by the same frequency division ratio as that of the first frequency divider that constitutes the PLL circuit. Frequency divider, a second switch circuit for selectively switching a first frequency signal output from the PLL circuit and a second frequency signal output from the frequency divider, and an output from the first switch circuit. A horizontal sync forming circuit for forming a second horizontal sync signal from the frequency signal, a phase of the first horizontal sync signal separated by the horizontal sync separation circuit and a second horizontal sync signal output from the horizontal sync forming circuit. With a comparator that compares The first switch circuit selects the frequency signal output from the second oscillator, and the second switch circuit selects the second frequency signal output from the second frequency divider. After the phases of the first and second horizontal synchronizing signals match, the first switch circuit selects the frequency signal output from the first oscillator based on the output of the comparator, and the second switch circuit selects the PLL signal. And a switch control circuit for controlling so as to select the first frequency signal output from the circuit.

[0022]

In the present invention, the first frequency signal SSC phase-synchronized with the color burst signal from the PLL circuits 4 to 7 is used.
You can get one. Since the PLL circuit for obtaining the second horizontal synchronizing signal DH2 synchronized with the first horizontal synchronizing signal DH1 separated from the input video signal SV is not required,
The cost can be reduced compared to the conventional example.

The oscillation frequency of the second oscillator 52 is P
Since the frequency is different from the oscillation frequency of the first oscillator 6 which constitutes the LL circuit, the second horizontal synchronization signal formed by the horizontal synchronization forming circuits 25, 25 from the frequency signal output from the second oscillator 52. The phase of DH2 changes with respect to the first horizontal synchronizing signal DH1 separated from the input video signal SV, and the phase always becomes the same. After the phase matching, the first horizontal synchronizing signal forming circuit forms a PLL circuit. A second horizontal synchronizing signal DH2 is formed from the first frequency signal output from the oscillator 6. Therefore, the phase matching state of the second horizontal synchronizing signal DH2 and the first horizontal synchronizing signal DH1 can be maintained without using a dedicated PLL circuit. Further, since the second horizontal synchronization signal DH2 is not compared in phase with the first horizontal synchronization signal DH1 after the phase synchronization, even if the phase of the first horizontal synchronization signal DH1 changes due to some factor, The second horizontal synchronizing signal DH2 is not affected and the second
It is possible to hold the phase synchronization state of the horizontal synchronization signal DH2.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, the frequency signal SSC1 output from the frequency divider 7 constituting the PLL circuit is the changeover switch 51.
Is supplied to the fixed terminal on the b side.

Further, 52 is a fixed oscillator, and a series circuit of a capacitor 53 and a connection switch 54 is connected between the oscillator 52 and the ground. FIG. 2 shows a specific configuration of the oscillator 52, which includes an inverter 52a and a crystal oscillator 52.
b, a resistor 52c, and capacitors 52d and 52e. The capacitor 53 and the connection switch 54 described above
Is connected in parallel with the capacitor 52d.

In the oscillator 52, the values of the resistor 52c, the capacitors 52d, 52e, etc. are set so that the oscillation frequency becomes 4 fsc when the connection switch 54 is off. When the connection switch 54 is on, the capacitor 52d
Since the capacitor 53 is connected in parallel with, the oscillation frequency decreases. The amount of decrease in the oscillation frequency is adjusted by the capacitance value of the capacitor 53.

Returning to FIG. 1, the frequency signal output from the oscillator 52 is supplied to the fixed terminal on the side a of the changeover switch 55. The fixed terminal on the b side of the changeover switch 55 has P
The frequency signal output from the oscillator 6 forming the LL circuit is supplied. The frequency signal output from the changeover switch 55 is supplied to the frequency divider 25 constituting the decoder 24. Further, the frequency signal output from the changeover switch 55 is supplied to the frequency divider 56 and is divided into 1/4, and the frequency signal SSC2 output from the frequency divider 56 is changed over to the changeover switch 5.
1 is supplied to the fixed terminal on the a side. The frequency signal output from the changeover switch 51 is the encoder 30 (see FIG. 4).
To the color subcarrier signal SSC.

The horizontal synchronizing signal DH1 separated by the separating circuit 9 has a pulse width of 1/9 in the pulse width converting circuit 57.
It is supplied to the AND circuit 10 after being converted into 10fH1 (fH1 is the frequency of the horizontal synchronizing signal DH1). Further, the frequency signal DH2 output from the frequency divider 26 of the decoder 24 has a pulse width of 1 / 910fH2 (f
H2 is supplied to the AND circuit 10 after being converted into the frequency signal DH2).

The output signal of the AND circuit 10 is supplied to the switch control circuit 59. The switch control circuit 59 controls the on / off of the connection switch 54 and the switching of the changeover switches 51 and 55 described above by the switch control circuit 59. That is, while the output signal of the AND circuit 10 is at the low level, the connection switch 54 is turned on and the changeover switches 51 and 55 are connected to the a side. Then, during a period after the phases of the horizontal synchronizing signal DH1 and the frequency signal DH2 match and the output signal of the AND circuit 10 becomes high level, the connection switch 54 is turned off and the changeover switches 51 and 55 are turned to the b side. Connected.

This example is constructed as described above, and the other parts are constructed in the same manner as the example shown in FIG.

In the present example, the phase of the horizontal synchronizing signal DH1 separated from the video signal SV is as shown in FIG. 3A (B in the figure is the output signal DH1 'of the pulse width conversion circuit 57), but the phase is divided. When the phase of the frequency signal DH2 output from the frequency divider 26 is as shown by the solid line in FIG. 7C (D in the figure, the output signal DH2 'of the pulse width conversion circuit 58), the horizontal synchronizing signal DH1 and the frequency signal DH2. Since the phases of
The output signal of the AND circuit 10 remains low level,
The connection switch 54 is controlled by the switch control circuit 59.
Is turned on, and the changeover switches 51 and 55 are connected to the a side.

In this case, the frequency signal output from the oscillator 52 is supplied to the frequency divider 56 via the changeover switch 55, and the frequency signal SSC2 output from the frequency divider 56 is changed via the changeover switch 51 to the color sub. It is output as a carrier signal SSC.

The frequency signal output from the oscillator 52 is supplied to the frequency divider 25 constituting the decoder 24 via the changeover switch 55, and the frequency signals are divided by the frequency dividers 25 and 26 by dividing the frequency signal. The signals DH2 and DH (2) are obtained. In the counter 27, the frequency signals DH2 and DH (2) and the frequency signal DV2 output from the frequency divider 29 form a composite synchronizing signal C.SYNC.

At this time, since the frequency of the frequency signal output from the oscillator 52 is lower than 4 fsc, the period 1 / fH2 of the frequency signal DH2 output from the frequency divider 26 is longer than the period 1 / fH1 of the horizontal synchronizing signal DH1. Therefore, the phase of the frequency signal DH2 is gradually delayed as shown by the arrow in FIG. 3C.

When the phase of the frequency signal DH2 matches the phase of the horizontal synchronizing signal DH1 (see the broken line in FIGS. 3C and 3D), the AND circuit 10 outputs a high level signal as shown in FIG. 3E. As a result, the connection switch 54 is turned off by the control of the switch control circuit 59, the changeover switches 51 and 55 are connected to the b side, and the state is held (see FIG. F).

In this case, the frequency divider 7 constituting the PLL circuit
The frequency signal SSC1 having the same frequency as that of the color burst signal output from the output terminal is output as the color subcarrier signal SSC via the changeover switch 51.

Further, the frequency signal output from the oscillator 6 forming the PLL circuit is supplied to the frequency divider 25 forming the decoder 24 via the changeover switch 55, and the frequency divider divides the frequency signal to divide the frequency. Frequency signals DH2 and DH (2) are obtained from 25 and 26. After the frequency signal DH2 is in phase with the horizontal synchronizing signal DH1, the frequency signal synchronized with the color burst signal output from the oscillator 6 is divided to form the frequency signal DH2. Therefore, the frequency signal DH2 is horizontally synchronized. It is possible to maintain the phase matching state with the signal DH1. The counter 27 uses the frequency signals DH2, DH (2) and the frequency signal DV2 output from the frequency divider 29 to generate a composite sync signal C.SYNC.
Is formed.

As described above, according to this example, the frequency signal DH2
Since a PLL circuit for synchronizing the phase with the horizontal synchronizing signal DH1 is not required, the cost can be reduced as compared with the conventional example.

Further, after the phase of the frequency signal DH2 matches the phase of the horizontal synchronizing signal DH1, the frequency signal output from the oscillator 6 is divided to obtain the frequency signal DH2, which is a dedicated PLL circuit. The phase matching state of the frequency signal DH2 and the horizontal synchronizing signal DH1 can be maintained even without using.

Further, since the frequency signal DH2 is not compared in phase with the horizontal synchronizing signal DH1 after the phase matching, even if the phase of the horizontal synchronizing signal DH1 changes due to some factor, the phase of the frequency signal DH2 is affected. It is possible to stably maintain the phase locked state of the frequency signal DH2 without applying it.

In the above embodiment, when the frequency signal DH2 and the horizontal synchronizing signal DH1 are out of phase with each other, the connection switch 54 is turned on so that the oscillation frequency of the oscillator 52 becomes lower than 4 fsc. However, the oscillation frequency of the oscillator 52 may be higher than 4 fsc when the phases of the frequency signal DH2 and the horizontal synchronizing signal DH1 do not match.

Further, in the above-mentioned embodiment, the example in which the video signal SV is of the NTSC system is shown, but the present invention can be similarly applied when the video signal SV is of the other system such as the PAL system. You can

[0044]

According to the present invention, the PLL circuit for obtaining the second horizontal synchronizing signal synchronized with the first horizontal synchronizing signal separated from the video signal is not required, and therefore, compared with the conventional example. It can be constructed at low cost.

After the second horizontal synchronizing signal is in phase with the first horizontal synchronizing signal separated from the video signal, a frequency signal synchronized with the color burst signal separated from the video signal is obtained. Since the second horizontal synchronization signal is formed by the horizontal synchronization forming circuit from the frequency signal output from the first oscillator that constitutes the PLL circuit, a dedicated PL
The phase matching state of the second horizontal synchronizing signal with the first horizontal synchronizing signal can be held without using the L circuit. Further, after the phase synchronization, the second horizontal synchronizing signal is not compared in phase with the first horizontal synchronizing signal, so that the phase of the first horizontal synchronizing signal separated from the video signal may fluctuate for some reason. Also, the phase synchronization state of the second horizontal synchronization signal can be stably maintained without affecting the phase of the second horizontal synchronization signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an external synchronization device according to the present invention.

FIG. 2 is a connection diagram showing a specific configuration of a fixed oscillator in the example of FIG.

FIG. 3 is a diagram for explaining phase matching in the example of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 2, 51, 55 selector switch 3 color burst separation circuit 4, 10 AND circuit 5 amplifier and low-pass filter 6 voltage controlled oscillator 7, 25, 26, 29, 56 frequency divider 8 sync separation circuit 9 horizontal / vertical sync separation circuit 21 CD 22 Optical pickup 23 Digital signal processing circuit for CD 24 CD-G decoder 27 Counter 30 RGB encoder 31 Matrix circuit 32 Synchronization addition circuit 34 Synthesizing circuit 35, 38 Balance modulator 36 Phase shifter 37 Adder 41 Character extracting circuit 52 Fixed oscillator 53 Capacitor 54 Connection switch 57, 58 Pulse width conversion circuit 59 Switch control circuit

Claims (1)

[Claims] 1. A color burst separation circuit for separating a color burst signal from an input video signal, a horizontal sync separation circuit for separating a horizontal sync signal from the input video signal, and a color burst signal separated by the color burst separation circuit. A PLL circuit that outputs a first frequency signal of the same frequency, and a second oscillator that outputs a frequency signal of a frequency different from the oscillation frequency of the first oscillator forming the PLL circuit; A first switch circuit that selectively switches frequency signals output from the first and second oscillators, and a first frequency divider that configures the frequency signal output from the first switch circuit in the PLL circuit. A second frequency divider which outputs a second frequency signal by dividing the frequency by the same frequency division ratio as that of the first frequency signal output from the PLL circuit. Signal and a second switch circuit for selectively switching the second frequency signal output from the frequency divider, and a horizontal switch for forming a second horizontal synchronizing signal from the frequency signal output from the first switch circuit. A synchronization forming circuit, a comparator for comparing the phases of the first horizontal synchronization signal separated by the horizontal synchronization separating circuit and the second horizontal synchronization signal output from the horizontal synchronization forming circuit, and the first switch. The circuit selects the frequency signal output from the second oscillator and the second switch circuit selects the second frequency signal output from the second frequency divider. After the phases of the first and second horizontal synchronization signals match, the first switch circuit selects the frequency signal output from the first oscillator based on the output of the comparator and the second Switch External synchronization apparatus characterized by comprising a switch control circuit for controlling to select the first frequency signal output from the PLL circuit in the circuit.