JPH06276400A - Display device - Google Patents

Abstract

PURPOSE:To drive a 2-screen division display device by display data of an input form for a CRT without provision of a conversion circuit such as a frame memory. CONSTITUTION:A control signal representing an upper pattern data valid period and a lower pattern data valid period is given from a logic control circuit 48 to a lower pattern data control circuit 81 and an upper pattern data control circuit 82. When the control signal representing the upper pattern data valid period is given to the lower pattern data control circuit 81 and the upper pattern data control circuit 82, a modulation voltage clamped to a constant voltage is impressed to data side electrodes LD1-LDm independently of display data DA. When the control signal representing the lower pattern data valid period is given to the lower pattern data control circuit 81 and the upper pattern data control circuit 82, a modulation voltage clamped to a constant voltage is applied to the data side electrodes LD1-LDm independently of the display data DA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a capacitive flat matrix display or a plasma display.

[0002]

2. Description of the Related Art An EL (electroluminescence) display device is a display device using a thin film EL element as a display panel. In this thin film EL device, a plurality of band-shaped transparent electrodes are arranged in parallel with each other on a glass substrate, a dielectric substance is laminated on this, an EL layer is further laminated thereon, and a dielectric substance is further laminated thereon. A three-layer structure is formed by stacking layers, and a plurality of strip-shaped back electrodes extending in a direction orthogonal to the transparent electrode are arranged on top of each other in parallel.

In the EL display device, the transparent electrode of the thin film EL element is used as the data side electrode, and the back electrode of the thin film EL element is used as the scanning electrode, and each intersection of the data side electrode and the scanning side electrode is Each becomes a picture element.

A data voltage is applied to the data-side electrode so that a grayscale display corresponding to display data is applied to the picture element.
In addition, a scan voltage for sequentially designating a row of picture elements is selectively applied to the scan electrodes.

As one of the conventional examples of such an EL display device, there is known one in which a display panel is divided into two upper and lower display areas. In the case of this EL display device,
The data-side electrode is divided into an upper half display area and a lower half display area of the display panel, and the data voltage is applied to each separately.

FIG. 5 is a block diagram showing a schematic structure of a conventional EL display device. This EL display device is a display device using a thin film EL element as a display panel 1, and the display panel 1 has an upper half display area (hereinafter, referred to as “upper screen”) and a lower half display area (hereinafter, referred to as “upper screen”). It is called "lower screen").

The upper screen is composed of the data side electrodes UD1 to UDm and the scanning side electrodes S1 to Sn, and the lower screen is the data side electrodes LD1 to LDm and the scanning side electrodes S (n + 1) to S2n.
It consists of and.

Two data side switching circuits 11 and 2
Reference numeral 1 corresponds to the upper screen and the lower screen, respectively, and the modulation voltage V, which is the data voltage corresponding to the display data, is individually applied to the corresponding data side electrodes UD1 to UDm and LD1 to LDm.
A circuit for applying MU and VML, and data side output port groups 12 and 22 individually connected to the respective data side electrodes UD1 to UDm and LD1 to LDm, and display data U.
Data side output port groups 12, 22 according to D ', LD'
And logic circuits 13 and 23 for turning on / off.

The scanning-side switching circuit 2 is a circuit for applying a writing voltage, which is a scanning voltage, to the scanning-side electrodes S1 to S2n in a line-sequential manner, and each scanning-side electrode S1 to S2n.
The scanning side output port group 3 connected to 2n and the logic circuit 4 for turning on / off the scanning side output port group 3 according to the line order of the scanning side electrodes S1 to S2n. The scan electrodes S1 and S (n + 1) are connected to the scan output port group 3 by one signal line, and the other scan electrodes S2 to S2.
Similarly, for n and S (n + 2) to S2n, two scanning-side electrodes are connected by one signal line.

The drive circuit 5 is a circuit for generating a high voltage for driving the display panel from a constant reference voltage VD,
It has a modulation drive circuit 6 for supplying a modulation voltage to a modulation voltage control circuit 31, which will be described later, and a write drive circuit 7 for supplying a write voltage to the scan side output port group 3.

A modulation voltage control circuit 31 is inserted between the modulation drive circuit 6 and the data output port groups 12 and 22 of the data side switching circuits 11 and 21. The modulation voltage control circuit 31 distributes and supplies the modulation voltage output from the modulation driving circuit 6 to the respective data output port groups 12 and 22, and also the amplitude of the modulation voltage VMU supplied to the upper screen data output port group 12, This is a circuit for individually variably adjusting the amplitude of the modulation voltage VML supplied to the lower screen data output port group 22.

The logic control circuit 8 operates by the drive voltage VL, and the upper screen display data UD and the lower screen display data L.
Display panel 1 based on input signals such as D, data transfer clock CK, horizontal sync signal HS, and vertical sync signal VS.
Is a circuit for generating various timing signals necessary for driving the.

The basic display operation of the display device shown in FIG. 5 is such that the period over the two fields of the first field and the second field is one cycle, and the data side electrodes UD1 to UD1.
A voltage VM is applied to UDm and LD1 to LDm as a modulation voltage corresponding to display data that determines emission or non-emission. The scanning-side electrodes S1 to S2n are line-sequentially applied with a voltage −VW in the first field and a voltage VW + VM in the second field as write voltages.

FIG. 6 is a timing chart for explaining the display operation of the display device shown in FIG. Figure 6 (a)
6B shows the upper screen display data U supplied to the upper screen logic circuit 13 and the lower screen logic circuit 23, respectively.
D'and lower screen display data LD 'are shown.

FIG. 6C shows the modulation voltage VMU corresponding to the display data UD 'output from the upper screen data side switching circuit 11 to the data side electrodes UD1 to UDm, and FIG. 6D shows the lower screen. Data side switching circuit 2
The modulation voltage VML output from 1 to the data side electrodes LD1 to LDm is shown. FIG. 6E shows the write voltages −VW and VW + VM which are the scan voltages output to the first and (n + 1) th scan side electrodes S1 and S (n + 1).

FIG. 6F shows the effective voltage applied to the portion of the picture element where the first scan side electrode S1 and the data side electrode UD1 intersect, and FIG. 6G shows the (n + 1) th scan. The effective voltage applied to the portion of the picture element where the side electrode S (n + 1) and the data side electrode LD1 intersect is shown. Also, the basic display operation of the display device is such that the period over two fields of the first field A'and the second field B'is 1
Set as a cycle.

By this display operation, the data side electrode UD
1 to UDm, LD1 to LDm, and scanning side electrodes S1 to S2
At the portion of the picture element where n intersects, write voltage -VW, VW
A superposition effect or a cancellation effect of + VM and the modulation voltage VM occurs. Since the thin film EL element forming the display panel 1 exhibits the applied voltage-luminance characteristics shown in FIG. 7, it is effective for the picture element due to the superposing effect and the canceling effect of the write voltage-VW, VW + VM and the modulation voltage VM. A voltage VW + VM equal to or higher than the light emission threshold voltage Vth or a voltage VW equal to or lower than the light emission threshold voltage Vth is applied as a voltage, and each pixel is in a light emitting or non-light emitting state, and a predetermined display is obtained.

[0018]

The above-mentioned EL display device is constructed by dividing the display panel 1 into two upper and lower display areas. When simultaneously driving the upper and lower screens of the display panel 1 divided into the upper and lower parts, the upper screen display data UD ′
And the lower screen display data LD 'are simultaneously applied to the data side switching circuits 11 and 21 corresponding to the upper screen and the lower screen, respectively, and the modulation voltage VM, which is a data voltage corresponding to each display data, is supplied to the data side electrode UD1. ~ UD
m, LD1 to LDm are generally applied.

However, the input form of the display data is
Since the data transfer order is completely different from the display data input form for a CRT (cathode ray tube) that is generally used as a display device, when the display data input form for a CRT is used, it is dedicated. Since a conversion circuit including a frame memory and the like must be provided, there arises a problem that the manufacturing cost of the product is increased.

An object of the present invention is to provide a display device capable of displaying an image by utilizing the input form of display data as it is, without newly providing a conversion circuit such as a frame memory.

[0021]

According to the present invention, a plurality of scanning side electrodes and a plurality of data side electrodes are arranged in directions intersecting with each other, and a pixel is provided at each intersection of the scanning side electrodes and the data side electrodes. A display panel in which two display areas are arranged above and below and a scan voltage which is connected to the scan side electrodes and which specifies a row of picture elements in a line-sequential manner are the same for the scan side electrodes in the upper and lower display areas. The scanning side driving means for outputting at a timing and the data side electrode of the upper display region are connected, and in order to apply a data voltage corresponding to a display signal to each column of picture elements, the data voltage is applied to each data side electrode. Connected to the data side driving means for the upper area and the data side electrode of the lower display area, and outputs the data voltage corresponding to the display signal to each column of the picture element, the data side electrode Output to And a data control means for outputting a display signal to the upper area data side driving means and the lower area data side driving means at the same timing. The driving means and the lower area data side driving means output the data voltage at the same timing, and the data control means,
A display device is characterized in that when a display signal is output to one data side drive means, a constant voltage signal is output to the other data side drive means.

[0022]

According to the present invention, the scanning-side electrodes forming the two display regions arranged above and below the display panel are designated by the scanning-side driving means by applying the scanning voltage line-sequentially and at the same timing. . That is, the first of the upper display area
The line and the first line of the lower display area are designated at the same time, and the same applies to the second and subsequent lines. A data voltage corresponding to a display signal is applied to the designated pixel array of the scanning side electrodes by the data driving means for the upper region and the data driving means for the lower region.

The display signal is given to the two data side drive means at the same timing by the data control means. At this time, when the data control means outputs the display signal to one of the data side driving means, it outputs the constant voltage signal to the other data side driving means. That is, when the display signal to be displayed in the upper display area is supplied, the constant voltage signal is supplied to the data driving means for the lower area, and conversely, the display signal to be displayed in the lower display area is supplied. When it is present, a constant voltage signal is applied to the data driving means for the upper area. Therefore, the input form of serial data such as a display signal for a CRT can be used as it is and displayed without conversion.

In particular, when the display panel is realized by a thin film EL element, the picture element selectively emitted once emits light again due to the polarization effect, and the picture element which did not emit light maintains the non-light emitting state.
This makes it possible to realize a clearer display brightness. Generally, in a double-insulation AC drive type thin film EL element having a three-layer structure, a writing voltage of about 200 V
The picture element that selectively emitted light is retained with the internal polarization formed in the light-emitting layer, but the non-light-emission picture element has no polarization, and then a writing voltage of the same voltage of opposite polarity was applied. At this time, due to the overlapping effect with the internal electrodes, the previously selectively emitted pixel element emits light again, and the non-emitted pixel element maintains the non-emission state.
Such a characteristic is called a polarization effect.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a schematic structure of a display device which is an embodiment of the present invention. This display device is an EL display device having a thin film EL element as a display panel 41, and the display panel 41 has an upper half display area (hereinafter,
This is called the "upper screen". ) And the lower half of the display area (below,
This is called the "lower screen". ) And divided. Display panel 41
Then, the transparent electrodes of the thin film EL element are the data side electrodes UD1 to UD1.
UDm, LD1 to LDm, and back electrodes of the thin film EL element are scan electrodes S1 to Sn and S (n + 1) to S2n. The upper screen is composed of the data side electrodes UD1 to UDm and the scanning side electrodes S1 to Sn, and the lower screen is the data side electrodes LD1 to LDn and the scanning side electrodes S (n + 1) to S2n.
Composed of and.

Two data side switching circuits 51, 6
A circuit 1 corresponds to the upper screen and the lower screen, and is a circuit for individually applying a modulation voltage, which is a data voltage corresponding to the display data DAU and DAD, to the data-side electrodes UD1 to UDm and LD1 to LDm, respectively. Yes, data side electrode UD1
To UDm and LD1 to LDm are connected to the data side output port groups 52 and 62, respectively, and the display data D to be provided.
Data side output port groups 52 and 62 according to AU and DAD
And logic circuits 53 and 63 for turning on / off.

The scanning side switching circuit 42 is a circuit for applying the writing voltages VW + VM, -VW, which are scanning voltages, to the scanning side electrodes S1 to S2n according to the line order, and the scanning side electrodes S1 to S2n are connected. The scan side output port group 43 and the logic circuit 44 for turning on / off the scan side output port group 43 according to the line order of the scan side electrodes S1 to S2n. The two scanning-side electrodes S1,
S (n + 1) is connected to the scan side output port group 43 by one signal line, and the other scan side electrodes S2 to Sn,
Similarly, for S (n + 2) to S2n, two signal lines are connected to each other by one signal line.

The drive circuit 45 is a circuit for generating a high voltage for driving the display panel from a constant reference voltage VD, and the modulation voltage VM is applied to the data side output port groups 52 and 62.
(More specifically, the modulation drive circuit 46 for supplying the voltages VMU, VML) and the write drive circuit 47 for supplying the write voltages VW + VM, -VW to the scan side output port group 43.
Have and.

A modulation voltage control circuit 71 is inserted between the modulation drive circuit 46 and the upper screen data output port group 52, and between the modulation drive circuit 46 and the lower screen data output port group 62. A modulation voltage control circuit 72 is inserted in the. These modulation voltage control circuits 71 and 72 are provided with the modulation voltage VMU supplied to the upper screen data output port group 52.
And an amplitude voltage of the modulation voltage VML supplied to the lower screen data output port group 62 are individually variably adjusted.

The logic control circuit 48 operates at the drive voltage VL and is necessary for driving the display panel 41 based on the input signals such as the display data DA, the data transfer clock CK, the horizontal synchronizing signal HS and the vertical synchronizing signal VS. It is a circuit for generating various timing signals. An upper screen data control circuit 82 is provided between the logic control circuit 48 and the upper screen logic circuit 53.
And a lower screen data control circuit 81 is interposed between the logic control circuit 48 and the lower screen logic circuit 63.

The lower screen data control circuit 81 and the upper screen data control circuit 82 operate based on the display data DA and the control signal supplied from the logic control circuit 48, and output the screen data at the same timing. When the data to be displayed on the upper screen of the display panel 41 is given, the upper screen data control circuit 82 outputs the display data DA as the upper screen data DAU as it is and receives the data to be displayed on the lower screen. If it is, the predetermined specific data is output as the upper screen data DAU.

Further, when the data to be displayed on the upper screen of the display panel 41 is given, the lower screen data control circuit 81 transfers the predetermined specific data to the lower screen data D.
When data to be output as AD and displayed on the lower screen is given, the display data DA is converted to the lower screen data DAD.
Output as.

The basic display operation of the display device shown in FIG. 1 is such that the period over the two fields of the first field and the second field is one cycle, and the data side electrodes UD1 to UD1.
A modulation voltage VM for determining light emission and non-light emission is applied to UDm and LD1 to LDm, and a voltage -V in the first field is used as a writing voltage for the scanning side electrodes S1 to S2n.
This is done by applying W, and in the second field, the voltages VW + VM line-sequentially.

2 and 3 are timing charts for explaining the display operation of the display device shown in FIG.
FIG. 2A shows the display data DA input to the logic control circuit 48. In the first field A, the logic control circuit 48
Is input with the upper screen display data, and in the second field B, the lower screen display data is input with the logic control circuit 48.

FIG. 2B shows control signals applied from the logic control circuit 48 to the lower screen data control circuit 81, the upper screen data control circuit 82, and the modulation voltage control circuits 71 and 72, respectively. In the first field A in which the upper screen display data is input to the logic control circuit 48, a control signal indicating the upper screen display data valid period is given to each circuit described above. In the second field B in which the lower screen display data is input to the logic control circuit 48, a control signal indicating the lower screen display data valid period is given to each of the circuits described above.

FIG. 2C shows the upper screen data control circuit 82.
Upper screen data DA given from the upper screen to the upper screen logic circuit 53
2D shows the lower screen data DAD supplied from the lower screen data control circuit 81 to the lower screen logic circuit 63. Further, FIG. 2E shows the modulation voltage VM applied from the modulation voltage control circuit 71 to the upper screen data output port group 52.
2F shows the modulation voltage VM applied from the modulation voltage control circuit 72 to the lower screen data output port group 62.
L is shown.

A control signal indicating the upper screen data valid period is
When given to the upper screen data control circuit 82 and the lower screen data control circuit 81, respectively, the upper screen data control circuit 8
2 is display data DA given from the logic control circuit 48
As it is as upper screen data DAU, upper screen logic circuit 5
Give to 3. The lower screen data control circuit 81 sets the lower screen data DAD to the data that sets all the outputs of the lower screen data output port group 62 to the high level regardless of the display data DA.
To the lower screen logic circuit 63.

When a control signal indicating the upper screen data valid period is applied to the modulation voltage control circuits 71 and 72, the modulation voltage control circuit 71 applies the voltage VM to the upper screen data output port group 52 as the modulation voltage VMU. . Further, the modulation voltage control circuit 72 uses the lower screen data output port group 62.
Is applied as the modulation voltage VML.

A control signal indicating the lower screen data valid period is
When applied to the upper screen data control circuit 82 and the lower screen data control circuit 81, respectively, the lower screen data control circuit 8
Reference numeral 1 designates the display data DA given from the logic control circuit 48 as the lower screen data DAD as it is, and the lower screen logic circuit 63.
Give to. The upper screen data control circuit 82 displays the display data D
Regardless of A, data for setting all outputs of the upper screen data output port group 52 to the high level are supplied to the upper screen logic circuit 53 as upper screen data DAU.

When a control signal indicating the lower screen data valid period is applied to the modulation voltage control circuits 71 and 72, the modulation voltage control circuit 71 applies a voltage 1/2 VM to the upper screen data output port group 52 as the modulation voltage VMU. give. The modulation voltage control circuit 72 also applies the voltage VM to the lower screen data output port group 62 as the modulation voltage VML.

FIG. 2 (g) shows the upper screen data output port waveform by the modulation voltage VM output from the upper screen data switching circuit 51 to the data side electrodes UD1 to UDm, and FIG. 2 (h) shows the lower screen. Data switching circuit 6
3 shows a lower screen data output port waveform according to the modulation voltage VM output from 1 to the data side electrodes LD1 to LDm.

As described above, in the first field A which is the upper screen data valid period, the upper screen logic circuit 53 receives the display data DA from the upper screen data control circuit 82 as it is as the upper screen data DAU, and the upper screen data DAU is supplied. Logic circuit 5
3 turns on / off the upper screen data output port group 52 according to the upper screen data DAU. Further, the voltage VM is applied from the modulation voltage control circuit 71 to the upper screen data output port group 52 as the modulation voltage VMU. Therefore, FIG.
As shown in (g), the data electrodes UD1 to UDm are
The modulation voltage VM is applied corresponding to the display data DA.

Further, in the lower screen logic circuit 63, data for setting all outputs of the lower screen data output port group 62 from the lower screen data control circuit 81 to the high level is the lower screen data DA.
It is given as D. As a result, in the first field A, the lower screen data output port group 62 is always on. In addition, in the lower screen data output port group 62,
The modulation voltage control circuit 72 outputs the voltage 1/2 VM as the modulation voltage V.
Since it is given as ML, the modulation voltage 1 / 2VM clamped to a constant voltage is applied to the data electrodes LD1 to LDm as shown in FIG. 2H regardless of the display data DA.

In the second field B, which is the effective period of the lower screen data, the upper screen logic circuit 53 receives data for setting all the outputs of the upper screen data control circuit 82 to the high level to the high level. It is given as screen data DAU. As a result, in the second field B, the upper screen data output port group 52 is always on. In addition, the voltage 1/2 VM is applied to the upper screen data output port group 52 from the modulation voltage control circuit 71 as the modulation voltage VMU. Therefore, as shown in FIG. 2G, the data side electrodes UD1 to UDm are Modulation voltage 1 / 2VM clamped to a constant voltage regardless of display data DA
Is applied.

Further, the display data DA is directly given from the lower screen data control circuit 81 to the lower screen logic circuit 63 as the lower screen data DAD, and the lower screen logic circuit 63 outputs the lower screen data according to the lower screen data DAD. Port group 6
Turn 2 on / off. In the lower screen data output port group 62, the voltage VM from the modulation voltage control circuit 72 is the modulation voltage VM.
It is given as L. Therefore, as shown in FIG. 2H, the display data DA is stored in the data electrodes LD1 to LDm.
The modulation voltage VM is applied corresponding to.

Next, description will be made with reference to FIG. Figure 3
2A shows the same display data DA as in FIG. 2A, and FIG. 3B shows the same control signal as in FIG. 2B. See also FIG.
FIG. 3C shows the same upper screen data output port waveform as in FIG. 2G, and FIG. 3D shows the same lower screen data output port waveform as in FIG. 2H.

As described with reference to FIG. 2, the upper screen is constructed in the first field A in which the control signal indicating the upper screen display data valid period is given to the lower screen data control circuit 81 and the upper screen data control circuit 82. Data side electrode UD1
The modulation voltage VM is applied to ˜UDm according to the display data given to the upper screen logic circuit 53. A modulation voltage 1 / 2VM clamped to a specific voltage is applied to the data-side electrodes LD1 to LDm forming the lower screen.

In the second field B in which the control signal indicating the effective period of the lower screen display data is given to the lower screen data control circuit 81 and the upper screen data control circuit 82, the upper screen data side electrodes UD1 to UDm are supplied. A modulation voltage 1 / 2VM clamped to a specific voltage is applied.
In addition, the lower screen data side electrodes LD1 to LDm are applied to the modulation voltage V according to the display data given to the lower screen logic circuit 63.
M is applied.

FIG. 3E shows write voltages -VW and VW + VM which are scan voltages applied to the first and (n + 1) th scan electrodes S1 and S (n + 1), respectively. Figure 3
(F) is the first scan electrode S1 and the data side electrode UD1
Indicates the effective voltage applied to the part of the picture element where and intersect,
FIG. 3G shows the effective voltage applied to the pixel portion where the (n + 1) th scan electrode S (n + 1) and the data electrode LD1 intersect.

By this display operation, the data side electrode UD
1 to UDm and the scanning side electrodes S1 to Sn intersect with each other, in the first field A, the writing voltage −
A superposition effect or a cancellation effect of VW and the modulation voltage VM occurs. The thin film EL element that constitutes the display panel 41 is
Since the applied voltage-luminance characteristics shown in FIG. 4 are shown, the light emission threshold voltage Vt is an effective voltage applied to each of the picture elements due to the superposition effect and the cancellation effect of the write voltage -VW and the modulation voltage VM.
A voltage greater than or equal to h- (VW + VM) or a voltage VW equal to or less than the light emission threshold voltage Vth is applied, and each pixel is in a light emitting or non-light emitting state, and a predetermined display is obtained.

In the second field B, an effective voltage having a polarity opposite to that of the effective voltage applied in the first field A is applied to each of the picture elements due to the superposition effect of the write voltage VW + VM and the modulation voltage 1 / 2VM. (VW + 1/2
VM) is applied. At this time, due to the above-mentioned polarization effect, the non-light emitting picture element does not emit light in the first field A, and the light emitting picture element emits light again.

Similarly, in the portion of each picture element where the data side electrodes LD1 to LDm and the scanning side electrodes S (n + 1) to S2n intersect, in the second field B, the write voltage VW + VM.
And a modulation voltage VM have a superimposing effect and a canceling effect.
Therefore, due to the superimposing effect and the canceling effect of the write voltage VW + VM and the modulation voltage VM, a voltage (VW + V) equal to or higher than the light emission threshold voltage Vth is applied to each of the picture elements as an effective voltage.
M) or a voltage VW equal to or lower than the light emission threshold voltage Vth is applied, and each picture element is in a light emitting or non-light emitting state, and a predetermined display is obtained.

In the first field A, which is repeated immediately after the second field B, the second field is added to each picture element by the superposition effect of the write voltage -VW and the modulation voltage 1 / 2VM. Effective voltage with polarity opposite to that applied at B- (VW + 1/2
VM) is applied. At that time, due to the above-mentioned polarization effect, the non-light emitting picture element does not emit light in the second field B, and the light emitting picture element emits light again.

Therefore, for each picture element, the first
In the field A and the second field B, the effective voltages having opposite polarities are alternately applied, and the alternating voltage drive of the thin film EL element is performed with the first field A and the second field B as one cycle. Therefore, of the display data DA supplied from the logic control circuit 48, the upper screen display data is supplied to the upper screen logic circuit 53 in the first field A, and the lower screen display data is supplied to the lower screen logic circuit 63 in the second field B. Good. As a result, it is possible to drive the aforementioned two-screen split type display device by using the input form of the display data for the CRT as it is, without newly providing a conversion circuit such as a frame memory.

In the display operation, a 1/2 VM modulation voltage is used as the clamped modulation voltage, but the clamp voltage is not necessarily limited to this potential voltage. Any potential between the ground potential GND and VM can be used depending on the required level such as the contrast of the display panel 41.

[0056]

As described above, according to the present invention, without providing a conversion circuit such as a frame memory or the like, the two screens can be displayed while the input form of the display data for the CRT generally used in the display device is maintained. It is possible to drive a split-type display device. This makes it possible to supply inexpensive and high-quality display devices to the market.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display device that is an embodiment of the present invention.

FIG. 2 is a timing chart showing a display operation of the display device shown in FIG.

3 is a timing chart showing a display operation of the display device shown in FIG.

FIG. 4 is a graph showing applied electrode-luminance characteristics of a thin film EL element that constitutes a display panel 41 of the display device shown in FIG.

FIG. 5 is a block diagram showing a schematic configuration of a display device as a conventional example.

6 is a timing chart showing a display operation of the display device shown in FIG.

FIG. 7 is a graph showing applied voltage-luminance characteristics of a thin film EL element forming the display panel of the display device shown in FIG.

[Explanation of symbols]

 41 display panel 42 scanning side switching circuit 45 drive circuit 46 modulation drive circuit 47 write drive circuit 48 logic control circuit 51, 61 data side switching circuit 52 upper screen data output port group 62 lower screen data output port group 71, 72 modulation voltage Control circuit 81 Lower screen data control circuit 82 Upper screen data control circuit

Claims (1)

[Claims] 1. A plurality of scanning-side electrodes and a plurality of data-side electrodes are arranged in a direction intersecting with each other, and a display area having a picture element is vertically arranged at each intersection of the scanning-side electrodes and the data-side electrodes.
And two display panels, which are connected to the scan-side electrodes, and which output a scan voltage for line-sequentially specifying the rows of picture elements to the scan-side electrodes of the upper and lower display areas at the same timing. Drive means and an upper area connected to the data side electrode of the upper display area and outputting the data voltage to each data side electrode in order to apply a data voltage corresponding to a display signal to each column of picture elements Data side driving means and a lower part connected to the data side electrodes of the lower display area and outputting the data voltage to each data side electrode in order to apply a data voltage corresponding to a display signal to each column of picture elements. An area data side driving means; and a data control means for outputting a display signal to the upper area data side driving means and the lower area data side driving means at the same timing. The data side driving means and the lower area data side driving means output the data voltage at the same timing, and when the data control means outputs the display signal to one data side driving means, the other data side driving means A display device which outputs a constant voltage signal to the display device.