JPH06276218A - Data check system for atm transmission system - Google Patents

Abstract

PURPOSE:To input a checking cell at a transfer interval of valid cells to test the normal state of data by providing a check cell generator means which puts a check cell including the test data into another cell and a check cell confirming means which confirms the normal state of the test data included in the check cell. CONSTITUTION:A check cell generator means 2 inputs a check cell including the test data of 8 bits of all '0' and 8 bits of all '1' at the input side, e.g. a cell synchronizing part of an ATM transmission system 1. Meanwhile a check cell confirming means 3 is set at the output side, for example, of the system 1 and confirms the normal state of the check cell received from the means 2. Thus it is possible to detect the fault of a bit line, i.e., a bit stack by means of the test data of all '1' and all '0' when the data are transmitted in 8 bit and in parallel to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer mode (AT
The present invention relates to a communication system for performing communication in a cell format using M), and more particularly to a data check method in an ATM transmission system for checking the normality of data transmitted by an ATM cell.

[0002]

2. Description of the Related Art In a transmission system using an ATM cell, data in the cell is transmitted, for example, in an 8-bit parallel format together with a parity bit obtained for the 8 bits. . Therefore, by checking the parity bit on the output side of the ATM cell transmission system, for example, the normality of the data transferred in the system can be confirmed.

However, although an error check method using a parity bit can detect an odd number of errors, it has a problem that an even number of errors cannot be detected. In the ATM cell transmission system, switching information is added in the ATM switching system corresponding to the virtual path identifier (VPI) and the virtual channel identifier (VCI) stored in the header part in a fixed length cell having a length of 53 bytes, for example. The transfer is performed based on the switching information, but since the error of the even number bit cannot be detected by the parity bit, there is a problem that the transmission does not always go well even though the error is not detected as the system maintenance system. there were.

According to the present invention, a check cell is input to the ATM transmission system between transfer of valid cells without using a parity bit for data transmitted in 8-bit parallel, and the normality of data is checked by using this. The purpose is to provide a data check method to be tested.

[0005]

FIG. 1 is a block diagram showing the principle of the present invention. The figure is a principle block diagram of a data check method in an ATM transmission system for transmitting data in an ATM cell in 8-bit parallel.

In FIG. 1, the check cell generating means 2 is, for example, a check cell generating circuit, and a check cell in which test data of 8 bit all 0s and 8 bit all 1s is inserted into one cell is an ATM transmission system 1.
Input side, for example, in the cell synchronization section.

The check cell confirmation means 3 is, for example, an AT.
It is provided on the output side of the M transmission system 1 and confirms the normality of the 8-bit all 0 and 8-bit all 1 test data inside the check cells output from the system. is there.

[0008]

According to the present invention, for example, a check cell in which 2 bytes of 8-bit all 1 test data are inserted immediately after 5 bytes of the header portion of an ATM cell and 2 bytes of 8-bit all 0 test data are inserted immediately thereafter. Is input to the ATM transmission system 1 from the check cell generating means 2, and the test data is checked by using the check cell confirming means 3 provided at the output side of the system 1 or at an arbitrary position in the system 1, A full or partial system check is performed.

The reason why both the test data of all 1s and the test data of all 0s are used is to detect the failure of the bit stack, that is, the bit line. The present invention is intended for the case where data is transmitted in 8-bit parallel. In this case, if a failure occurs in a specific bit line, the output of that bit line may always be 1 or 0. It is possible to detect a bit line failure, that is, a bit stack, by using all-zero test data.

In the present invention, the check cell confirmation circuit constituting the check cell confirmation means 3 has, for example, a bit indicating the arrival of a check cell, a bit indicating the normality of 8-bit all 0 test data, and an 8-bit all 1 bit. The method of displaying the data check result by a total of 3 bits indicating the normality of the test data is used.

As described above, in the present invention, the data check is performed using the check cell without using the parity bit for the data transmitted in 8-bit parallel.

[0012]

FIG. 2 is a block diagram of the entire configuration of an ATM transmission system using the data check method of the present invention. In the figure, data input as an optical signal is converted into an electrical signal by the optical / electrical interface 10, and cell synchronization is achieved by the cell synchronization unit 11 to create a head pulse for the cell. Here, the content of the header error control (HEC) byte in the header of the cell is used for cell synchronization, but error checking is also performed at the same time. Therefore, a bit check on the highway of the ATM transmission system is necessary after the cell synchronization unit 11.

When synchronization is achieved by the cell synchronization unit 11, cell-based processing becomes possible thereafter, and the cells are input to the switch unit 14 via the subscriber interface 12 and the multiplexer 13, exchanged by the switch unit 14, and then switched. The signal is transmitted to the subscriber on the other end of the communication via the demultiplexer 15 on the output side of the unit, the subscriber interface 16, the synchronization signal providing unit 17, and the electric / optical interface 18.

In FIG. 2, processing can be performed on a cell-by-cell basis in the portion after the cell synchronizer 11. Therefore, for example, a check cell for detecting a bit stack is created and input to the subscriber interface 12. The check cell is input during the transfer period of the invalid cell so that the input of the check cell does not affect the transmission cell of the actual valid data.

FIG. 3 shows an embodiment of the check cell format. In the figure, the check cell has a specific value as its virtual channel identifier (VCI). V
The value of CI is inserted into the 4th bit of the 2nd byte of the 5th byte of the header part, all of the 3rd byte, and the 4th bit of the 4th byte of 53 bytes of the ATM cell. For example, the value in 4-bit units is' 100
The one that becomes 0'is used.

Of the 48 bytes of the information area of the cell, the first 2 bytes are all 1's of test data, the next 2 bytes are all 0's of test data, and the remaining 44 bytes of data are all don't cares.

FIG. 4 is an explanatory diagram of the enable signal showing the distinction between the valid cell and the invalid cell in the ATM transmission system. In the figure, the cell frame (CF) signal is, for example, a pulse indicating the beginning of the cell detected by the cell synchronization unit 11 in FIG. 2, and the enable signal (ENB) indicates a valid cell when its value is'L '. It is a signal indicating an invalid cell when it is "H".

FIG. 5 is a configuration block diagram of the check cell generation circuit. In the figure, the check cell generation circuit includes a shift register 2 for shifting the cell frame signal CF.
0, a counter 21 that counts an enable signal, a VCI assigning unit 22 that assigns a virtual channel identifier for identifying a check cell to a check cell, and an AND circuit 23 to
30 and an OR circuit 31.

In FIG. 5, the shift register 20 shifts the cell frame signal CF for each input of one byte of the cell described with reference to FIG. 3, and sequentially outputs it to the output terminals 1-9. Further, the counter 21 is incremented every time the enable signal ENB described in FIG. 4 becomes “H”, and becomes “H” when it reaches a certain value, that is, when some invalid cells are input. To output the check cell output timing.

Therefore, in the output timing of the check cell, the AND circuit 2 is operated at the time of inputting the second byte in FIG.
AND circuit 2 at the time of input of the 3rd, 3rd and 4th bytes
The outputs of Nos. 4 and 25 are respectively set to “L”, and the VCI adding unit 22 determines the specific VC according to the outputs of these AND circuits.
I, in FIG. 3, '1000' is added in 4-bit units. As the value of this specific VCI, for example, "1000" can be used as a fixed value, or it can be specified from the software side when the system is started up.

The output of the AND circuit 26 is "L" at the 6th and 7th bytes of FIG. 3, that is, at the timing when the test data of all 1s should be inserted into the check cell.
In response to this, the output of the AND circuit 30 becomes “H”, and the test data of all 1s is output from the AND circuit 28. Further, since the output of the AND circuit 27 becomes "L" and the output of the OR circuit 31 also becomes "L" at the 8th and 9th bytes, that is, at the timing when the test data of all 0s should be inserted, the AND circuit 29 becomes "L". To output all 0 test data.

The check cell generating circuit of FIG. 5 is, for example, as shown in FIG.
It is provided in the cell synchronization unit 11 of the above, and each device after the subscriber interface 12 in the system can check the test data in the input check cell. That is, each device monitors the VCI value of the input cell and checks the data if it is a check cell.

FIG. 6 is a configuration block diagram of a check cell confirmation circuit for checking test data. In the figure, the check cell confirmation circuit is a shift register 40 for shifting the cell frame signal CF, a VCI monitor 41 for judging whether or not the VCI added to the input cell is for the check cell, and an AND circuit 42. ~ 4
4, OR circuits 45 and 46, a NOR circuit 47, and flip-flops 48 and 49.

The operation of the check cell confirmation circuit of FIG. 6 is shown in FIG.
The check result output control signal will be described. 6, the shift register 40 performs the same operation as the shift register 20 in FIG. 5, and shifts the cell frame signal CF for each byte. Therefore, “L” is output to the VCI monitor 41 at the second byte to the fourth byte, that is, at the time of input of VCI, and in response to this, the VCI monitor 41 compares the VCI in the input cell with, for example, “1000”, When these coincide with each other, "H" indicating the arrival of the check cell is output.

The output of the AND circuit 42 becomes "L" as shown in FIG. 7 corresponding to the 6th and 7th bytes of the input cell. At this time, if all of the 8 bits of input data are 1, the output of the AND circuit 44 becomes "H", and the value is input to the flip-flop 48. OR circuit 4 at this time
"H" is input to one of the input terminals of the input terminal 5, that is, the terminal to which the output of the VCI monitor 41 is input. Further, as shown in FIG. 7, a signal in which only the 6th byte becomes'L 'is input to the other terminal, and the output of the OR circuit 45 causes the signal to rise, that is, at the boundary between the 6th byte and the 7th byte. And circuit 4 on page 48
The output of 4 is set, and the output of the flip-flop 48 becomes "H" indicating the normality of all 1's test data.

Similarly, the output of the AND circuit 43 becomes "L" at the 8th and 9th bytes. NOR circuit 47
8 bits of input data are also input to this, and when the 8 bits of input data and the signal all become'L ', the NOR circuit 47 outputs'H' to the flip-flop 49, and this value is flip-flop. Similarly to the case of the flip-flop 48, the output of the OR circuit 46 sets it at the boundary between the 8th byte and the 9th byte, and the output of the flip-flop 49 becomes "H" indicating the normality of all 0's test data.

In FIG. 6, the data check result is set to "OK" only when all the 3 bits of the outputs of the VCI monitor 41 and the two flip-flops 48 and 49 are all "H", and this determination result is set to the check cell. The data can be held correspondingly and notified to the software side as status data, or can be displayed by using an LED. For example VC
When the output of the I monitor 41 reaches the check cell and the output of the flip-flop 48 does not become "H", the stack of bit lines is 0, and when the output of the flip-flop 49 does not become "H", the stack of 1 of the bit line is It has been detected.

[0028]

As described above in detail, according to the present invention, it is possible to check data without transmitting a parity bit and reduce the number of signal lines. Further, it becomes possible to detect the stack of bit lines, which greatly contributes to the improvement of the reliability of the ATM transmission system.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing the overall configuration of an ATM transmission system using the data check method of the present invention.

FIG. 3 is a diagram showing a format of a check cell.

FIG. 4 is an explanatory diagram of an enable signal indicating a distinction between a valid cell and an invalid cell.

FIG. 5 is a block diagram showing a configuration of a check cell generation circuit.

FIG. 6 is a block diagram showing a configuration of a check cell confirmation circuit.

FIG. 7 is a diagram illustrating a check result output control signal.

[Explanation of symbols]

 1 ATM Transmission System 2 Check Cell Generating Means 3 Check Cell Confirming Means 11 Cell Synchronizing Unit 12, 16 Subscriber Interface 14 Switch Unit 20, 40 Shift Register 22 VCI Assigning Unit 41 VCI Monitor 48, 49 Flip Flop

Claims (3)

[Claims] 1. An ATM transmission system for transmitting data contained in cells in 8-bit parallel, wherein an ATM transmission system is a check cell in which test data of 8-bit all 0s and 8-bit all 1s is inserted in one cell. Check cell generating means (2) to be input to (1), and a check cell for confirming the normality of 8-bit all-0 and 8-bit all-1 test data of the check cell output from the ATM transmission system (1) A data check method in an ATM transmission system, comprising a confirmation means (3). 2. The check cell confirmation means (3) is a bit indicating the arrival of the check cell, 8 bits all 0s.
The total number of bits indicating the normality of the test data of 8 and the normality of the test data of all 8 bits is 3
2. The data check method in an ATM transmission system according to claim 1, wherein the data check result is displayed by bits. 3. The check cell confirmation means (3) is provided at each of a plurality of locations in the ATM transmission system, and it is possible to check a partial system from the check cell generation means (1) to each of the plurality of locations. The data check method in the ATM transmission system according to claim 1 or 2, wherein