JPH06275080A - Method and circuit for writing data of semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a method and a circuit for writing data of a semiconductor memory capable of eliminating the skew in a pulse signal and reducing a pulse width for making a write recovery time zero. CONSTITUTION:A logic circuit 30 consisting of a chip selection signal CSB and a write enable signal WEB, and the logic circuit 31 consisting of a data input signal DIN and the output signal of the logic circuit 30 are arranged on one position in a chip. After the output signals of the logic circuits 30, 31 are transmitted to the whole chip, are inputted to the logic circuits 14 arranged in the common data line of every memory mat together with a decoding signal. A pulse generation circuit 11 is connected to the logic circuit 14, and the common data line is driven by the output signal of the circuit 11, that is, the pulse signal to write the data in a memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a clock signal and the like.
The present invention relates to a semiconductor integrated circuit device that uses a pulse signal as a control signal, and more particularly to a write circuit of a semiconductor memory in which data is written with a pulse signal in order to achieve a write recovery time of zero in a static random access memory (SRAM).

[0002]

2. Description of the Related Art A conventional SRAM write circuit has a method of starting recovery of a data line at the rise of an external write enable signal (WEB). The problem with this writing method is that when the decoder speeds up, the sub-word line (SWL) switches before the data line recovers, causing erroneous writing and write recovery access delay. In other words, the specification that the write recovery time is set to zero cannot be achieved. Therefore, the problem of write recovery is becoming more prominent in a high-speed SRAM having a high-speed decoder circuit.

As a means for solving this problem, a cell flight system, which is a circuit system for writing data with a pulse signal, has been proposed. Figure 4 shows a functional block diagram of this cell flight method, and Figure 3 shows a schematic diagram of the circuit layout in the SRAM chip. External write enable signal (W
EB) Chip select signal (CSB) and data input signal (DIN)
Is provided with a logic circuit 20 for receiving the output signal,
Similarly, a pulse signal is generated by a pulse generation circuit 21 arranged in one chip. After transmitting the pulse signal to the chip, the output signal of the logic circuit 23 and the pulse generated by the pulse generation circuit 21 with the mat selection signal (MS) and the inhibit signal (INH) which are other control signals as input signals. The logic of the signal is taken by multiple logic circuits 22 arranged in the chip, and this signal (
(Pulse) Common data lines, CDL0, CDLB0 to CDLn, CDLBn are driven to write data.

(Japanese Patent Application Laid-Open No. 4-69893) The SRAM write circuit using the pulse signal has been described above, but the general LSI is as follows. Figure 6 is a functional block diagram showing the generation method of pulse signals such as clock signals in a conventional LSI. In the figure, the output of the logic circuit 1 provided at one place in the LSI chip is received, a pulse signal is generated by the pulse generation circuit 6 also provided at one place in the chip, and this pulse signal is transmitted to the chip. The logic circuit 4 takes the logic of the output of the logic circuit 3 that receives other control signals and the pulse signal output from the pulse generation circuit 6, generates the pulse signal at the required location, and outputs it as the final pulse signal. I was using it. That is, in the chip, the logic circuit
Multiple 4's were formed and the output of 4 was used as a pulse signal.

[0005]

The above-mentioned problems of the cell flight system will be specifically described as follows.

The first point is that WEB, CSB,
This is the point where an internal pulse signal (PSG) consisting of DIN is formed and transmitted inside the chip. As the chip area increases, internal pulse signal (PSG) skew and waveform distortion become noticeable.
The timing of the internal pulse signal (PSG) varies greatly depending on the location in the chip, which makes designing difficult.

The second point is that the common data line (CDL) drive signal, which is the final write control signal, is formed by taking the logic with the mat select signal (MS) after forming the pulse signal. is there. As the memory capacity and the chip area increase, the temporal variations of PSG and MS in the chip increase, and the PSG pulse width margin must be increased. As a result, the difference between the pulse widths of external WEB and external DIN becomes smaller, and the effect of the cell flight method becomes smaller.

The third point is that the PSG controls the CDL.
This is because the PMOS load of the data line is controlled by the external WEB as in the conventional method. The most effective way to recover the data line is the PMOS load, and controlling the PMOS load control signal via the WEB without using the PSG significantly reduces the effect of the cell flight method. Furthermore, in the case of this cell flight method, the same data is
Is fixed to Low and DIN is fixed, and it is not possible to write to different addresses by switching only the address signal.
There is a drawback that.

The above-mentioned problem of the SRAM write circuit using the pulse signal is a solution problem common to all semiconductor integrated circuits using the pulse signal. That is, as the chip area increases, the skew of the pulse signal becomes a problem, and if the control signal other than the pulse signal is taken as logic, the pulse width cannot be accurately controlled because the timing with the control signal differs depending on the place in the chip ( In some cases, the pulse disappears.)

The present invention has been made in view of the above circumstances, and an object thereof is to provide a write circuit for a semiconductor memory, which is suitable for a large-capacity, high-speed SRAM and has a write recovery time of zero. To do.

[0011]

In a semiconductor integrated circuit device of the present invention, an integrated circuit chip is divided into a plurality of circuit blocks, and a pulse signal used as a clock signal and various control signals in each integrated circuit chip is provided in each circuit block. It is characterized in that it is generated by a pulse generation circuit provided in a unit, and the pulse signal generated by each pulse generation circuit is directly used as a target pulse signal without taking logic with other signals.

The semiconductor integrated circuit device according to the present invention is characterized in that the pulse generation circuit keeps fan-out or output load capacitance constant in the integrated circuit chip.

The semiconductor integrated circuit device according to the present invention is characterized in that the pulse generating circuit forms a required pulse width in each circuit block unit.

The semiconductor memory writing method of the present invention is
In a writing method of a semiconductor memory for writing data to a memory cell by setting a potential of one data line of the data line pair lower than a potential of the other data line, a plurality of data line pairs are connected via a switch means. If the potential of one common data line of the pair of common data lines is lower than the potential of the other for a certain period of time, the data line will be written even though the external write enable signal (WEB) instructs writing. It is characterized in that the electric potential of is automatically restored to the other electric potential which is not lowered.

The write circuit of the semiconductor memory of the present invention is
A common data line drive signal forming circuit for driving a common data line, a delay circuit using an output signal of the common data line drive signal forming circuit as an input signal, an output signal of the common data line drive signal forming circuit, and the delay circuit And a logic circuit that forms an internal write pulse by taking a logic with the output signal of 1. and drives the common data line by the internal write pulse output from the logic circuit.

The write circuit of the semiconductor memory of the present invention is
The delay circuit holds the input signal high for a certain period of time.
It is a circuit that outputs Low.

The write circuit of the semiconductor memory of the present invention is
The delay circuit comprises an inverter circuit and a 2-input NAND gate circuit.

The write circuit of the semiconductor memory of the present invention is
The delay circuit holds the input signal low for a certain period of time.
It is a circuit that outputs High.

The write circuit of the semiconductor memory of the present invention is
The delay circuit comprises an inverter circuit and a 2-input NOR gate circuit.

A semiconductor memory data write circuit of the present invention is a semiconductor memory write circuit for writing data to a memory cell by setting the potential of one data line of a data line pair to be lower than the potential of the other data line. At
When the data line holds a low potential for a certain period of time, the potential of the data line is automatically restored to the other potential that has not been lowered, even though the external write control signal (WEB) instructs writing. It is characterized by

The semiconductor memory writing method of the present invention is
Chip select signal (CSB), external write enable signal (WEB),
A logic signal consisting of a data input signal (DIN) and a memory block selection signal (BS) becomes a potential for instructing data writing, and if this potential is held for a certain period of time, the external write enable signal (WEB) instructs writing. Nevertheless, it is characterized in that writing is canceled and data line recovery is started. The semiconductor memory write circuit according to the present invention includes a chip select signal (CSB) and an external write enable signal.
(WEB), data input signal (DIN), memory block selection signal (B
S) a logic signal generating circuit for generating a logic signal, a delay circuit having an output signal of the logic signal generating circuit as an input signal, a logic of the output signal of the logic signal generating circuit and the output signal of the delay circuit And a logic circuit for controlling writing by the output signal of the logic circuit.

The semiconductor memory write circuit of the present invention is
13. The semiconductor memory writing circuit according to claim 12, wherein the delay circuit is a circuit similar to the logic circuit according to claim 6.

The write circuit of the semiconductor memory of the present invention is
The delay circuit is the same circuit as the logic circuit according to claim 8.

The write circuit of the semiconductor memory of the present invention is
The delay circuit is the same circuit as the logic circuit according to claim 7.

The write circuit of the semiconductor memory of the present invention is
The delay circuit is the same circuit as the logic circuit according to claim 9.

The write circuit of the semiconductor memory of the present invention is
An address transition detection signal forming circuit for forming a signal for detecting an address transition state, and a pulse stretch circuit for extending the pulse width of the address transition detection signal forming circuit,
A write control pulse is formed on the basis of an output signal of the pulse stretch circuit, thereby writing the same data in memory cells having different addresses.

In the semiconductor memory of the present invention, the memory cell has a pair of read-only data lines and a pair of write-only data lines, and each data line pair has a read-only common data line and a write via the switch means. It is characterized by being connected to a dedicated common data line.

The write circuit of the semiconductor memory of the present invention is
The write control signal (WEB, CSB) is sent as a signal with a lower amplitude than the signal of the decoder system up to the memory mat or memory blocks consisting of multiple memory mats, and a level conversion circuit is provided for each memory mat or memory block. It is characterized by having.

The method of writing data in the semiconductor memory of the present invention is characterized in that the set time of the data input signal DIN ends before the rise of the write enable signal. The semiconductor memory data writing method of the present invention is characterized in that the write pulse width tWP is always smaller than the address cycle time tWC.

The semiconductor memory of the present invention is a semiconductor memory having a pair of data lines in memory cells, wherein one data line is used as a read-only data line and the other data line is used as a write-only data line. And

To precisely control the write control pulse, the pulse is formed by a signal as close as possible to a signal for writing data in the memory cell.
In other words, ideally, the potential of one of the data line pairs (DL, DLB) of the memory cell section you want to write is low for a certain period of time.
A stable cell flight method can be realized if it is a method that automatically starts recovery after holding. In other words, the data line completion information may be fed back to the write circuit and the data line recovery may be started. However, a pulse generation circuit is required to form the write pulse, and it is not practical to provide this circuit for each data line because the circuit scale becomes huge.

Therefore, as shown in FIGS. 1 and 2, a cell flight system is devised in which a pulse generating circuit 11 is provided for each common data line CDL to form an internal write pulse, and this signal is used to directly drive the common data line. . Figure 1 shows a schematic diagram of the circuit layout of this method in a memory chip. A logic circuit 30 with WEB and CSB as input signals is placed at one location in the chip, and each data is also placed at one location in the chip.
Place 31. The output signals of the logic circuits 30 and 31 are transmitted to the entire chip and then input to the logic circuit 14 arranged in each mat in units of common data lines (CDL). Further logic circuit 14
When a decode signal is input to, and all three signals instruct writing, the logic circuit 14 outputs a signal instructing to write, and the pulse generation circuit 11 arranged in CDL unit in each mat as well as the logic circuit 14 outputs the pulse signal. Output and data is written. As described above, since the pulse signal is not transmitted using the long wiring, the writing can be controlled with an accurate pulse width without considering the signal skew and the like.

FIG. 2 is a schematic diagram showing the function of the write circuit of the semiconductor memory according to the present invention in the form of a logic circuit.
MS is a mat selection signal, DSEL is a data selection signal (for example, in the case of a chip configuration with a maximum of × 8 (bits) input / output, select data corresponding to × 4 (bits) × 1 (bits).), INH
Is an inhibit signal. When all the signals such as MS, DSEL, DIN, WEB, INH are in the state to instruct to write, the logic circuit, 30, 31, 13 outputs the signal to instruct to write to the logic circuit 14, and the logic circuit, 14 writes Is output to the pulse generation circuit 11, a negative pulse is formed, the common data line (CDL) is kept low for a certain period of time, and data is written. As described above, since the pulse signal is generated after the logic of all the signals necessary for forming the write pulse is taken, it is not necessary to consider the timing margin of the pulse signal and the control signal unlike the conventional method, A pulse having a small pulse width can be formed with good controllability.

Further, using this negative pulse signal,
High-speed write recovery can be realized by forming the data line recovery control signal, φWP1 data line equalization control signal, φWP2, etc. before the rise of the external write enable signal (WEB) (FIG. 17).

The solution to the above-mentioned problem can be solved by satisfying the following requirements as a general means when it is expanded to other than the write circuit. That is, the means for accurately controlling the timing and pulse width of the pulse signal is as follows.

1) The pulse signal is formed after the logics of all the signals necessary for forming the pulse signal (the signal finally required) are taken.

2) The pulse signal is formed into a pulse in a required circuit block unit. That is, a plurality of pulse generation circuits are provided in the chip.

3) After the pulse signal is formed, the pulse signal is directly used without taking the logic of other signals.

FIG. 5 is a functional block diagram showing a pulse forming system according to the present invention based on the above basic concept. Conventionally, the pulse was formed only from the output of the logic circuit 1, but in the present invention, the pulse is formed after the logics of the logic circuits 1 and 3 are taken. That is, a new logic circuit 5 is provided and the logic circuit 5
Form a pulse signal from the output signal of. Further, a plurality of logic circuits 5 and pulse generation circuits 2 are arranged in the chip under the conditions 2) and 3) described above.

[0040]

The pulse generation circuit provided for each pair of common data lines is arranged in the vicinity of the memory mat and acts on all signals other than the column selection signal to provide a stable internal pulse for writing data. it can. In addition, this pulse generation circuit is a circuit that does not generate a pulse unless the writing state is held for the time set by the common data line drive signal, and there is no risk of erroneous writing due to hazards or the like. Has become.

Further, when the present invention is applied to an LSI in general, since a pulse signal can be used without taking a logic with other signals after pulse formation, that is, the pulse signal is not processed by another signal, the pulse signal is applied to each circuit block. Has a stable supply function.

[0042]

Embodiments of the present invention will be described below with reference to the drawings.

An embodiment in which the present invention is applied to a write circuit will be described below with reference to the drawings. (Basic Configuration) FIG. 7 is a logical diagram showing the basic configuration of the present invention shown in FIG. 2 for one common data line pair. The mat selection signal (MS) and data selection signal (DSEL) become High, and the output of the 2-input NAND gate circuit (BiNMOS gate circuit) 51 is Low.
Then, when the internal write enable signal (WE) becomes High, the output of either of the two 3-input NOR gate circuits 52 and 53 becomes High. The pulse forming circuit (delay circuit) 54 is set to High when the internal write enable signal (WE) is Low. Therefore, for example, the output of the 3-input NOR gate circuit 52 '
When A ′ becomes High, the output of the 2-input NAND gate circuit 55, that is, the potential of the common data line CDL becomes Low, and the data is written. Furthermore, if the signal'A 'is held High for the minimum time tW (for example, 3 ns) required for data writing, the output'AD' of the pulse forming circuit 54 outputs Low and the output of the 2-input NAND gate circuit 55 High, WE signal is high
Even in (write state), writing ends and data line recovery starts.

In FIG. 7, φWP1, φWP2, and φWP3 are data line load control signal, common data line (read-only common data line) and data line recovery control signal, respectively.
Data line and common data line equalization control signal. Both are formed using the signals'A 'and'AD', that is, in order to control the signals φWP1, φWP2, φWP3 by the internal pulse, only the common data line CDL is controlled by the internal pulse. Data line recovery can be achieved at a higher speed than the cell flight method. ATD is an address transition detection signal and outputs a positive pulse at address transition. This is a signal for equalizing the data line and the common data line when reading data. That is, in this embodiment, the equalizing MOSFET at the time of write recovery and the equalizing MOSFET at the time of reading are made common by combining the ATD signal and φWP1.

FIG. 8 is a timing chart showing the above-mentioned operation principle. External write enable signal WEB
Goes low, and when the data input signal DIN is fixed, the signal'A 'goes high, the common data line CDL goes low, and the write state is set. When the signal'A 'is held High during the data writing time tW, the signal'AD' becomes Low and the writing is completed. In other words, when writing data, the signal is'
Determined by the rising edge of A ', the end of data writing is signal'A
Determined by D '. The data writing time is determined by the delay time of the pulse forming circuit 54. In this way, the external write enable signal (W
Even though EB) is Low, the common data line CDL is recovered, and it can be seen that the cell flight system is realized.

A concrete configuration of the pulse forming circuit 54 shown in FIG. 7 is shown in FIG. It is composed of an inverter circuit, a 2-input NAND gate circuit, and a 3-input NAND gate circuit. In the figure,
The signal described as WATD is a signal obtained by converting the ATD signal into a pulse width of the time required for writing data in the pulse stretch circuit (negative pulse). When the input signal'A 'is held High for a certain period of time, the output signal'AD' outputs Low. The operation mechanism of this pulse forming circuit is as follows. By taking the AND logic of the output signal'A1 'and the input signal'A' which delayed the input signal'A 'by two stages of the inverter circuit, the signal is output only when the input signal'A' and the output signal'A1 'are High. 'A2' goes high. Further, by taking the AND logic of the signal'A2 'and the signal'A', the output signal'A3 'becomes High only when the signal'A2' is High from the input signal'A '. In this way, when the input signal'A 'holds High from the time t0 when the signal'A' is input to the time t4 when the signal'A4 'is output, the output signal'AD' becomes Low. That is, if there is a Low time from time t0 to time t4, the output signal'A
D'does not output Low and is always High. In the above description, WATD is fixed at High.

Next, the WATD signal forming circuit will be described. FIG. 10 shows an embodiment. Inverter circuit and 2-input NO
It consists of an R gate circuit. The operation mechanism of this circuit will be described with reference to the timing chart shown in FIG.
When the ATD signal, which is a positive pulse, is input at time t0, the signal ATD1 delayed by two stages of the inverter circuit is output at time t1. By taking the OR logic of the input signal ATD and the signal ATD1, the input signal ATD becomes the stretched signal ATD2. By repeating this operation, the ATD pulse becomes
The signal is stretched from t1 to t4, and converted into a negative pulse by the last 2-input NOR gate circuit (BiNMOS gate circuit) 80. For example, when one memory mat is provided with one WATD signal formation circuit, writing is completed for one address, and the same data is written after changing the address after the signal'AD 'shown in Figs. 7 and 9 goes low. The low pulse of WATD causes the 3-input NAND gate circuit, 70 outputs, and'AD 'to be Hi.
Reset to gh and'A 'is High, 2 in Figure 7
The input NAND gate circuit, 55 goes low again and the data is written.

(Overall Structure) The basic structure of the present invention has been described above. The overall structure of the write circuit designed based on the basic structure of the present invention will be described below.

FIG. 12 is a diagram showing a wiring image of the external write enable signal WEB and the data input signal DIN. Multiple memory mats (8 mats or
A memory block consisting of 16 mats) is composed of 8 blocks, and data input / output has a maximum of 8 bits. That is, the number of data input signal lines DIN is eight. In the figure, BS is a block selection signal, and when it is High, a memory block is selected. When the memory block is not selected, the block selection signal BS is low, so the output of the 2-input NOR gate circuit (BiNMOS circuit) 100 is fixed low regardless of whether the external write enable signal WEB or the data input signal DIN is low or high. This is because the external write enable signal (W
This is because EB) WEB and the data input signal line DIN are activated. After the output of the 2-input NOR gate circuit 100, the write enable signal, WEB, becomes the positive signal WE that is in the write state when High.

FIG. 13 is a diagram showing a circuit (a circuit represented by WEBBF in FIG. 12) from the output of the WEB buffer to the entrances WEBL and WEBR of the WEB signal lines on the left and right of the chip. WE unless the chip select signal CSB is Low (chip selected)
BL and WEBR are fixed at Low, thus reducing power consumption. Figure 13
Among them, the plurality of inverter circuits 110 have a delay time of WEBL, W until the mat selection signal MS is output to prevent erroneous writing.
This is a circuit to delay the output of EBR.

FIG. 14 is a diagram showing a circuit (a circuit represented by DINBF in FIG. 12) from the output of the DIN buffer to the DINL and DINR entrances of the DIN signal lines on the left and right of the chip. DINL, DIN, except when WECS, which is a signal that is High when a chip is selected and a write is instructed, shown in Fig. 13 is High
R is fixed to Low, which reduces power consumption.

The write control signal generation circuit arranged in each memory mat receives the WE, DIN signals and the decoding system signals such as MS, DSEL distributed to each memory mat as described above.
A signal that finally controls writing, such as a CDL drive signal, is formed.

FIG. 15 shows an embodiment of a write control signal generation circuit arranged in each memory mat, one set. Based on Fig. 7, this is a circuit that assumes × 4 (bit) and × 8 (bit) input / output. When the output of the 2-input NAND gate circuits 130 and 131 is × 4 (bit), either of them becomes LOW, and when the output is × 8 (bit), both of them are fixed to LOW. Signals φWP10, φWP20, WP30 are added to the timing chart shown in Fig. 8 and shown in Fig. 17. Data line load control signal φWP10,
Since the data line / common data line recovery control signal φWP20 and the data line / common data line equalize signal φWP30 are also controlled by the internal pulse as shown in the figure, high speed write recovery can be realized.

FIG. 16 is a diagram showing a pair of data lines. The common data line is a read-only common data line
(R-CDL) and write-only common data line (W-CDL). YSB is a column selection signal. Data line load PMOS142, common data line load PMOS14
6 Signal is φWP1, data line recovery PMOS143, common data line (R-CDL) recovery PMOS144 are controlled by signal φWP2, data line equalize PMOS141, common data line (R-CDL) equalize PMOS145 are controlled by signal φWP3, respectively. There is.

In the write circuit having the above configuration, when the data write time tW described above is set to 4 ns and the external write enable signal WEB and the data input signal DIN are simulated with the minimum pulse width of 8 ns, the data line is It was clarified that it is possible to easily recover the write recovery time tWR to zero by recovering 2ns earlier than the rising edge of the enable signal WEB.

(Other Embodiments) In the embodiments described above, the circuit scale is larger than that of the conventional method because the pulse forming circuit is provided for each common data line. Therefore, a pulse forming circuit is provided for each memory block to design an internal write pulse.

FIG. 18 shows an embodiment in this case. The figure shows the case of × 8 (bit) input for one memory block. When the block selection signal BSB goes low,
For each DIN signal, the output of either one of the 2-input NOR gate circuits, 160 is High. Then the pulse forming circuit 54
As a result, a negative pulse in which the potential of either the DIN line or the DINB line is low for a certain period of time is obtained using the same principle as described above. The write control circuit shown in FIG. 15 arranged in each memory mat receives this signal and the cell flight system is realized. In this method, the number of DIN lines is doubled, although the hardware is reduced compared to the case where the pulse forming circuit is provided for each common data line.

FIG. 19 shows another embodiment of the write control circuit shown in FIG. It is shown for one common data line pair. Mat selection signal MSB, data selection signal DS
When ELB and write enable signal WEB are all Low, 3
One of the input NAND gate circuits 171 becomes Low. Then, the pulse forming circuit 170 goes low when WEB is high.
Since it is set, one of the 2-input NOR gate circuits 172 becomes High, CDL or CDLB becomes Low, and data is written.

The pulse forming circuit 170 is a circuit which outputs High when the input signal holds Low for a certain time (tW).
After tW, when the output becomes High, the output of the 2-input NOR gate circuit 172 becomes Low, and the write recovery is automatically started.

(Embodiment Other than Writing Circuit) An embodiment other than the writing circuit will be described below.

FIG. 20 is a circuit block diagram showing a case where the present invention is applied to a microprocessor. The accumulator, ALU, instruction register, and register file are each provided with a logic circuit 180 and a pulse generation circuit 181, and a pulse signal is formed from the logic of the signal formed by the control circuit and the external clock signal (if necessary), and the control signal is generated. I am trying. A plurality of logic circuits 180 and pulse generation circuits 181 may be provided in the circuit block as needed. As described above, unlike the case where a pulse signal is transmitted from one pulse generation circuit to a large number of circuit blocks, the microprocessor can be operated with a pulse signal having accurate timing and pulse width, and the speed can be increased.

FIG. 21 is a circuit block diagram of a microprocessor when the present invention is not used. Logic circuit 190,
The pulse generation circuit 191 is formed in one chip, and the pulse signal is transmitted through the internal signal bus 192. Further, a logic circuit 193 provided in each circuit block takes a logic with a control signal as needed to obtain a final pulse signal.

This system has a problem such as a skew of a pulse signal generated by the internal signal bus 192, and further has a problem with the timing with respect to the control signal, so that it is difficult to control accurately.

[0064]

The effect of applying the present invention to a write circuit is that it is not necessary to consider the skew of the pulse signal, the timing margin of the pulse signal and other control signals, and the narrow pulse signal is used as the write pulse. Can be used.
Therefore, before the external write enable signal, WEB rise,
In order to start the recovery of the data line, erroneous writing,
Since the margin for the write recovery access delay can be set sufficiently large, the write recovery time tWR can be easily set to zero.

[Brief description of drawings]

FIG. 1 is an image diagram of a cell flight type chip according to the present invention.

FIG. 2 is a basic conceptual diagram of a cell flight system according to the present invention.

FIG. 3 is a view of a conventional cell flight type chip image.

FIG. 4 is a basic conceptual diagram of a conventional cell flight system.

FIG. 5 is a basic conceptual diagram of a pulse signal generation circuit of the present invention.

FIG. 6 is a basic conceptual diagram of a conventional pulse signal generation circuit.

FIG. 7 is a diagram showing one embodiment shown in FIG. 2 for one common data line.

FIG. 8 is a timing chart showing a cell flight method according to the present invention.

FIG. 9 is a circuit diagram showing an embodiment of a pulse forming circuit.

FIG. 10 is a circuit diagram showing an embodiment of a WATD forming circuit.

FIG. 11 is a timing chart showing an operating state of the WATD forming circuit.

FIG. 12 is an explanatory diagram showing in-chip wiring images of a write enable signal, WEB, a data input signal, and DIN.

FIG. 13 is a circuit diagram showing an embodiment of a WEB signal forming circuit.

FIG. 14 is a circuit diagram showing an embodiment of a DIN signal forming circuit.

FIG. 15 is a circuit diagram showing an embodiment (1 set / memory mat) of a write control signal generation circuit.

FIG. 16 is a schematic diagram of one data line pair.

FIG. 17 is a tinging chart showing the output timing of various internal pulses.

FIG. 18 is a circuit diagram showing an embodiment in which a pulse forming circuit is provided for each memory block.

FIG. 19 is a circuit diagram showing another embodiment of the write control signal generation circuit.

FIG. 20 is a circuit block diagram when the present invention is applied to a microprocessor.

FIG. 21 is a circuit block diagram of a conventional microprocessor.

[Explanation of symbols]

 1 logic circuit 3 logic circuit 4 logic circuit 5 logic circuit 12 logic circuit 13 logic circuit 14 logic circuit 20 logic circuit 22 logic circuit 23 logic circuit 25 logic circuit 30 logic circuit 31 logic circuit 180 logic circuit 190 logic circuit 193 logic circuit 2 pulse Generation circuit 6 Pulse generation circuit 11 Pulse generation circuit 21 Pulse generation circuit 181 Pulse generation circuit 191 Pulse generation circuit 32 Memory mat 33 Peripheral circuit 51 2 input NAND gate circuit 55 2 input NAND gate circuit 56 2 input NAND gate circuit 130 2 input NAND Gate circuit 131 2-input NAND gate circuit 52 3-input NOR gate circuit 53 3-input NOR gate circuit 54 pulse forming circuit 170 pulse forming circuit 70 3-input NAND gate circuit 171 3-input NAND gate circuit 80 2-input NOR gate circuit 100 2-input NOR Gate Road 160 two-input NOR gate circuit 172 two-input NOR gate circuit 110 inverter circuit 192 internal data bus 140 data lines fixed loading PMOS 141 data line equalizing PMOS 142 data line control load PMOS 143 data line recovery PMOS. 144 common data line recovery PMOS 145 common data line equalize PMOS 146 common data line control load PMOS. 147 Y switch (NMOS) 148 Y switch (PMOS)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H01L 27/11 6866-5L G11C 11/34 362 H 7210-4M H01L 27/10 381 (72) Invention Shinya Mitsumoto 111, Nishiyokote-cho, Takasaki-shi, Gunma Prefecture, Hitachi, Ltd. Semiconductor Design Development Center

Claims (22)

[Claims] 1. An integrated circuit chip is divided into a plurality of circuit blocks, and pulse signals used as clock signals and various control signals in the integrated circuit chip are generated by a pulse generation circuit provided for each circuit block, A semiconductor integrated circuit device characterized in that a pulse signal generated by a pulse generation circuit is directly used as a target pulse signal without taking a logic with other signals. 2. The semiconductor integrated circuit device according to claim 1, wherein the pulse generation circuit keeps fan-out or output load capacitance constant in the integrated circuit chip. 3. The semiconductor integrated circuit device according to claim 1, wherein the pulse generation circuit forms a required pulse width in each circuit block unit. 4. A semiconductor memory writing method for writing data to a memory cell in which a potential of one data line of a data line pair is lower than a potential of another data line, and a plurality of data line pairs are switch means. If the potential of one of the common data lines of the pair of common data lines connected via is kept lower than the potential of the other for a certain period of time, the external write enable signal (WEB) may indicate writing. Regardless, a method for writing data in a semiconductor memory, which automatically recovers the potential of the data line to the other potential which is not lowered. 5. A common data line drive signal forming circuit for driving a common data line, a delay circuit using an output signal of the common data line drive signal forming circuit as an input signal, and an output of the common data line drive signal forming circuit. A semiconductor memory having a logic circuit that forms an internal write pulse by taking a logic between a signal and an output signal of the delay circuit, and drives the common data line by the internal write pulse output from the logic circuit. Writing circuit. 6. The input signal of the delay circuit is Hi for a certain period of time.
The semiconductor memory write circuit according to claim 5, wherein the write circuit is a circuit that outputs Low when gh is held. 7. The semiconductor memory write circuit according to claim 6, wherein the delay circuit includes an inverter circuit and a 2-input NAND gate circuit. 8. The delay circuit, wherein the input signal is Lo
The semiconductor memory write circuit according to claim 5, wherein the write circuit is a circuit that outputs High when w is held. 9. The write circuit of a semiconductor memory according to claim 8, wherein the delay circuit is composed of an inverter circuit and a 2-input NOR gate circuit. 10. In a writing circuit of a semiconductor memory for writing data to a memory cell in which a potential of one data line of a data line pair is lower than a potential of another data line, the potential of the data line is low for a certain period of time. Holds, the semiconductor memory is characterized by automatically recovering the potential of the data line to the other potential that has not been lowered even though the external write control signal (WEB) has instructed to write. Data writing circuit. 11. A logic signal composed of a chip selection signal (CSB), an external write enable signal (WEB), a data input signal (DIN), and a memory block selection signal (BS) becomes a potential for instructing data writing and is constant. If this potential is held for a time,
A method for writing to a semiconductor memory, wherein writing is canceled and recovery of a data line is started even though the external write enable signal (WEB) signal instructs writing. 12. A logic signal generation circuit for generating a logic signal including a chip selection signal (CSB), an external write enable signal (WEB), a data input signal (DIN) and a memory block selection signal (BS), and the logic signal. A delay circuit having an output signal of the generation circuit as an input signal; and a logic circuit taking a logic between the output signal of the logic signal generation circuit and the output signal of the delay circuit,
A writing circuit of a semiconductor memory, wherein writing is controlled by an output signal of the logic circuit. 13. The delay circuit is the same circuit as the logic circuit according to claim 6, wherein:
A semiconductor memory writing circuit according to item 1. 14. The delay circuit is the same circuit as the logic circuit according to claim 8.
A semiconductor memory writing circuit according to item 1. 15. The delay circuit is the same circuit as the logic circuit according to claim 7.
A semiconductor memory writing circuit according to item 1. 16. The delay circuit is the same circuit as the logic circuit according to claim 9, wherein:
A semiconductor memory writing circuit according to item 1. 17. An address transition detection signal forming circuit for forming a signal for detecting an address transition state, a pulse stretch circuit for extending a pulse width of the address transition detection signal forming circuit, and an output signal of the pulse stretch circuit. A writing circuit for a semiconductor memory, comprising means for writing the same data to memory cells having different addresses by forming a write control pulse. 18. The memory cell has a pair of read-only data lines and a pair of write-only data lines, each data line pair being a read-only common data line and a write-only common data line via a switch means. A semiconductor memory characterized by being connected. 19. A write control signal (WEB, CSB) is sent as a signal having a lower amplitude than a decoder system signal up to a memory mat or a memory block including a plurality of memory mats, and each memory mat or each memory block. A writing circuit for a semiconductor memory, characterized in that it has a level conversion circuit. 20. The set time of the data input signal DIN is
A method for writing data in a semiconductor memory, which is completed before the rise of a write enable signal. 21. A method of writing data in a semiconductor memory, wherein a write pulse width tWP is always smaller than an address cycle time tWC. 22. A semiconductor memory having a pair of data lines in a memory cell, wherein one data line is used as a read-only data line and the other data line is used as a write-only data line.