JPH0627024Y2 - Digital information demodulator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital information demodulation device, and more particularly to a PCM.
The present invention relates to a digital information demodulation device for extracting a PCM digital signal from a reproduction RF signal obtained by reproducing a recording disc on which a digital signal is recorded and demodulating the extracted PCM digital signal.

BACKGROUND ART In a device of this type, since a reproduced digital signal contains jitter, which is a time-axis fluctuation component, due to rounded edge shapes of pits on a recording disc, variations in characteristics of an optical system in a pickup, and the like, In general, a clock signal is extracted from the reproduced digital signal, and the reproduced digital signal is latched by this clock signal to suppress the jitter and then demodulate.

By the way, in the digital audio disc player, the demodulation system is composed of a one-chip LSI (large scale integrated circuit), and this LSI also includes a signal processing circuit for suppressing the above-mentioned jitter. Moreover, in an actual product, the digital processing system and the audio processing system are not completely separated, so that digital data including, for example, jitter is input to the digital processing system, and the jitter component exists in the digital processing system. In this case, this jitter component may adversely affect the audio processing system on the path such as crosstalk.

Therefore, as described above, in the case where the signal processing circuit for suppressing the jitter is integrated with the demodulation system into an IC, the reproduced digital signal at the time of input to the IC contains the jitter. Therefore, the demodulation output, the power supply line, and the like are adversely affected by the jitter component, and especially the S / N of the audio signal is deteriorated and the sound quality is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and by reliably suppressing the jitter contained in the reproduced digital signal, the S / N, etc., of the reproduced digital signal after the demodulation system caused by the jitter component. It is an object of the present invention to provide a digital information demodulating device that improves the above.

In the digital information demodulating device according to the present invention, a plurality of signal processing circuits for latching the reproduced digital signal in synchronization with the clock signal included in the reproduced digital signal are arranged in series.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, the RF signal from the pickup 2, which is the information read from the recording disk 1, is transmitted to the MTF by the equalizer 3.
(Modulation Transfer Function) Compensated and further AT
Level slicing is performed by C (Automatic Threshold Control) 4 to obtain a PCM audio signal. This PCM audio signal is an EFM (Eight to Fourteen Modulatio).
n) signal, which is input to the EFM demodulation circuit 6 via the signal processing circuits 5 _{1 to} 5 _n connected in series in a plurality of stages. Of the signal processing circuit 5 ₁ to 5 _n in a plurality of stages, the signal processing circuit 5 _n of the final stage is made up of one-chip LSI together with the demodulation circuit 6. In other words, (n-1) signal processing circuits 5 _{1 to} 5 _n-1 are provided in series in front of the signal processing circuit 5 _n integrated with the demodulation circuit 6 as IC external circuits. It is composed.

As shown in FIG. 2, each of the plurality of stages of signal processing circuits 5 _{1 to} 5 _n includes a clock extraction circuit 50 for extracting a clock signal included in a reproduced digital signal, and a clock signal extracted by the clock extraction circuit 50. And a data latch circuit 51 for latching the reproduced digital signal. The clock extraction circuit 50 is, for example, a VCO.
(Voltage controlled oscillator) 52, frequency divider 53 that divides the oscillation output of VCO 52 into a bit synchronization clock, and phase comparator 54 that uses this bit synchronization clock as a reference input and a reproduced digital signal as a comparison input. PL consisting of
It has an L circuit configuration. It is well known that various settings such as the frequency band or responsiveness of the PLL circuit are arbitrary and are set according to the desired performance. The clock extraction circuit 50 is not limited to the one having the PLL circuit configuration, and may be any circuit that can extract the clock signal included in the reproduced digital signal. on the other hand,
The data latch circuit 51 is composed of, for example, a D-type flip-flop, and has the function of suppressing the jitter contained in the reproduced digital signal by generating the reproduced digital signal synchronized with the transition timing of the bit synchronization clock.

As described above, by further providing the signal processing circuits (5 _{1 to} 5 _n-1 ) in series in front of the IC-formed signal processing circuit 5 _n , the reproduced digital signal is transferred to the IC in a state where the jitter is almost suppressed. Since it can be input, it is possible to improve the S / N and the like of the reproduced digital signal after the demodulation system due to the jitter component included in the reproduced digital signal and obtain an audio output with good sound quality.

In the above embodiment, the signal processing circuit 5 _n integrated into an IC is used.
Although (n-1) signal processing circuits 5 _{1 to} 5 _n-1 are provided in the preceding stage, the number of them is set as necessary, and the effect can be sufficiently obtained even with only one.

Further, in the above-mentioned embodiment, the demodulation circuit 6 uses the signal processing circuit 5 _n.
The case where the signal processing circuits 5 _{1 to} 5 _n-1 are provided as the external circuits in the demodulator having the configuration integrated into an IC and manufactured as a product has been described. However, the present invention is not limited to this. Even when the circuit 6 is individually integrated into an IC, by connecting a plurality of signal processing circuits in series and changing individual characteristics, the jitter included in the reproduced digital signal is increased as compared with the case where there is a single signal. Can be suppressed more reliably, which can contribute to the improvement of the S / N and the like of the reproduced digital signal after the demodulation system caused by the jitter component contained in the reproduced digital signal.

Furthermore, in the above embodiment, a plurality of stages of signal processing circuits 5 ₁
.About.5 _n each have the clock extraction circuit 50 for extracting the clock signal included in the reproduced digital signal, but it is not necessary that all the signal processing circuits 5 _{1 to} 5 _n have the clock extraction circuit 50. As shown in FIG. 3, the signal processing circuit 5'is composed of only the data latch circuit 51 and the frequency divider 55, and as shown in FIG.
It is also possible to use the clock signal extracted by another signal processing circuit and divide this clock signal by the frequency divider 55 to use it as the latch input of the data latch circuit 51.

In each of the above-described embodiments, the case where the present invention is applied to the demodulation device for demodulating the PCM audio signal has been described. However, the present invention is not limited to this, and a clock is extracted from digital data and data is further latched by this clock. Can be applied to any system including a signal processing circuit that suppresses jitter by performing

As described above, according to the digital information demodulating device of the present invention, a plurality of signal processing circuits for latching the reproduced digital signal in synchronization with the clock signal included in the reproduced digital signal are provided in series and the plurality of signal processing circuits are provided. Since at least one of the stages is different from the other stages in the jitter suppression operation characteristic, it is possible to reliably suppress the jitter contained in the reproduced digital signal. Therefore, the S of the reproduced digital signal after the demodulation system caused by the jitter component can be surely suppressed. / N etc. can be improved and an audio output with good sound quality can be obtained. Also,
The present invention is particularly useful for a digital information demodulation device using a demodulation circuit integrated with a signal processing circuit into an IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a concrete configuration of the signal processing circuit in FIG. 1, and FIG. 3 is another configuration of the signal processing circuit. FIG. 4 is a block diagram showing another embodiment of the present invention. Description of the sign of the main portion 1 ...... recording disk 2 ...... pickup 5 ₁ to 5 _n ...... signal processing circuit 50 ...... clock extraction circuit 51 ...... data latch circuit

Claims (2)

[Scope of utility model registration request] 1. Digital information for demodulating the reproduced digital signal that has passed through the signal processing circuit, the signal processing circuit latching the reproduced digital signal in synchronization with a clock signal included in the reproduced digital signal to suppress jitter. In the demodulator, the signal processing circuits are provided in a plurality of stages in series, and at least one of the plurality of stages of the signal processing circuits is a clock signal obtained by extracting a clock signal included in the reproduced digital signal. A digital information demodulating device characterized in that it is a circuit for performing a jitter suppressing operation by latching it on the basis of the above, and at least one of the signal processing circuits has a jitter suppressing operation characteristic different from other circuits. 2. At least one of the plurality of signal processing circuits has a PLL circuit for extracting a clock signal included in the reproduced digital signal, and other signal processing circuits are extracted by the one signal processing circuit. The digital information demodulating device according to claim 1, wherein the reproduced digital signal is latched on the basis of the generated clock signal.