JPH0626999A - Failure code memory device - Google Patents

Abstract

PURPOSE:To simplify memory processing by providing such a constitution as detecting failure generation, when a computer detects a failure of a constituting element, in the memory address of a failure code memory corresponding to the failure code showing the failure in 1:1. CONSTITUTION:An electronic control device 11 is provided with a failure code memory 25 connected to a microcomputer 21. The memory 25 has, for example, 128 memory addresses 26 from n=0 to n=127, and each address 26 is formed in 8 bits. Of the 128 addresses 26, the addresses from n=1 to n=127 are conformed to failure codes of the same numerical values as the respective addresses in 1:1, and when failure codes of a wheel speed sensor 12 are set to, for example, '15', '16', the data related to the failures are stored in the memory addresses 26 of n=15, 16 of the failure code memory 25, respectively. The bit of each address 26 is set to, for example, P=0-7. P=7 represents the presence or absence of failure detection, P=5 and 4 are complements of P=7, 6, fixed data are inputted to P=0-3, and whether a failure is present or not is detected by the display of '1' or '0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault code storage device, and more particularly to a vehicle in which a fault code memory is connected to a microcomputer of a vehicle electronic control device for processing a signal input from a wheel speed sensor or the like. The present invention relates to a failure code storage device, which simplifies the process of storing a failure code indicating a failure of the wheel speed sensor or the like in the failure code memory and prevents replacement of non-defective products, and enables accurate understanding of the failure history. It is a thing.

[0002]

2. Description of the Related Art Conventionally, there has been provided a failure code storage device for storing the occurrence of a failure and the location of the failure when a failure is detected by a wheel speed sensor, an alternator or the like.

The fault code storage device processes signals input from a wheel speed sensor, a motor, a solenoid, etc., an ignition voltage, an alternator voltage, etc., and
A fault code memory is connected to the microcomputer of the electronic control unit that outputs and controls signals to the motor and solenoid valve of the anti-lock control unit based on the result, and when the microcomputer detects a fault occurrence, the fault code memory is stored in the fault code memory. The configuration is such that the location of failure is stored.

Each component of the vehicle, such as a wheel speed sensor,
A corresponding number (fault code) is defined, and when a failure occurrence of a certain element is detected, the failure code corresponding to the component is stored in the failure code memory. For example, in the fault code memory 1 shown in FIG. 5, n = 0 to n =
128 memory addresses 2 shown by 127 are provided, and the failure codes are sequentially stored from the memory address 2 of n = 0 in the order of failure occurrence.

That is, as shown in FIG. 6, first, data is read from the memory address 2 of n = 0 (step #
1), n = 0 if the read data is 0
The failure code is written in (step # 2). On the other hand, when the data is not 0, that is, when the failure code is already stored in the memory address 2 of n = 0, the process moves to the memory address 2 of n = 1 (step # 3), and the same process is performed. repeat.

For example, as shown in FIG. 5, the failure code "$" is assigned to each memory address 2 from n = 0 to n = 2.
When a new failure is detected while 15 "," $ 18 ", and" $ 11 "are already stored, the failure code corresponding to the component that caused the failure is not stored in the data due to the above processing. It is stored in the memory address 2 of the storage n = 3.

If a failure code is already stored in all memory addresses 2 of n = 0 to n = 127 of the failure code memory 1 due to a large number of failures, the failure code memory 1 is first to fail. A special process is required to search the memory address 2 in which the code is stored and store the fault code corresponding to the fault that occurred this time in this memory address 2.

For example, as shown in FIGS. 7A to 7E, n =
In the case of the fault code memory 1 having three memory addresses 2 from 0 to n = 2, first, as shown in FIG.
The failure code “$ 11” corresponding to the component at the failure code address 2 is stored, and then the failure code “$ 12” is stored in the memory address 2 of n = 1 as shown in (B).
Then, as shown in (C), the failure code “$ 13” is stored in the memory address 2 of n = 2.

When the fault corresponding to the fault code "$ 14" is detected in the state where the fault codes are stored in all the memory addresses 2 as described above, the fault code is first detected as shown in (D). The fault code “$ 14” corresponding to the fault detected this time is stored in the stored memory address of n = 0. Further, when a new fault is detected, the fault code "$" corresponding to the fault detected this time is stored in the memory address 2 of n = 1 in which the fault code is first stored at this point.
15 "is stored.

The fault code stored in the fault code memory as described above is read by a test device connected to the electronic control unit at the time of maintenance, and this test device is provided with a corresponding fault code by means such as a warning light. The failure occurrence is displayed for the stored component, and the repair or replacement of the component is prompted.

[0011]

However, in the conventional fault code storage device, as described above, in order to store the fault code, it is necessary to search the memory address where the fault code is not stored. , If the fault code is stored in all the memory addresses, it is necessary to search the fault code memory in which the fault code is stored first at that time, which requires complicated processing and is already stored. The information may be lost because the memory address of the fault code being processed is overwritten.

Since the above-mentioned processing is performed based on a program stored in a memory such as a read-only memory (hereinafter referred to as "ROM") of a microcomputer, most of the storage capacity of the memory is for the processing. However, the limited storage capacity of the memory could not be efficiently used.

Further, for example, in a vehicle inspection, when the body of a two-wheel drive vehicle is lifted up and the accelerator is stepped on,
In some cases, even if the system itself is normal, it may be determined that there is a failure, such that only the drive wheels rotate and the non-rotating driven wheels are considered to be a failure. If this failure code is stored, the failure code will be displayed when the contents of the failure code memory are confirmed by a test device at a later date, so that good parts may be replaced.

On the other hand, as in the case of the driven wheels described above, it may be considered not to store a fault code that may detect a fault even if the system itself is normal in the fault code memory. To be However, in this case, since the failure code is not stored even when the failure actually occurs, the failure history cannot be accurately grasped.

The present invention has been made in order to solve the problem in the conventional vehicle fault code storage device as described above, and simplifies the process for storing the fault code in the fault code microcomputer. The purpose of this invention is to make effective use of the memory and prevent the non-defective non-defective product from being replaced, while at the same time being able to accurately grasp the failure history.

[0016]

Accordingly, the present invention processes signals input from components such as wheel speed sensors,
An electronic control unit including a microcomputer for detecting the occurrence of a failure, and a failure code memory having a plurality of memory addresses and connected to the microcomputer, wherein the plurality of memory addresses are each a failure of each component. There is a one-to-one correspondence with the failure code that indicates the occurrence,
Provided is a fault code storage device configured to store, when a microcomputer detects a fault, whether or not to permit detection of the fault and display of the fault at a memory address corresponding to the fault code.

Further, in the present invention, it is preferable that the fault code memory has a dedicated memory address for storing a fault code corresponding to the latest fault.

[0018]

Since the fault code storage device of the present invention is configured as described above, when a microcomputer detects a fault of a certain component, a fault code indicating this fault is detected in a plurality of memory addresses of the fault code memory. The memory address of the corresponding address stores whether or not a failure has occurred and whether or not the test device is allowed to display the failure.
The storage process of the fault code is simplified. In addition, even if the occurrence of the failure is detected, if the failure is likely to occur at normal times, the display of the failure code is prohibited to prevent replacement of non-defective products.

If one of the memory addresses is a memory address dedicated to the fault code corresponding to the latest fault, a fault frequently occurring with a high occurrence rate is surely displayed on the test apparatus. .

[0020]

The present invention will now be described in detail with reference to the embodiments shown in the drawings. The fault code storage device according to the embodiment of the present invention shown in FIGS.
In addition, a component of the vehicle control system, that is, the wheel speed sensor 1
2, stop switch 13 and parking switch 14
The signal from is input. Further, the ignition voltage 15 and the alternator voltage 16 are input to the electronic control unit 11.

Further, the electronic control unit 11 includes signals from the drive system components of the antilock control unit, that is, the fail-safe relay 18, the motor 19 and the solenoid 20.
The signal from is input.

The microcomputer 21 of the electronic control unit 11 receives inputs from the components such as the wheel speed sensor 12 based on a control program stored in a read-only memory 22 (hereinafter abbreviated as "ROM"). The signal is processed to output a signal for performing required control such as antilock control to the fail-safe relay 18, the motor 19, the solenoid 20, the warning light 23, and the like.

Further, the microcomputer 21 is
On the basis of the failure detection program stored in the ROM 22, signals generated from the components such as the wheel speed sensor 12 are processed to detect the occurrence of failure. The ROM 22 stores a table in which each constituent element has a one-to-one correspondence with a failure code from "1" to "127", and when the microcomputer 21 detects a failure of a certain constituent element, it responds to it. One failure code is set. Further, the microcomputer 21 uses the random access memory 2 used when the failure detection program and the control program are operated.
4 (hereinafter, abbreviated as “RAM”).

In the electronic control unit 11, a fault code memory 25 connected to the microcomputer 21 is provided.

As shown in detail in FIG. 2, the fault code memory 25 has 128 memory addresses 26 from n = 0 to n = 127, each memory address 26 being 8
It consists of bits.

Of the 128 memory addresses 26, the memory addresses 26 from n = 1 to n = 127
Corresponds to the fault code having the same numerical value as the address, one to one. For example, the wheel speed sensor 12 for the left and right rear wheels
Assuming that the failure code of the failure that occurs in "15", "16", the failure code memory 25 at the memory address 26 of n = 15, n = 16, the failure that occurred in the wheel speed sensor 12 of the left and right rear wheels, respectively. Data is stored.

As shown in FIG. 2B, each memory address 26 is composed of 8 bits. Hereinafter, for the sake of explanation, the bits of each memory address 26 are assumed to be p = 0,1,2,3,4,5,6,7 in order from the least significant digit at the right end in the figure.

The bit of p = 7 indicates the presence or absence of failure detection, and is set to "1" when a failure is detected and "0" when no failure is detected.

The bit of p = 6 means that if the bit of p = 7 is "1" indicating the failure detection, the failure detection for the component corresponding to the memory address 26 is actually the component. It indicates that the device itself has not failed and can be detected even when the system is operating normally. That is, in the case of a failure that can be detected even during normal operation, the test device 29, which will be described later, is prohibited from displaying a failure code by "1". On the other hand, it is set to “0” which allows the display of the failure code. For example, as shown in (B), the wheel speed sensor 12 for the left front wheel corresponding to the memory address 26 of n = 15 can be detected as a failure even when the vehicle body is lifted up. 1
When the p = 7 bit of 5 is set to "1", the p = 6 bit is set to "1".

The bits of p = 5 and p = 4 correspond to the above p = 7.
And p = 6 bit complements. For example, as shown in (B), when the bits of p = 7 and p = 6 are "1" and "1", the complement "1" and "1" are input. This p =
The bits 5 and p = 4 are for finding out whether or not the memory address 26 has a failure, and when the failure code is displayed by the test apparatus 29, the above p = 6, p = 7.
It is possible to confirm that these bits are normal by adding all the bits of p = 7 to p = 4 to “0” when added to the numerical value of.

Further, fixed data "1010" is input to the bits of p = 3, 2, 1, 0. The bits from p = 3 to p = 0, like the bits from p = 5 and p = 4, are also used to confirm whether the memory address 26 is operating normally.

At the memory address 26 of n = 0, the fault code of the latest fault is stored. That is, when a new fault is detected, the fault code corresponding to the component having the fault is overwritten and stored in the memory address 26 of n = 0.

In this embodiment, each memory address (not shown) of the RAM 24 is also composed of 8 bits from p '= 0 to p' = 7.

The test device 29 is connected to the microcomputer 22 at the time of maintenance, and confirms the data stored in the failure code memory 25 via the microcomputer 22 and a warning lamp 30 constituting a display means.
The failure code is displayed according to the number of times of flashing.

Next, the operational features of the above embodiment will be described. First, based on FIG. 3, a process of storing a failure code when the microcomputer 22 detects a failure of a certain component will be described. In step # 11, R
Each bit of AM24 is set to "0". Next, in step # 12, it is judged whether or not the detected failure may occur even when the system is normal, and if there is a possibility,
In step # 13, the bit of p '= 6 of RAM 24 is set to "1".
Set to. Next, in step # 14, the bit of p '= 7 of the RAM 24 is set to "1".

In step # 15, p '= in the RAM 24
For bits 5 and p ′ = 4, p ′ = 7 and p ′ =
Set the 6's complement. In step # 16,
Set the bits in the RAM 24 from p '= 3 to p' = 0 to "101".
0 ". In step # 17, in each bit of p = 0 to p = 7 of the memory address 26 of the fault code memory 25 having the same numerical value as the fault code of the detected fault,
The data of "0" or "1" input to each bit of p '= 0 to p' = 7 of the RAM 24 is stored.

Further, in step # 18, the fault code corresponding to the fault detected this time is stored in the fault code memory 25.
In memory address 26 of n = 0.

As described above, in this embodiment, since the memory address 26 of the fault code memory 25 corresponds to each fault code one-to-one, in order to store the fault code, the data in the fault code memory is not stored. It is not necessary to perform the process of searching the memory address of the storage and the process of searching the memory address where the data was stored first when all the memory addresses are full, and the storage process of the failure code can be simplified. .

Next, as described above, the fault code memory 25
A process of reading the data stored therein by the test device 29 connected to the microcomputer 21 and displaying the failure code will be described with reference to FIG. First, step #
At 21, the RAM 24 is set to "0". Step # 2
2, the memory address 26 of the same numerical value as the value set in the RAM 24, that is, the memory address 26 of n = 0
The fault code stored in is read. In step # 23, it is checked whether or not the value of the RAM 24 is "0". If the value of the RAM 24 is "0" as described above, the value of the RAM 24 is used as the failure code in the test device 24 in step # 24.
This is indicated by the warning light 29. As described above, in the present embodiment, the failure corresponding to the failure code stored at n = 0, that is, the latest detected failure can be surely displayed at the beginning of displaying the failure code. As above, n =
After displaying the failure code of the memory address 26 of 0, 1 is added to the value "0" of the RAM 24 in step # 25 to set it to "1", and the process returns to step # 22.

When the value of the RAM 24 is "1", the memory address 26 of the value indicated by the RAM in step # 22, that is, the data of the memory address 26 of n = 1 is read in the same manner as in the above case. , Step # 23 to Step # 26 and Step # 27.

In steps # 26 and # 27,
The p = 7 and p = 6 of the read memory address 26 are checked, and if p = 7 is “1” and p = 6 is “0”, it is the same as the number of the memory address 26 previously. A failure corresponding to the failure code of the number is detected, and the failure is unlikely to occur if the system is normal, so the failure code is displayed in step # 24.

On the other hand, if p = 7 is "0" in step # 26, it means that the failure corresponding to the failure code has not been detected previously, so the failure code is not displayed. Further, in step # 27, even if p = 7 is “1”, if p = 6 is “1”, the failure corresponding to the failure code may occur even when the system is normal. Therefore, the failure code is not displayed. That is, in this embodiment, the test device does not display a failure code corresponding to a failure that may be detected during normal operation of the system, such as a wheel speed sensor for a driven wheel. Therefore, replacement of non-defective products can be prevented.

In this embodiment, as shown in step # 28, the processing from step # 22 to step # 25 is performed by R.
Repeat until the value of AM24 becomes 127.

In the confirmation of the contents of the fault code memory 25 by the test device 29, the fault codes corresponding to the faults that may be detected even if the system is operating normally are not displayed. By directly reading the data of the memory address 26, the test apparatus 2
Even if 9 does not display the failure code, if the failure is detected even once, it is possible to know the failure occurrence,
Accurately understand the failure history.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, in the above embodiment, the data is stored in the memory address having the same number as the failure code, but when the failure codes are not continuous, the memory address number corresponding to each failure code is defined in advance. A table or the like may be stored in a microcomputer, and when a failure occurs, the memory address for storing data may be determined by referring to the table. Further, in the present embodiment, the failure code memory is provided inside the electronic control device, but the failure code memory may be provided outside the electronic control device as long as it is connected to the microcomputer.

[0046]

As is apparent from the above description, in the fault code storage device according to the present invention, when a computer detects a fault in a component, a fault code memory that corresponds one-to-one with a fault code indicating the fault is stored. Memory address,
Since the configuration is such that the occurrence of a failure is detected, it is not necessary to search for an unstored memory address, and the storage processing of the failure code can be simplified. Therefore, the program for the storage processing in the memory of the microcomputer is It is possible to reduce the capacity occupied by and to effectively utilize the memory of the microcomputer having a limited storage capacity.

Further, since the memory address of the memory code memory is configured to store whether or not the display of the failure code is permitted, even if the system itself is normal, such as the wheel speed sensor of the driven wheel, there is a failure. For items that may be detected, it is possible to prevent non-defective product replacement by prohibiting the display of the failure code. On the other hand, even when the display of the failure code is prohibited as described above, the failure code itself is stored in the failure code memory, so by directly reading the contents of the memory address,
The failure history can be accurately grasped.

Further, according to the present invention, by providing a dedicated memory address for storing a fault code corresponding to the latest fault, there are various advantages such as being able to know a fault that frequently occurs.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an embodiment of the present invention.

FIG. 2A is a schematic diagram showing a fault code memory, and FIG.
FIG. 4 is a schematic diagram showing memory addresses.

FIG. 3 is a flowchart showing a fault code storage process.

FIG. 4 is a flowchart showing a failure code display process.

FIG. 5 is a schematic diagram showing a conventional fault code memory.

FIG. 6 is a flowchart showing a conventional fault code storage process.

FIG. 7 is a schematic diagram showing a special process in a conventional storage process.

[Explanation of symbols]

 11 Electronic Control Device 12 Wheel Speed Sensor 21 Microcomputer 22 ROM 24 RAM 25 Fault Code Memory 26 Memory Address 29 Testing Device 30 Warning Means

Claims (2)

[Claims] 1. An electronic control device comprising a microcomputer for processing a signal input from a component such as a wheel speed sensor to detect the occurrence of a failure, and having a plurality of memory addresses, connected to the microcomputer. And a plurality of memory addresses, each of which has a one-to-one correspondence with a failure code indicating the occurrence of a failure of each component, and when the microcomputer detects a failure, the plurality of memory addresses correspond to the failure code. A fault code storage device configured to store, in a memory address, whether detection of a fault and display of the fault are permitted. 2. The apparatus according to claim 1, wherein the fault code memory has a dedicated memory address for storing a fault code corresponding to a latest fault.