JPH06266375A - Noise reducing device - Google Patents

Abstract

PURPOSE:To specify only an engine sound, to improve the efficiency of sound elimination, and to place the noise reducing device in stable operation even when the duty of the ignition pulse signal is varied. CONSTITUTION:The noise reducing device is equipped with a pulse converting circuit PTC which generates a 50% duty pulse wave having the same frequency as the frequency of the ignition pulse signal of an engine, a phased lock loop PLL which generates clock pulses CL by multiplying the frequency of the pulse wave outputted by the pulse converting circuit, a 1st frequency selecting means SCF1 which extracts only a frequency range specified by the clock pulses CL from a sound detected by a noise detection microphone M1, an adaptive digital filter ADF which makes a speaker sound by adaptively controling the signal passed through the 1st frequency selecting means SCF1, and an error detection microphone M2 which detects a sound in a cabin and feeds it back to the adaptive digital filter ADF.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reducing device for reducing noise by adding anti-phase noise to noise.
It can be applied to reduce noise in passenger cars, buses, ships, cabins of passenger cars, airplanes, etc.

[0002]

2. Description of the Related Art As a method for reducing noise by adding anti-phase noise to noise, it is generally disclosed in Japanese Patent Laid-Open No. 20435/1993.
There is an adaptive control system as disclosed in Japanese Patent Publication No. The adaptive digital filter (Adaptive Digital Filter) ADF used in the adaptive control system includes a transversal filter 35 and an adaptive algorithm 36, as shown in FIG. 7. The adaptive algorithm 36 refers to the sound on the main input side and sets the filter coefficient of the transversal filter 35 so as to create an antiphase sound of the sound on the main input side. The transversal filter 35 performs a convolution operation on the reference input, and emits a sound from the speaker SP. The signal VB detected from the error detection microphone M2 is sent to the reference input of the adaptive digital filter ADF.

FIG. 8 shows an adaptive digital filter A.
One structure using DF is shown. The noise detection microphone M1 detects noise. The error detection microphone detects the sound in the room. The adaptive digital filter ADF sets a filter coefficient so as to reduce the level of sound in the room, and emits an antiphase sound of noise from the speaker SP. As a result, the human ears in the room can hear the synthesized sound of the noise and the antiphase noise of the noise,
The noise is offset and muted.

When mounted on a vehicle, it is usually necessary to muffle the engine sound, but there is a method of estimating the noise by detecting the engine speed instead of the noise detecting microphone M1. FIG. 9 shows a method of estimating noise from the engine speed. The engine rotation sensor PP detects the rotation speed of the engine 12. The adaptive digital filter ADF performs a product-sum operation on the engine rotation detection signal with a predetermined filter coefficient to generate a sound from the speaker SP. On the other hand, the signal VB detected by the error detection microphone M2 is sent to the adaptive digital filter ADF. The adaptive digital filter ADF finds the optimum filter coefficient from the signal VB and changes the filter coefficient.

[0005]

SUMMARY OF THE INVENTION In the above technology,
The engine speed is detected and the noise from the engine is estimated from the engine speed. The actual engine sound transmitted to the passenger compartment is not determined only by the engine speed, but changes depending on the state change in the engine compartment, the resonance state in the passenger compartment, the humidity and the temperature change. Therefore, when the noise is specified only from the engine speed, the waveform of the actual noise and the waveform of the predicted noise signal may deviate from each other, and the noise may not be sufficiently suppressed.

On the other hand, when the noise detecting microphone is used, if the sound other than the engine enters the noise detecting microphone and the level of the sound other than the engine is higher than the engine sound, the adaptive control does not work well, May diverge.

Therefore, it is an object of the present invention to identify the noise to be input to the adaptive digital filter from among the sounds that are actually generated to improve the silencing efficiency.

[0008]

In order to solve the above-mentioned problems, the first means used in the invention of claim 1 is a noise detection microphone for detecting a sound generated by an engine, and a signal of an ignition pulse of the engine. A pulse conversion circuit that generates a pulse wave of 50% duty with the same frequency as the frequency;
A phased lock loop that generates a clock pulse by multiplying the frequency of the pulse wave output by the pulse conversion circuit,
First frequency selection means for receiving only outputs of the noise detection microphone and the phased lock loop and extracting only a frequency range designated by a clock pulse from sounds detected by the noise detection microphone, and the first frequency selection means An adaptive digital filter that adaptively controls the signal that has passed through, a speaker that generates sound in the room based on the output signal of the adaptive digital filter, and an error detection microphone that detects the sound in the room and feeds back to the adaptive digital filter. Be prepared.

In order to solve the above-mentioned problems, the second means used in the invention of claim 2 uses a noise detection microphone for detecting the sound generated by the engine, and a frequency equal to the frequency of the signal of the ignition pulse of the engine. A pulse conversion circuit that generates a pulse wave with a duty of 50%, a phased lock loop that generates a clock pulse by multiplying the frequency of the pulse wave output by the pulse conversion circuit, and an output of the noise detection microphone and the phased lock loop. A first frequency selecting unit that extracts only a frequency range designated by a clock pulse from the sound detected by the noise detecting microphone; and an adaptive digital filter that adaptively controls a signal that has passed through the first frequency selecting unit. , Generate sound in the room based on the output signal of the adaptive digital filter Receives the output of the speaker, the error detection microphone that detects the sound in the room, the error detection microphone and the phased lock loop, and extracts only the frequency range specified by the clock pulse from the signals detected by the error detection microphone. Second frequency selecting means for feeding back to the adaptive digital filter.

[0010]

According to the above-mentioned first means, of the engine sounds detected by the noise detecting microphone, only the sounds in the frequency range of the engine rotation frequency and its harmonic components pass through the first frequency selecting means. As a result, only the noise actually generated by the engine can be extracted. The adaptive digital filter sets the filter coefficient by feedback from the error detection microphone so that the detection sound of the error detection microphone is minimized, convolves the sound passing through the first frequency selecting means, and calculates the error detection microphone from the speaker. It works to generate the opposite phase sound of the detected sound. The frequency band of sound emitted from the speaker, that is, the frequency band of silenced sound is limited to only the frequency band of noise actually generated by the engine. Therefore, an antiphase sound in the noise frequency band is generated from the speaker, and among the sounds in the room, the sound actually generated by the engine is silenced.

According to the first means, when listening to music indoors or outdoors, the sound of the siren of a police car or the like, the warning at a railroad crossing, the sound of an approaching car, etc. are excluded from the silence. Therefore, the necessary sound is not muted. Moreover, since the noise that is actually generated is detected, it is possible to effectively muffle the noise.

According to the second means, among the engine sounds detected by the noise detecting microphone, only the sound in the frequency range of the engine rotation frequency and its harmonic components passes through the first frequency selecting means. As a result, only the noise actually generated by the engine can be extracted. The adaptive digital filter sets the filter coefficient by feedback from the error detection microphone so that the detection sound from the error detection microphone that has passed through the second frequency selection means is minimized, and outputs the sound that has passed through the first frequency selection means. The convolution operation is performed, and it works so as to generate the antiphase sound of the sound detected by the error detection microphone from the speaker. Also in the feedback from the error detection microphone, only the frequency band of the noise actually generated by the engine is extracted by the second frequency selecting means, so that the optimum antiphase sound is obtained in the noise frequency band. Therefore, the level of sound other than the noise generated by the engine is not reduced. Even if a sound with a frequency extremely close to the frequency band of the noise emitted by the engine is emitted from other than the engine, only the noise from the engine can be selected and silenced.

In the above-mentioned first and second means, a pulse conversion circuit sends a pulse wave of 50% duty having the same frequency as the frequency of the signal of the ignition pulse of the engine to the phased lock loop. Phased lock loop is mainly composed of phase comparator, loop filter,
It is composed of a voltage controlled oscillator. The phase comparator detects the phase difference between the input signal and the signal from the voltage controlled oscillator,
The error is output as a voltage. The loop filter is
The high frequency component of the error signal is cut. The voltage controlled oscillator adjusts the phase in an attempt to reduce the error signal to zero and oscillates a frequency corresponding to the phase. This oscillation signal is a pulse with a duty of 50%. When the duty of the input signal of the phase comparator is 50%, the phase difference between the signal input to the phase comparator and the output signal of the voltage controlled oscillator is simple, and the voltage controlled oscillator reduces the phase difference. It just works. However, if the duty of the input signal of the phase comparator is not 50%, the phase difference between the signal input to the phase comparator and the output signal of the voltage controlled oscillator will not be simple, and the operation of the voltage controlled oscillator will be complicated, resulting in a phase difference. The voltage commensurate with will increase or decrease and will be disturbed. As a result, the oscillation frequency of the voltage controlled oscillator also fluctuates significantly. When the first frequency selecting means inputs the pulse having the large fluctuation as the clock pulse, it becomes impossible to pass the desired frequency. Therefore, it is desirable that the duty of the output pulse of the pulse conversion circuit is 50%. In the above means, the pulse conversion circuit generates a pulse wave of 50% duty having the same frequency as the signal of the ignition pulse signal of the engine and uses it as the input of the loop filter, so that the first frequency selecting means is stable. And work.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is mounted on a vehicle will be described below with reference to the drawings.

FIG. 1 is an overall schematic view of the present invention. The speaker SP and the error detection microphone M2 are arranged to extend from the headrest 11 of the seat 10 to the ears. The speaker SP and the error detection microphone M2 may be arranged so as to extend from the backrest portion 14 of the seat 10. Noise detection microphone M1
Are installed in symmetrical positions with respect to the error detection microphone M2 so that the sound pressures of noises in the respective vehicle compartments become equal.
The engine 12 operates by receiving the ignition pulse signal E. The pulse conversion circuit PTC receives the ignition pulse signal E of the engine 12 and outputs a pulse signal ET. Pulse signal E
T is a pulse signal having the same frequency as the ignition pulse signal E and a duty of 50%. The pulse signal ET is input to a phased lock loop PLL. The phased lock loop PLL generates the clock pulse CL. The clock pulse CL is the pulse signal E
It is a pulse signal having a frequency of a predetermined multiple of T. The clock pulse CL is given to the first frequency selector SCF1 and the second frequency selector SCF2. First frequency selector S
CF1 receives the reference signal VA from the noise detection microphone M1 and outputs the reference signal PA. Second frequency selector SCF
2 receives the error signal VB from the error detection microphone M2 and outputs the error signal PD. The first frequency selector SCF1 and the second frequency selector SCF2 work to pass only the frequency band designated by the clock pulse CL.
An adaptive digital filter ADF, which is an adaptive filter, receives the reference signal PA and the error signal PD and outputs a muffling signal PB. The adaptive digital filter ADF adjusts the phase and gain of the reference signal PA so that the error signal PD, which is a feedback signal, is minimized, and outputs the silence signal PB. The mute signal is output as sound in the speaker SP.

Here, the configuration of the pulse conversion circuit PTC will be described with reference to FIG. The external clock output of the external clock generation circuit 20 for generating an external clock of 10 KHz is connected to the clock terminal of the binary counter 21 and the clock down terminal of the up / down counter 24. Here, SPG8 is used as the external clock generation circuit 20.
640B is used. In addition, the binary counter 21
Is a dual 4-bit 74HC393, and the up / down counter 24 is a 74HC193. Ignition pulse signal E is NOT gate, resistor, capacitor, N
It is input to the short pulse conversion circuit 23 configured by an AND gate. The load signal output from the short pulse signal conversion circuit 23 is further inverted and delayed by the delay circuit 22, and then the binary counter 21 is used as a reset signal.
Sent to. Here, the delay circuit 22 is a DCE 35-
I am using 20. The 2nd to 8th bits (Q2 to 8) of the output of the binary counter 21 are the up / down counter 2
Bits 1 to 7 of the input of 4, 25 (P0 of up-down counter 24, P0 of up-down counter 25
2) is connected. Up-down counter 24,2
The outputs 5 (Q0 to Q3 of the up / down counter 24 and Q0 to 2 of the up / down counter 25) are inverted by the NOT gates and input to the NAND gate 26. The load signal and the output of the NAND gate 26 are inverted by a NOT gate and input to the OR gate 27. The output of the OR gate 27 is used as the JK flip-flop 2
Input to 8 clock terminal.

Next, the operation of the pulse conversion circuit PTC will be described with reference to FIG. First, the external clock generation circuit 20 generates an external clock of 10 KHz. The external clock is used as a clock for the binary counter 21 and the up / down counter 24. The short pulse conversion circuit 23 converts the input ignition pulse signal E into a load signal. Here, the ignition pulse signal E is inverted, delayed by a delay circuit using a resistor and a capacitor, and the delayed signal and the ignition pulse signal are ANDed. As a result, the output of the short pulse conversion circuit 23 is the ignition pulse signal E.
From the rising edge of, the level becomes low only for a predetermined time determined by the resistor and the capacitor. The load signal output from the short pulse signal conversion circuit 23 is further inverted, delayed by the delay circuit 22, and then sent to the binary counter 21 as a reset signal.

The binary counter 21 is reset by a reset signal and counts up at the rising edge of the external clock. The load signal is input to the up / down counters 24 and 25 at the rising edge of the ignition pulse, and the input value at that time is set.

After that, the countdown is performed every time the external clock is input. Due to the influence of the delay circuit 22, the binary counter 21 is reset after the up / down counters 24 and 25 set the input values, and starts counting up again. 2-8 of the output of the binary counter 21
Bits (Q2-8) are up / down counters 24, 2
5th to 1st to 7th bits of input (up / down counter 24
P0-3 and P0-2 of the up / down counter 25), a half of the count value of the binary counter 21 is set at the time of loading. By doing so, the count value becomes zero in half of the cycle of the ignition pulse, and the load signal, the outputs Q0 to 3 of the up / down counter 24 and the output Q of the up / down counter 25.
A state where 0 to 2 all become low level appears. When the outputs of the up / down counters 24 and 25 are respectively inverted and input to the NAND gate 26, when the outputs of the up / down counters 24 and 25 are all at the low level, NA
A low level output is obtained from the ND gate 26. Invert the load signal and the output of the NAND gate 26,
When input to the OR gate 27, the output of the OR gate 27 generates a short pulse that goes high every half cycle of the ignition pulse. When the output of the OR gate 27 is input to the clock terminal of the JK flip-flop 28, the OR gate 2
The pulse signal ET having a duty of 50% can be output by using the high level signal of No. 7 as a trigger.

The internal structure of the phased lock loop PLL is shown in FIG. The phased lock loop PLL includes a phase comparator 31, a loop filter 32, a voltage controlled oscillator 33.
And a frequency divider 34. The phase comparator 31 outputs a phase error between the duty-converted ignition pulse signal ET and the output of the frequency divider 34 to the loop filter 32 as a signal. The loop filter 22 has an integrator configuration,
The phase error signal is sent to the voltage controlled oscillator 33 in the form of analog voltage. The voltage controlled oscillator 33 oscillates a frequency pulse according to the input voltage, outputs it as a clock pulse CL, and sends it to the phase comparator 31. Clock pulse C
L is set to be N times the frequency of the ignition pulse signal ET. The value of N is set in advance. The frequency divider 34 frequency-divides the clock pulse CL and outputs a frequency-divided signal to the phase comparator 31. The frequency divider 34 is set so that the frequency of the clock pulse CL is 1 / N.

Now, it is assumed that N times the frequency of the ignition pulse signal E matches the frequency of the clock pulse CL. Here, when the engine speed increases, a phase difference occurs between the pulse from the frequency divider 23 and the ignition pulse signal ET. At this time, the phase comparator 31 outputs a signal according to this phase difference. The output pulse voltage is increased when the phase is increased, and the output pulse voltage is decreased when the phase difference is decreased. The loop filter 32 converts the output pulse into an analog voltage, and the voltage controlled oscillator 33 generates a clock pulse having a frequency corresponding to this analog voltage. Therefore, when the phase difference increases, the clock frequency increases, and when the phase difference decreases, the clock frequency decreases. Therefore, the clock frequency fluctuates depending on the engine speed. Since the loop filter 32 has the configuration of an integrator, even if the phase difference matches and the pulse from the charge pump is no longer output, the loop filter 32 continues to output the value up to that point.
Therefore, the frequency of the clock pulse CL is N times the engine speed.

The first frequency selector SCF1 is a switched capacitor filter SC.
It is composed of F. The switched capacitor filter SCF is an integrator that applies the property of a switched capacitor in which the equivalent resistance Req is 1 / (C · fc). When designing the filter, if this Req is a resistor,
It is possible to realize a filter that follows changes in fc. As the switched capacitor filter SCF, there is an MF10 universal monolithic dual switched capacitor filter manufactured by National Semiconductor. By using this MF10, it is possible to form a bandpass filter that extracts only the frequency band corresponding to the frequency fc of the clock pulse CK.

A clock pulse having a frequency N times the frequency of the engine speed is a switched capacitor filter S.
Switched capacitor filter SCF given to CF
Adjusts the frequency band to be selected according to the frequency of the clock pulse CL. By adjusting this value N and the voltage range of the voltage controlled oscillator 33, it is possible to obtain a bandpass filter capable of extracting only the frequency of a predetermined multiple of the engine speed. As a result, only the nth harmonic component of the engine speed can be extracted from the vehicle interior sound detected by the noise detection microphone M1. Usually, in a 4-cylinder engine, the level of the second harmonic component of the engine speed is high, which causes noise in the vehicle interior.
It is advisable to adjust the value N and the voltage range of the voltage controlled oscillator 33 to select the frequency per twice the engine speed.

The sound generated by the speaker enters the ears of the driver and passengers together with the sound coming from the engine, which is a noise source, and the inside and outside of the vehicle. At the same time, these sounds are detected by the error detection microphone M2. The output VB of the error detection microphone M2 is sent to the adaptive digital filter ADF. The adaptive digital filter ADF, as shown in FIG.
Transversal filter 35 and adaptive algorithm 3
6 is provided. The adaptive algorithm 36 is an error detection microphone M
The output VB of 2 is received, and the transversal filter 35 is received.
Determine the filter coefficient of. The transversal filter 35 performs a convolution operation on the signal PA from the first frequency selector SCF1 and sends a signal sound PB to the speaker SP. As a result, the adaptive digital filter ADF minimizes the level of the detection sound of the error detection microphone M2.
Adjust the filter coefficient.

A second frequency selecting means, which is a second frequency selecting means, is provided between the error detecting microphone M2 and the adaptive digital filter ADF.
The frequency selector SCF2 is inserted.

The sound generated by the speaker enters the ears of the driver and passengers together with the sound coming from the engine, which is a noise source, and the inside and outside of the vehicle. At the same time, these sounds are detected by the error detection microphone M2. The output VB of the error detection microphone M2 is frequency-selected by the second frequency selector SCF2, which is the second frequency selection means, and is sent to the adaptive digital filter ADF as the signal PD. Second frequency selector SCF2
Has the same configuration as the first frequency selector SCF1,
Output clock CL from phased lock loop PLL
Thus, only the signal in the frequency band corresponding to the nth harmonic component of the engine speed is extracted.

By inserting a bandpass filter that follows only the frequency range of noise on the error detection microphone M2 side as well, only noise can be reliably silenced.

In the above embodiment, since the actual noise is detected and the control is performed by separating only the frequency band of the noise, the noise can be surely silenced, and the convergence speed of the adaptive digital filter ADF is increased. Is improved. Therefore, the effectiveness of the adaptive digital filter ADF increases.

In the case of a 6-cylinder engine, the engine rotation first order component, 1.5th order component, second order component, 2.5th order component and third order component appear in the noise distribution in the passenger compartment.
When it is desired to mute all of these components, a plurality of frequency selectors may be provided, and each component may be extracted, then synthesized, and given to the adaptive digital filter ADF.

As described above, only noise is silenced, and necessary sounds such as music, voice, alarm, and warning sound are not silenced, so that it can be mounted on a car. Further, by detecting the actually generated noise with the microphone, the noise can be surely silenced.

In the above embodiment, the device for reducing the noise of the engine in the vehicle is shown, but the present invention is not limited to the engine, but can be applied to a device in which the frequency of the noise portion changes according to the state of the noise source. . For example, a number of applications are conceivable, such as reducing the engine sound in the cabin of an airplane, or reducing the noise generated by a device such as a medical treatment placed on the bedside of a patient, which is adopted in the bed of a patient. In this case, the noise of an arbitrary frequency band may be reduced by adjusting the clock of the switched capacitor filter. For vehicles, it is also effective in reducing the operating noise of the seat adjuster, the sliding noise of the wiper, the noise generated by the transmission during a shift change, the operating noise of the solenoid valve mounted on the vehicle, and the like.

Since the speaker SP and the error detection microphone M2 are arranged near the human ear, the speaker SP does not need to make a loud sound. Therefore, the sound emitted from the speaker SP does not affect the part away from the seat 10 or the outside of the vehicle, and the sound is not emphasized in other parts. Therefore, it reliably reduces only the noise coming into the ears of the person sitting in the seat and does not affect others.

When the present invention is mounted on a vehicle, the noise reduction device of the present invention can be mounted on each seat. In this case, it is advisable to provide a switch for permitting / prohibiting the operation of this device so that the individual seats can be switched. For example, the device can be operated for a person sleeping in the back seat, and the driver can turn off the device to check the engine sound or prevent drowsiness. Will be possible.

In the above embodiment, the pulsed lock loop PLL is supplied with the pulse wave ET of 50% duty having the same frequency as the frequency of the ignition pulse signal E of the engine by the pulse conversion circuit PTC. When the duty of the input signal of the phase comparator 31 of the phased lock loop PLL is 50%, the phase difference between the signal input to the phase comparator 31 and the output signal of the voltage controlled oscillator 33 is simple, and the voltage controlled oscillator 33 Operates simply to reduce this phase difference. However, when the duty of the input signal of the phase comparator 31 is not 50%, the phase difference between the signal input to the phase comparator 31 and the output signal of the voltage controlled oscillator 33 becomes unsimple, and the operation of the voltage controlled oscillator 33 is complicated. Then, the voltage commensurate with the phase difference will increase or decrease and will be disturbed. As a result, the oscillation frequency of the voltage controlled oscillator 33 also fluctuates significantly. When the first frequency selector SCF1 inputs this pulse with a large fluctuation as a clock pulse, it becomes impossible to pass a desired frequency. Therefore, the duty of the output pulse of the pulse conversion circuit PTC is preferably 50%. In the present embodiment, the pulse conversion circuit PTC generates a pulse wave ET of 50% duty having the same frequency as the ignition pulse signal E of the engine, and the loop filter P
Since the input is LL, the first frequency selector operates stably.

[0035]

According to the present invention, the user does not want to erase all sounds heard by the user, but only the sound of a specific frequency emitted from the noise source is reduced. It doesn't erase even.

Moreover, since the noise that is actually generated is detected, the noise reduction effect is excellent.

Even when the adaptive digital filter is used, the convergence speed and the volume of noise are excellent.

Furthermore, since a pulse wave of 50% duty having the same frequency as the ignition pulse signal of the engine is generated and used as the input of the loop filter, the first
The frequency selection means operates stably. Therefore, it is not necessary to care about the duty of the ignition pulse signal of the engine.
Further, even if the duty of the ignition pulse signal of the engine changes according to the change of the engine speed, the silencing operation is accurately performed.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of one embodiment of the pulse conversion circuit of FIG.

3 is a time chart of the pulse conversion circuit of FIG.

FIG. 4 is a block diagram of the phased lock loop of FIG.

FIG. 5 is a time chart of a phased lock loop when the present invention is used.

FIG. 6 is a time chart of a conventional phased lock loop.

FIG. 7 is a block diagram of an adaptive digital filter.

FIG. 8 is a configuration diagram of a noise reduction device using a conventional adaptive control method.

FIG. 9 is a configuration diagram of a noise reduction device using a conventional adaptive control method.

[Explanation of symbols]

10 Seat 11 Headrest 12 Engine 14 Backrest 20 External clock generation circuit 21 Binary counter 22 Delay circuit 23 Short pulse conversion circuit 24, 25 Up-down counter 26 NAND gate 27 OR gate 28 JK flip-flop 31 Phase comparator 32 Loop filter 33 voltage controlled oscillator 34 frequency divider 35 transversal filter 36 adaptive algorithm CL clock pulse E ignition pulse signal ET pulse signal PA reference signal PB mute signal PD error signal PLL phased lock loop PTC pulse conversion circuit M1 noise detection microphone M2 error detection microphone SCF Switched Capacitor Filter SCF1 First Frequency Selector (First Frequency Selector) SCF2 Second Frequency Selector (Second Frequency Selector) SP speaker VA reference signal VB error signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03H 17/02 G 7037-5J 21/00 7037-5J

Claims (2)

[Claims] 1. A noise detection microphone for detecting a sound generated by an engine, a pulse conversion circuit for generating a pulse wave of 50% duty having a frequency equal to the frequency of an ignition pulse signal of the engine, and a pulse conversion circuit for output. A phased lock loop that generates a clock pulse by multiplying the frequency of a pulse wave, receives the output of the noise detection microphone and the phased lock loop, and of the sound detected by the noise detection microphone, only the frequency range specified by the clock pulse A first frequency selecting means for extracting a signal, an adaptive digital filter for adaptively controlling the signal that has passed through the first frequency selecting means, a speaker that generates sound in the room based on the output signal of the adaptive digital filter, and a sound for detecting the room. , Feed to the adaptive digital filter A noise reduction device that includes an error detection microphone that moves back. 2. A noise detection microphone for detecting a sound generated by an engine, a pulse conversion circuit for generating a pulse wave with a duty of 50% having the same frequency as a signal of an ignition pulse signal of the engine, and an output of the pulse conversion circuit. A phased lock loop that generates a clock pulse by multiplying the frequency of a pulse wave, receives the output of the noise detection microphone and the phased lock loop, and of the sound detected by the noise detection microphone, only the frequency range specified by the clock pulse A first frequency selecting means for extracting a signal, an adaptive digital filter for adaptively controlling a signal that has passed through the first frequency selecting means, a speaker for generating a sound in a room based on an output signal of the adaptive digital filter, and a sound for detecting a room. Error detection microphone, the error detection microphone and Noise reduction including a second frequency selecting unit that receives the output of the locked lock loop, extracts only the frequency range designated by the clock pulse from the signal detected by the error detection microphone, and feeds back to the adaptive digital filter. apparatus.