JPH06261383A - Method for discriminating line fault - Google Patents

Abstract

PURPOSE:To monitor the presence or absence of error in a connection route. CONSTITUTION:A time slot TS includes the 1st to 3rd count code sections CC1-CC3. The time slot TS successively counting up the 1st to 3rd count code sections CC1-CC3 from '000' is sent to the line in succession. At the reception side, the 1st to 3rd count code sections in the time slot TS and the count value in the system are compared to discriminate the presence or absence of error generation in the time slot TS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line fault identification method, and more particularly to a line fault identification method for improving the line quality in a basic speed interface or a primary rate interface.

[0002]

2. Description of the Related Art In recent years, ISDN (high-speed digital communication network)
Due to the spread of, various data communication using high-speed digital lines is widely used. ISDN, which is generally available in Japan at present, such as INS Net 64, has 6
It is possible to use two B channels, which are information channels capable of transmitting code, voice, audio, video, etc., by a circuit switching system at 4 kbit / sec (64 kbps). This B
The channels enable so-called multimedia digital communication for transmitting various information such as audio signals and video signals.

In this kind of ISDN, a basic speed interface having a speed of 64 kbps or 128 kbps, and a primary group interface (Nx192 kb)
In the circuit switching service using ps, Nx256 kbps), when a call is originated from the own station, the other station is connected through an arbitrary route.

[0004]

However, in the prior art, communication is performed without identifying the line quality of the route connected as described above, and thus the line quality of the route cannot be examined. , Communication with errors will be forced on a poor quality line. In addition, even when the line is being used, in general, if the fault occurrence period in the network is less than 1 second, for example, it is not possible to receive a fault report from the network. I can't know.

The present invention has been made under such a background, and an object thereof is to provide a line fault identification method capable of reliably monitoring and detecting the presence or absence of an error on a line in a connection path. Especially.

[0006]

According to the line fault identifying method of the present invention, a time slot including a predetermined pattern is transmitted to a line, the pattern is read from the time slot received from the line, and the read pattern is read. It is characterized in that the occurrence of an error in the line is determined by the presence or absence of the error in.

The time slot to be transmitted is
Configured with the bit length of the frame format in the basic speed interface and the primary group speed interface,
Further, it is preferable that the transmission of this time slot is performed when the line is connected or when the transmission line of the line becomes vacant.

[0008]

Function: For example, before the main communication at the time of line connection, the above-mentioned pattern transmission is performed, and the receiving side checks the presence or absence of an error in this pattern to identify the presence or absence of the line failure. You can Therefore, for example, the quality of the line is confirmed before the main communication, and if there is no error, high-quality communication can be performed through the line. On the other hand, if an error is included, another procedure is performed by calling again, taking a different route, and performing the same confirmation for this different route. Can communicate.

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is an explanatory diagram of a line fault identifying method according to an embodiment of the present invention, and illustrates a time slot TS transmitted to the line after the line is connected. This time slot TS is divided into, for example, two time slots as shown in FIG.
Channel and B2 channel.

The time slot TS is a pattern composed of 16 bits in total, and the details thereof are as follows. That is, the 3 bits from bit number 1 to 3 are the first
5 of the count code portion CC1 of bit number 4 to 8 are the cell type identification portion ST and bit number 9 of 1
Bit is error information transmission part ER, bit number 1 of 1
Bits are sequence check part SC, bit numbers 11 to 11
3 bits up to 13th are the second count code part CC
The third count code portion CC3 is assigned to each of the 2 bits and the 3 bits of the bit numbers 14 to 16.

First to third count codes CC1 to CC
For each 3 bits of 3, "0" as illustrated in the lower side of FIG.
Bit patterns composed of logical values corresponding to the numbers 00 "to" 111 "are sequentially set. Therefore, at least the 16 patterns shown in the lower part of FIG. The 16 patterns are sequentially transmitted to monitor whether or not a line failure has occurred when the line is connected.

A 5-bit cell type identification unit ST
Is for identifying the cell type (cell type) of the time slot TS, and these five bits are "0000".
The bit configuration of "0" is set. That is, by setting the cell type identification unit ST to have such a bit configuration, the system recognizes that this time slot TS is for line monitoring (for line fault identification). Error information transmission part ER 1
The bit is used to confirm the presence / absence of an error in the transmission partner, and is set to a logical value "1" when a transmission error occurs and there is a line failure as described later. Further, the sequence check unit SC is used to start the counter in the device as described later.

FIG. 2 illustrates a system to which the line fault identification method of the present invention is applied. This system has a transmission unit and a reception unit, and the transmission unit includes a data terminal device interface 1 and data buffers 21-2.
n, cell assemblers 31 to 3n, cell buffers 41 to 4
n, cell counters 51 to 5n, and a cell multiplexer 6.

The receiving section includes a cell disassembler 8, a demultiplexer 9, information field disassemblers 101-10n, data buffers 111-11n,
And the data terminal device interface 1. Reference numeral 7 is an interface (basic speed interface, primary group speed interface) I / O.

The data terminal device interface 1
Although only one is shown in the figure, in actuality, similar data terminal equipment interfaces are connected to the respective ports.

The outline of the operation of these components is as follows. First, in the transmitting unit, the data terminal device interface 1 converts a signal from the terminal device into a signal level of the system. The data buffers 21 to 2n temporarily store the level-converted signal data in order to form cells (time slots; the same applies hereinafter) of a predetermined format. The cell assemblers 31 to 3n are connected to the cell buffers 41 to 41n.
As soon as 4n becomes empty, the data is divided into units of a predetermined number of bits, and an address part for designating the destination port address number is added to this to create a cell of a predetermined format. The cell buffers 41 to 4n store the created cells until the transmission order comes. Cell counter 5
The cells 1 to 5n count the number of cells transmitted from the cell buffers 41 to 4n after the transmission permission from the cell multiplexer 6 is down, and transmit the transmission completion to the cell multiplexer 6 when the number of cells to be transmitted is counted. . The cell multiplexer 6 issues the transmission permission to the cell buffers 41 to 4n in order from the port with the highest priority, the transmission of which has not ended. The cells transmitted from the cell multiplexer 6 are interface I / O by, for example, one or both of two B channels (B1, B2) in the case of 64 kbps or three B channels in the primary rate interface (Nx192 kbps). O7
And further transmitted from the interface I / O 7 to the interface network.

Further, in the receiving section, the cell disassembler 8 receives the interface I / O from the interface network.
The cell received via O7 is decomposed into an address part and other data (information field). The demultiplexer 9 distributes the information field to the corresponding user port according to the decomposed address part. The information field disassemblers 101 to 10n decompose the distributed information field into a cell type identification part and other data parts. Data buffers 111 to 11n
Temporarily stores the user data in the decomposed data part for speed conversion. Then, this user data is corrected to each terminal speed, converted into a signal level of each terminal device by the data terminal device interface 1, and transmitted to the terminal.

In the above system, the time slot T of the present invention composed of 16 bits as described above.
As described above, S is recognized by the cell type identification unit for line monitoring (line fault identification).

In FIG. 3, in the system as described above,
An example of the process of reading the pattern from the received time slot TS and the presence or absence of the detected error is shown. Here, the logical value of the bit number 9 of the time slot TS is "
In the case of 1 ", the receiving unit recognizes that a line error has occurred and displays a line error.

On the other hand, the bit number 9 of the time slot TS
If the logical value of No. is "0", the following processing is performed. First, of the TS time slots received by the receiving section, the first count code section CC1 having bit numbers 1 to 3, the second count code section CC2 similarly having 11 to 13 and the 14th to 16th Each 3-bit pattern of the third count code part CC3 of is read in a divided form. Then, the read three 3-bit patterns are sequentially compared in the comparator (3 × 3 bit comparator) 12.

As a result of this comparison, if all three 3-bit patterns are the same, the comparator (2 × 3 bit comparator) 13 determines the count value of the pattern by the cell counter 14 and the 3-bit pattern. Be compared. The cell counter 14 includes three first to first cells in the time slot TS.
If all the bit patterns of the count codes CC1 to CC3 of 3 have the logical value "0" and the sequence check bit of the bit number 10 has the logical value "0", "00"
The count-up is sequentially started from 0 ". When the result of the comparison in the comparator 13 indicates that the 3-bit pattern is different from the count value of the cell counter 14, a counter error is displayed. It is sequentially performed with the reception of 16 time slots TS which are sequentially transmitted as described above.

As described above, the first to third count codes CC which are the three 3-bit patterns of the time slot TS.
If the bit patterns of 1 to CC3 do not match, it is recognized that the line contains an error. In this case, if the own station is the called side, the bit number 9 of the time slot TS transmitted from the transmitting section to the other side is a logical value "
By setting this to 1 ", the other side is notified that there is an error in the line.

If the own station is the calling side, the current line connection is disconnected once, and the calling process is again performed to the called side by the same procedure. The first of the comparators 12 and 13
.About.3 count codes CC1 to CC3 and the count value in the cell counter 14, a total of four 3 bit patterns are compared, and these four 3
If the bit patterns are all the same and the bit number 9 of the time slot TS received by the receiving unit is the logical value "0", it is determined that there is no error on the line, and this communication is performed. Is started.

Furthermore, if the bit patterns of the first to third count codes CC1 to CC3 in the time slot TS match, but if these do not match the 3-bit pattern of the count value in the cell counter 14, then there is a system failure. To be judged. In this case, the currently connected line is connected and the system operator is informed of the system failure by the above counter error display.

On the other hand, on the transmitting side of the system, when the time slot TS for monitoring the line fault is transmitted to the line after the line is connected, as shown in FIG.
Therefore, the bit pattern in the first to third count codes CC1 to CC3 of the time slot TS is "00".
The count-up is sequentially started from 0 ". This count-up starts when the first time slot TS is transmitted after the line connection.

By adopting the configuration of this embodiment,
Since it is possible to monitor the presence / absence of an error on the line in the connection path and to identify the presence / absence of a fault in the system by the counter error display, there is an advantage that the fault isolation when the fault occurs becomes easy.

Although the embodiment in which the time slot is composed of 16 bits has been described above, the bit length of the time slot TS is not limited to this, and the bit length of the frame format in the basic speed interface or the primary group speed interface. It may be composed of, for example, 24 bits or 32 bits according to the above. Further, it is needless to say that the above-described confirmation of the line error by the time slot TS can be appropriately performed not only when the line is connected but also when the transmission line of the line becomes available.

[0029]

As described above, according to the present invention, since it is possible to reliably monitor and identify the presence or absence of an error on a line in a connection path, it is possible to perform error-free main communication and to perform error-free data transmission. There is an effect that becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a cell format of a time slot used in a line fault identifying method according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of a system to which the line fault identification method of the present invention is applied.

FIG. 3 is an explanatory diagram of confirmation processing of presence / absence of an error using a time slot received from a line.

[Explanation of symbols]

 1 Data Terminal Equipment 21-2n Data Buffer 31-3n Cell Assembler 41-4n Cell Buffer 51-5n Cell Counter 6 Cell Multiplexer 7 Interface I / O 8 Cell Disassembler 9 Demultiplexer 101-10n Information Field Disassembler 111-11n Data Buffers 12 and 13 Comparators 14 and 15 Cell counter

Claims (3)

[Claims] 1. A time slot including a predetermined pattern is transmitted to a line, the pattern is read from a time slot received from the line, and the occurrence of an error in the line is determined by the presence or absence of an error in the read pattern. A method for identifying line faults characterized by. 2. The line fault identifying method according to claim 1, wherein the transmitted time slot is configured by a bit length of a frame format in a basic rate interface or a primary rate interface. 3. The line fault identification method according to claim 1, wherein the transmission of the time slot is performed when a line is connected or when a transmission line of the line is vacant.