KR860000498B1 - Telephone system with automatic test call generator for remote port groups - Google Patents

Abstract

Message translation arrangement for telephony system switches calls to remotely located port groups in network and concentrates telephone lines from remote subscriber. Automatic test circuit is provided for remote subscriber line to disconnect through the remote-test-access- relay, and has the interface provided to complete the call processing between the remote subscriber line and automatic test circuit.

Description

Telephone system with automatic test call generator for remote port group

1 is a schematic diagram of a telephone network constructed in accordance with the present invention.

FIG. 2 is a schematic diagram showing in more detail a digital telephone switchboard in the telephone network shown in FIG.

3 is a schematic diagram showing signal organization on a communication line shown in FIG. 1 and FIG.

4 is a system diagram of a digital satellite access device (DSI) connected to the network shown in FIG. 1 and FIG.

FIG. 5 is a schematic diagram showing in detail the data path in the call processor busbar connection device shown in FIG.

FIG. 6 is a schematic diagram showing in detail the data passages in the former shown in FIG. 4. FIG.

7 is a schematic diagram showing details of data passages in the processor shown in FIG.

8 is a schematic diagram showing details of data paths in the memory shown in FIG.

9 shows a number of messages that may be sent from a call processor to a digital satellite access device.

10 shows a number of messages that can be transmitted from the digital satellite access device to call processing.

FIG. 11 is a generalized flow diagram of the control function used by the call processor when sending and receiving the messages of FIGS. 9 and 10. FIG.

FIG. 12 is a diagram of a memory location allocation state showing a plurality of memory locations used for understanding the flow chart of FIG. 13 as shown in FIG. 12 (a) and FIG. 12 (b).

FIG. 13 is an operational flow diagram required for transmitting a message between the digital satellite access device shown in FIG. 4 and the call processor shown in FIG. 13 (a) and FIG. 13 (b).

FIG. 14 is a schematic diagram showing details of the buffer data passage shown in FIG.

FIG. 15 is a system diagram of the remote digital satellite unit shown in FIG. 1 and FIG.

FIG. 16 shows a number of messages that can be transmitted from a digital satellite access device to a remote digital satellite unit.

FIG. 17 shows a number of messages that can be transmitted from a remote digital satellite unit to a digital satellite contact device.

FIG. 18 is a flow chart showing the control program used in the digital satellite access device, which is composed of FIG. 18 (a) and 18 (b).

FIG. 19 is a system diagram of the accessory busbar connection buffer shown in FIG. 4. FIG.

20 is a schematic diagram of the diagnostic circuit shown in FIG.

21 is a diagram showing the operation of these devices during the mutual conversion of messages between the maintenance processor and the digital satellite access device, consisting of FIGS. 21 (a), 21 (b) and 21 (c). .

22 is a schematic diagram showing the automatic test circuit shown in FIG. 2, and FIGS. 22 (a) to 22 (e) show the tone generator circuit, the tone receiver circuit, and the frequency used in the auto test circuit of FIG. A detector circuit, an automatic test control circuit and a dial pulse detector circuit are shown.

FIG. 23 is a view showing a part of the maintenance and right circuit shown in FIG. 15, and FIGS. 23 (a) to 23 (e) respectively show an automatic test control circuit, a timing circuit, Diagram showing a detector circuit, a tone circuit, an alarm control and receiver reset circuit, and a dial pulse circuit.

24 is a schematic diagram showing the organization of the control module used by the maintenance processor.

FIG. 25 is a diagram of FIG. 25 (a), FIG. 25 (b) and FIG. 25 (d), which shows a number of transmission relationships that occur during the automatic test operation.

FIG. 26 is a distribution diagram showing details of the DSIFLD module shown in FIG. 24; FIG.

FIG. 27 is a distribution diagram showing details of the DSITMO module shown in FIG. 24; FIG.

FIG. 28 is a distribution diagram showing details of the DSICOM module shown in FIG. 24;

FIG. 29 is a distribution diagram showing details of the DSIMSG module shown in FIG. 24; FIG.

FIG. 30 is a flow diagram showing the details of the means shown in FIG. 18, comprising 30 (a) and 30 (b).

FIG. 31 is a flow chart showing details of the means shown in FIG. 30, comprising 31 (a) and 31 (b).

32 is a flow diagram showing details of the means shown in FIG.

33 is a distribution diagram showing details of the DSICAL module shown in FIG. 24;

FIG. 34 is a distribution diagram showing details of the DSIAT module shown in FIG. 24; FIG.

Figure 35 is a function flow diagram used to understand the possible interactions that occur during automated test processing.

* Explanation of symbols for main parts of the drawings

10: digital telephone exchange station 13: remote digital phase unit

14: digital satellite connection device 15: multi-path communication line

16: port group trunk line connection device 17: call processor bus line connection device

18: Maintenance bus connection buffer 19: Port circuit

20: automatic test circuit 25: forming machine

27: processor 28: memory

29: shock absorber 30: diagnostic circuit

79: maintenance and management automatic test circuit 300: maintenance processor

402: port group unit 408: call handler

The present invention relates to a telephone network, and more particularly to a telephone switching system characterized by switching a call to a group of remote ports in the network.

U.S. Patent Application No. 924,883 describes a telephone network including a digital switching center for performing switching operations.

In this network, telephone lines from subscribers and relay line circuits from other telephone switching centers are directly connected to the digital telephone switching center through the multiple line and trunk line circuits in the port group unit. This connection is made through conventional tips and rings or similar conductors extending from each subscriber or switching center to the digital switching center.

These conductors carry signals in analog form representing voice and surveillance information. Surveillance information received from the telephone exchange office is called "sense monitoring" information and contains hook status and dial pulse information and is sent to the port group unit, and conductors are called "control monitoring" information, ringing and other Include other information.

Each port group unit is connected to a plurality of telephone lines through respective port circuits such as line or repeater circuits. Each port circuit inverts the input speech signal into a pulse code and a modulated signal which are multiplexed and fed into a series of pulse trains on a port group trunk. Sensing monitoring information is also multiplexed in this pulse train.

The Time Slot Interchange (TSI) matrix network receives this pulse train and strips the input sense information to accumulate in the pot data accumulation area assigned to each pot circuit. The port event handler modifies and uses the information in each region to sample information in each port data accumulation region and send a message to the call control handler. The call control processor sends information, including instructions, to each port data accumulation area to operate the port event handlers to control the lines of the corresponding telephone subscribers, and sends these commands to the TSI matrix network to establish a switching channel through the network. Information is sent to cause the called telephone to establish a passage for digitalized voice signals on the same or different port group trunks.

Commands from the call control processor to the port event handler enable transmission of the dial tone, termination of the dial tone, or ringing of called and calling telephones. The port event handler generates control monitoring information in response to these commands. The control monitoring information inserts the voice information in digital form to be transmitted to the port group unit connected to the port group trunk. The corresponding port group unit then performs a number of functions in response to the command and inverts the digital voice data signal in analog form for transmission to the telephone line and telephone line of the subscriber via a particular port circuit.

U.S. Patent Application No. 924,883 describes a signal call processing system of this general structure that acts as a digital telephone exchange. US Patent Application No. 10,910 describes a digital telephone switchboard comprising two such call processing systems operating in parallel with a maintenance processor. Both parallel call processing systems simultaneously receive input signals from subscribers and trunk lines and operate synchronously. However, the signal from only one of these call processing systems passes through the port group unit to the subscriber and the trunk line. The maintenance processor system analyzes the synchronization loss, even odd error, and other conditions between the two call processing systems. This determines that the two parallel call processing systems actually control the telephone network.

This type of digital switching center must use a telephone line from each subscriber's location to the location of the digital central switching center. This improves performance and is economical when the subscriber is located in a relatively close area around the digital switching center or is roughly widely distributed. However, for most applications, telephone network subscribers will be geographically remote. For example, subscribers live in many small towns in rural areas and in apartments in cities.

Telephone networks in these applications each combine with a number of cables to make a connection. This cable shall be more than an electrical conductor. Multiple gain devices are needed for these conductors, typically at least one gain device is needed for each subscriber line. Therefore, cable expenses increase as the number of subscribers increases. Also, in most states, the amount of call in this network, such as the maximum call amount, is very low. Therefore, the actual use of the telephone line is very expensive and inefficient.

The collector can efficiently utilize data channels in the digital data network. Basically, digital data circuitry includes a modulation and demodulator for causing digital information to be transferred onto a conventional telephone network in analog form. When a large number of subscribers in an area need only slow data transfers, each subscriber is connected to the local concentrator at a particular location by two low speed modulation and demodulators. These two low-speed modulation and demodulators are located at the subscriber's position and the collector's position, respectively. The collector position will have one such slow modulator and demodulator on each input telephone line. The digital processing circuit will have a high speed modulation and demodulator in the high speed path of the data processing center. The digital processing circuit inverts the digital signal between a series of time multiplexed high speed digital pulse trains received from a high speed modulation and demodulator in the high speed path of the data processing center and applied to the high speed modulation and demodulator and the low speed modulation and demodulator of the current collector. Sometimes these concentrators are so sophisticated that they congregate very loudly.

However, for most applications, the actual aggregation is 40: 1 or less. In addition, this method is not easy to apply to the conventional voice telephone method. High-speed data networks require special state telephone lines that are expensive to use and some expensive modulation and demodulators. Indeed, the modulation and demodulators and digital processing circuits that make or respond to carriers with finite frequency bands are very complex and expensive independent switches. In addition, although readily applicable to telephone networks, the economical advantage of replacing this type of collector network at remote locations within the telephone system is economically incorrect by saving cables in other ways.

Another method that can be applied to the telephone network is to install a remote port unit at the center of the subscriber and to specify the number of communication lines between each subscriber and a particular unit connected in place of one or more lines in the analog part of the digital switching center. For example, to reduce one to three lines. However, as described in US Patent Application No. 10,910, it is difficult to provide the system with a number of maintenance functions provided in conventional digital telephone switching centers.

One such repair function is the test call function described in US Patent Application No. 10,910. In such a system, the circuitry associated with the maintenance processor can effectively disconnect two telephone lines from each subscriber and complete the selected call from one such line to the other via a test access relay. have. This provides a particularly useful maintenance tool for performing preliminary maintenance and other diagnostic functions. In this system, however, all port group units are at a digital telephone exchange, so that the interconnection between the maintenance processor and its associated circuits and the test access relays of the port group unit and port circuits is facilitated. There is also a single test call generator that provides all test calls through test access relays and other switching circuits. However, this type of test call generator is not easy to apply to a remote port unit. This application adds to the cost of the cable because it requires separate connections to the test access meter. In addition, it is difficult to obtain the tone to be generated and transmitted and the information necessary to control the tone.

It is therefore an object of the present invention to provide a method and apparatus for testing a remote port unit.

It is another object of the present invention to provide a method and apparatus for performing a simple test that provides an apparatus for determining whether another diagnosis of a remote port unit is needed.

It is yet another object of the present invention to provide a method and apparatus for testing a remote port unit that makes it easy to make these calls on a given baseline.

It is yet another object of the present invention to provide a method and apparatus for testing a remote port unit that easily diagnoses when an initial test indicates a failure.

According to the invention, the remote subscriber line is connected to the connection device at the digital central switch via a communication line with the remote port unit. The automatic test circuit interacts with the connecting device, which makes the remote subscriber line designed when making a command disconnect through the remote test access relay and completes the call between the remote subscriber line and the automatic test circuit. The automatic test circuit then generates a first tone for the remote location. When the remote location receives the first tone continuously, it transmits a second tone and a dial pulse with successively predetermined time characteristics. The automatic test circuit monitors the incoming tone and dial pulses to determine whether the test is completed in series. If not, additional measures can be taken through the connecting device to isolate the problem that arises, including the use of automated test circuits at regular intervals.

Therefore, the present invention provides a simple test that is done easily and quickly. This requires an automatic test circuit to interact with the interface and add a test circuit to each remote port unit. In one embodiment, the digital telephone exchange includes an automatic maintenance device and the test is facilitated by connecting the automatic test circuit to the pot on the digital central switch. In addition, if this test is wrong, ancillary tests may be made to isolate the problem.

The invention is particularly described in detail in the claims. The above and other objects and advantages of the present invention can be easily seen from the following description described in detail with reference to the drawings.

A. Telephone Network

1 illustrates a telephone system providing multiple levels of aggregation. At the heart of the telephone network shown in FIG. 1 is a digital central office (DCO) 10 of the type described in US Patent Nos. 10,910 and 924,883. A number of local telephone lines 11 come out of the digital telephone switching center 10 and are connected to the plurality of local subscribers according to the above-described application.

This particular network depicts an embodiment of a system in which "remote" subscribers are clustered around a number of shipping positions (A to G). Multiple telephone lines 12 interconnect these remote subscribers at locations A-G to remote port units each containing a Remote Digital Satellite Unit (RDSU) 13A-13G.

Each remote digital satellite unit 13 is connected to and operates in response to a digital switching center 10 via a digital satellite access device (DSI) 14 and a multipath communication line 15. For example, the digital satellite connection device 14A is connected to the remote digital satellite unit 13A through the communication circuit 15A. At this time, the other digital satellite units 13B, 13C, and 13D are interconnected by the communication lines 15B to 15D to form a good chain connection from the digital satellite unit 14A. This type of connection is well suited when the clusters of remote subscribers are distributed along the backline from the digital switched office location. The digital satellite device 14E, the communication line 15E, and the remote digital satellite unit 13E represent a connection type that can be very usefully used in an apartment in a city.

In particular in the embodiments described above, each remote digital satellite unit can be connected to a number of 240 subscriber telephone lines as shown at location E, and each digital satellite connection can adjust the volume of calls from 240 subscribers. . A typical number of subscribers, each connected to such a remote digital satellite unit 13, is shown in FIG. In addition, thirty digital satellite connections 14 may be connected to a single digital telephone switchboard.

From a general point of view, it can be seen from the circuit of FIG. 1 that the cables connected to this network can be reduced in size. Each communication line 15 may include one, two or three data paths. Therefore, the cable can be reduced from 80: 1 to 240: 1. The actual aggregation that can be made depends on the volume of calls of the plurality of remote subscribers and the capacity of the communication line 15.

As will be described later, the communication line 15 in this embodiment carries pulse code modulated signals over time division multiple passages. Each digital satellite access device 14 is connected to a digital switching center and inverts voice and monitoring information between the format of the digital switching center 10 and the format of each communication line 15. The digital satellite access device 14 also reconstructs the supervisory and voice data signals and allocates a particular time slot, or channel, on the communication line 15 to a particular remote subscriber when this telephone line is used for telephone conversation. Typically, the number of useful channels on communication line 15 is less than the number of subscriber lines.

Each remote digital satellite unit 13 provides a connection device between the conventional telephone line and the communication line 15 exiting from this unit 13. This combines the voice signal between the telephone or subscriber line, and makes sense monitoring information in response to activity by the subscriber, and responds to control monitoring information received from the communication line 15. In addition, the remote digital satellite unit 13 reconstructs the monitoring information, transmits the information to the appropriate telephone line in response to the received control monitoring information, and performs the analog / digital conversion necessary for transmitting and receiving analog voice signals on the telephone line. Do it.

FIG. 2 is a modified view of the telephone system described in US Patent Application No. 10,910, which is cut away from FIG. Also shown in FIG. 2 is a remote digital satellite unit 13 having a single digital satellite access device 14, a communication line 15 called span, and a plurality of telephone lines 12 exiting the remote subscriber's cluster. Is shown. Elements common to the above description of drinking are denoted by the same reference numerals. In particular, 100 to 399 reference numerals are in US Patent Application No. 10,910 and 400 to 499 reference numerals are in US Patent Application No. 924,833. Their function is to interconnect only certain elements, as is known. In particular, the digital satellite access device 14 is connected to this system at four points. First, there is a port group trunk line connecting portion 16 which interconnects a port group trunk line and a digital satellite connection device from the TSI matrix switch A 200 and the TSI matrix switch B 100.

The second connection is to be connected to the call processing system by a call processor bus interface (CBI). In particular, CBI " A " 17A establishes a communication path between the digital satellite connector 14 and CPU " A " 204, and CBI " B " A communication path is set between the 104. Each CBI 17 may be connected to a number of other digital satellite access devices (ie, all 30 in one embodiment). Each call processing bus interface 17 modifies data between the corresponding call processor 408 and the available format and digital satellite interface 14. Each CBI 17 polls its corresponding digital satellite interface 14 to request to enter its call processing unit 408. In addition, each CBI 17 detects an error and interferes with a particular digital satellite interface 14 to allow no operation through that interface.

The third connection between the digital satellite access circuit 14 and the digital telephone exchange office 10 is a maintenance bus interface (MBI) that establishes a communication path between the maintenance processor 300 and the digital satellite access device 14. It is made by the repeller 18. The MBI buffer 18 is also connected to each digital satellite connection device connected to the call processing busbar connection device 17. The MBI buffer 18 provides inversion between the signal format on the busbar of the maintenance processor 300 and the signal format at the digital satellite interface 14. This modifies the time, extends the addressing, and performs a selection operation to determine when the connected digital satellite connection device 14 wishes to communicate with the maintenance processor 300.

The fourth connection between the digital satellite junction 14 and the digital switched office 10 is to be connected to a switch transient control circuit 301 which sets up two call processing systems to actually control the telephone network.

These first three connections were made by the digital satellite access device 14, the communication line (span) 15, and the remote digital satellite unit 13, the processor 300 and the call processing system 408A shown in FIG. And joint communications paths for operating in response to control of 408B. However, this operation consists of a minimum change of the actual line. The major change is in the control functions used by the call processing system 408 and the maintenance processor 300. Therefore, the possibility of the call processing system 408 shown in FIG. 2 is included and used in connection with the present invention, further increasing call processing efficiency and reducing costs.

As described above, the port group unit 402 interconnects the digital telephone switching center 10 shown in FIG. 1 to the plurality of local subscriber lines 11 via the port circuit 19. However, in this particular embodiment according to one aspect of the present invention, the automatic test circuit 20, which cooperates with the maintenance processor 300 and tests the circuit in the remote digital satellite unit 13, is connected to the main group controller. It is connected to the connection circuit.

B. Communication Lines 15

The particular structure of the plurality of elements shown in FIG. 2 is determined in part according to the signaling characteristics of both ends of span 15. Therefore, the span 15 will be described in more detail. The span is a known differential electrical connection between two remote points. As described later, span 15 may include two or three span circuits or passageways that operate independently. Right-angle span circuitry defines a number of time domain channels. The specific configuration and purpose of the data signal on this channel is that of a single "superframe" (i.e., passing over a span circuit in a series of bits with the superframe "n-1" and "n") before and after. 3 shows the configuration of the superframe "n + 1".

Each superframe includes 12 consecutive frames (frame numbers 1 to 12). In turn, each frame contains 193 bits and one sync bit that form 24 8-bit words. According to the invention, the time interval of each word corresponds to a channel. Therefore, word number 1 corresponds to channel 1 and word number 24 corresponds to channel 24. Further, as shown on the right side of FIG. 3, each frame terminates the sync bit and the sync bit pattern of the superframe is selected so that the sync loss can be easily detected. In this figure, "D" represents a signal to be interpreted as voice data.

Two of the twelve frames carry surveillance information and command it across the span. This is done by "bit stealing" during the 6th and 12th frame times. During the sixth frame, at least significant bits (bits 8) in each word 1 to 24 are encoded into " A " signaling bits in response to sensing monitoring information from the subscriber's remote digital satellite unit 13 assigned to the corresponding channel. do. For example, if the subscriber is off-hook to receive channel 7, the off-hook information is transmitted during A7 bit time (ie, at least significant bit of word number 7 in the sixth frame). Therefore, during the sixth frame, the sensing monitoring information for the 24 subscribers is transmitted from the remote digital satellite unit 13 to the digital satellite access device 14.

The least significant bits in each word 1 to 24 make up the "B" signaling bit for the 12th frame. In this embodiment, the "B" signaling bit is used to transfer a 24-bit message between the digital satellite access device 14 and its remote digital satellite unit 13.

All information in the data word containing at least significant bits in each word during the sixth and twelfth frames is also transferred to the port group trunk 16. Errors occur during the sixth and twelfth frames, but these errors do not significantly reduce the sound quality ultimately heard by the subscriber.

Hence, FIG. 3 illustrates a particular embodiment of a time division multiple system that defines a number of channels. As described later, each of these channels is assigned to this subscriber line when a particular subscriber line is used. It also provides fast transfer techniques for "A" and "B" signaling bits, such as the "A" and "B" bit signaling rates of 2,000 bytes / second in certain embodiments, as long as each frame requires 125 microseconds. to provide.

The circuit along this line is a span device. 4 shows three isolation spans 15 coupled to a span device within a digital satellite interface (DSI) 14. In particular, the digital satellite connection device 14 includes a span 0 device 21, a span 1 device 22, and a span 2 device 23. Span devices 21 to 23 are connected to TSI matrix switch A 200 and TSI matrix switch B 100, respectively.

The span device includes a span transmitter, a span receiver and a span connector, respectively. The transmitter accepts data from the port group trunk line connection 16 and adds the registration pattern shown in FIG. 3 to form data that simplifies the span, and the instrument 24 of the telephone exchange station driving the span 15. Information is sent to the span connector for continuous transfer over the amplification circuit. The span receiver synchronizes the input data from the span connector and changes it in a form and ratio compatible with the port group trunk line connection 16. The span connector provides a suitable signal level and time for the span device between the digital satellite interface 14, the port group trunk line connection 16, and the instrument 24 of the telephone exchange.

The span transmitter also synchronizes the device to the digital switching center 10, forms a signal on the port group trunk line connection 16 within the span format, and achieves the correct synchronization pattern for each superframe. Insert the correct sync bit at the frame end and transfer the data to the span connector for continuous transmission over the span 15. The span receiver synchronizes the input span data and forms data for compatibility with the port group trunk line connection 16. It also sends voice data and monitoring data on the port group trunk line connection 16. The span connection device interconnects the digital satellite connection device 14 to the port group trunk line connecting portion 16 and the telephone exchange station repeater 24. This circuit may include a bit error comparator. Therefore, each span device provides a passage between the TSI matrix switches 100 and 200 and the span 15.

In order to facilitate understanding of the present invention, a plurality of communication paths, i.e., (1) call processor-digital satellite interface passages, (2) digital satellite interface-remote digital satellite unit passages, and (3) maintenance processor-digital satellite connection A number of circuit configurations and operations for establishing device passages will be described.

C. Call Handler-Digital Satellite Access Channel

The call processor-digital satellite interface includes one of the call processor busbar connection circuits 17A and 17B and respective call processor systems 408A and 408B as shown in FIG. Independently operable former generator circuits 25A and 25B in digital satellite connection 14 are connected to bus 26 and processor 27 connected to connection circuits 17A and 17B, respectively, and coupled to control processor 27. The passageway of the memory 28 and the shock absorber 29 to be used. The shock absorber 29 is part of the communication path between the digital satellite connection 14 and the corresponding remote digital satellite unit 13. This shock absorber 29 also acts as an input / output connecting device between the bus bar 26 and the spanning devices 21 to 23. The diagnostic circuit 30 is connected to the busbar and is described later in connection with the repair processor-digital satellite connection path.

5 shows one call processor bus bar connection circuit (CBI) 17. This is the bus receiver 1711 and the bus driver connected to the receiver-driver 1710 connected from the corresponding one of the call handlers 408A and 408B to the busbar and to the corresponding one of the formers 25A and 25B. (1712). Each call processor bus bar connection circuit 17 extends the corresponding call processor bus bar to the corresponding former. The address signal is coupled to the address latch circuit 1713, and optionally coupled to the driver 1712 via the multiplexer 1714 when the address corresponds to a position associated with a particular digital connection device 14. Data from the call processor 408 is also transferred from the receiver-driver 1710 to the bus driver 1712 via the multiplexer 1714. Other circuits set a number of delays and controls to enable communication. Once the data is retrieved, it is received at the bus receiver 1711 and transferred to the receiver-driver 1710. The even odd circuit 1715 monitors the even odd error.

Each CBI 17 also includes a counter 1716 that selects a plurality of multiple connection devices that may be connected to the CBI 17 via a driver 1917. This selection operation occurs when the call handler 408 is not communicating with the CBI 17. When the digital satellite access device is to be repaired, information is transferred from the bus receiver 1711 to the state latch circuit 1718 which is periodically interrogated by each call processor 408.

It is also possible to "mask out" the particular connector 14. Masked random access memory (RAM) 1720 may be loaded with suitable mas- tic bits via receiver-driver 1710 and multiplexer 1721. The counter 1716 confirms the connecting device during each selection, the number is transferred through the multiplexer 1721 and the mask RAM 1720 generates a mask signal when the corresponding connecting device is masked out. However, this masking does not interfere with the communication between each call handler 408 of the attachment 14.

As described above, the former 25 as shown in Figs. 4 and 6 receives data from the call processor 17, transfers this data to the processor 27 shown in Fig. 4, From 27); Transfer the data to the call handler 17. Communication through the generator 25 is in the form of a message. An input message is received from the bus driver 2510 shown in FIG. 6 by the bus receiver 2510 shown in FIG. These messages are sent consecutively by 8-bit bytes and transferred into First-in / First-out (FIFO) 2511. The input FIFO controller 2512 controls transfers from the bus receiver 2510 to the input FIFO 2511 and transfers control to a standard program connection adapter 2513. Each time the call processor 408 sends a message to the interface 14, it addresses the corresponding input FIFO 2511 and is loaded into the input FIFO 2511 with the corresponding control signal received in the bus receiver 2514. Send data to be coupled to common control address read and latch circuit 2515. Input FIFO controller 2512 responds to transitioning data into input FIFO 2511. As is known, data entering this FIFO is automatically transitioned to output. When the data byte is at the output of the input FIFO, the input FIFO controller 2512 generates a byte useful signal for the input of the program connection adapter 2513, after which this information is sent from the FIFO 2511 by a transition signal. Transition into data input of program input adapter 2513.

When the message is sent to the call handler 408, it passes through the output FIFO 2516 under the control state of the output FIFO control circuit 2517. When the output FIFO 2516 is left empty, the controller 2517 sends a RESEND signal to the program connection adapter 2513. When a message is sent to the output FIFO 2516 on the data line, a transition signal is also sent. After the message is sent, output FIFO controller 2517 receives a RESEND signal. The output FIFO controller 2517 also sets the SERVICE REQYEST bit in the status register 2518.

Each call processor 408 periodically addresses the status register 2518 in each generator 25 and decodes the status register through the bus driver 2519 in accordance with a control signal passing through the bus driver 2520. When the call processor 408 determines that the output FIFO 2516 includes the message, it addresses the output FIFO 2516 and decodes consecutive message bytes that appear under the control of the output FIFO controller 2517. When the message is complete, the output FIFO controller 2517 sends a retransmission signal, causing another message to be sent.

If the formatter 25 is included in each of a number of digital satellite connection devices that may be connected to the call processor busbar connection device, the call processor 408 first identifies the digital satellite connection device and then assigns a common address to address the former. In communication with the particular former 25. Therefore, after a particular digital satellite interface is selected, only the formatter in this interface will respond to the following signals, even if the specific formatter address is common to all of the formatters' addresses. This state appears until the call processor 408 releases the digital satellite unit and sends another message to "unselect".

The even odd circuit 2521 detects even odd errors and examines all addresses and data to set the even odd error bits in the status register 2518.

The data buffer 2522 is connected between the processor 27 and the program connection adapter 2513. This includes a number of connections to the processor 27 and the memory 28 that cause the program connection adapter 2513 to perform control operations.

When the former is used in a network constructed in accordance with FIG. 2, one of the call processing systems, labeled "A" or "B" system, actually acts as a switching control. The A / B selection circuit 2523 includes an A / B confirmation switch that is set upon connecting the generator 25 to an "A" or "B" call processor. Processor 27 will send data to output FIFO 2516 in formers 25A and 25B of FIG. However, this will only respond to the generator connected to the selected call processor 408A or 408B. In particular, the selection A / B signal from the switch transient controller 301 and the spanning device in FIG. 2 is represented by the BSELO signal in FIG. When this signal is issued, the data buffer 2523 in the former 25A is activated and the data buffer in the former 25B is stopped so that the "A" system controls the calling process. If no BSELO signal is present, the "B" system controls the calling process. When the span 0 device 21 is removed, the SCPO signal comes out, and the BSEL 1 signal from the span 1 device 23 that carries the same information is used.

In order to communicate between the call processor 408 and the connection device 14 shown in FIG. 4, the processor 27 and the memory 28 must be interacted with each other. Processor 27 and memory 28 include a conventional microprogram digital computer system. Processor 27 is shown in FIG. 7 and memory 28 is shown in FIG. The process 27 in this particular embodiment is the Motorola 6800 Micro Programmable Digital Data Processing System. This is a microprocessor unit connected to a number of other units including a clock generator 2711, a stop / single controller 2712, a reset generator 2713, a program connection adapter 2714, and a watchdog timer 2715. 2710.

The clock generator 2711 supplies a plurality of clock signals necessary for sequentially processing the MPU 2710 through a plurality of processing means. Every six milliseconds or every other predetermined time, the buffer 29 prevents the MPU 2710 from connecting to the program connection adapter 2714 to initiate six milliseconds of normal call processing or maintenance and management actions that make up the DSI program. Generates a second clock signal. This repair function or action is to test the alarm input present in the program connection adapter 2714 from the buffer 29, the span receiver and the span transmitter.

The stop / single controller 2712 acts as a fault quest and prevents the MPU 2710 from operating in a normal cycle. The watchdog timer 2715 is normally reset periodically when the MPU 2710 performs a number of functions. However, if the MPU is locked to perform its function in the normal mode of resetting watchdog timer 2715, timer 1715 will stop and prevent MPU 2710 from operating to begin the recovery sequence.

BUS SYNC, ADDRESS, DATA, READ / WRITE CONTROL, and RESET signals are shown in the generators 25A and 25B, memory 28, It is applied to the bus bar 26 so as to be transferred to the shock absorber 29 and the diagnostic circuit 30. In addition, data signals may be received from these elements, respectively, while controlling other signals.

Memory 28 includes bootstrap ROM 2810, program RAM 2811, and working RAM 2812. Bootstrap ROM 2810 includes a small portion of a program that is automatically addressed when a power-up signal is applied to reset generator 2713 of FIG. Such bootstrap programs are known. The address is applied to the peripheral address decoder 2813 and the memory address decoder 2814. Memory data buffers 2815 are interconnected to data paths between processor 27 and respective memories 2810, 2811, and 2812. However, the memory data buffer 2815 becomes inoperable when the peripheral address decoder 2813 decrypts the peripheral address.

During the reset operation of the call processing system, the maintenance processor 300 loads information into the program PAM 2811 and the construction PAM 2812. In particular, this is done when the front end circuit 30 generates a DOWNLOAD signal and a WRITE signal. This is because a data DATA signal representing a program and data reference is loaded into the program and operating RAMs 2811 and 2812 as the logical AND circuits 2816 and 2817 perform a write operation in the memory. On the other hand, the decryption operation can only occur in response to the address signal from the processor 27.

The format of the message to be transferred between the digital satellite connection 14 and the call processor 408 is shown in FIG. 9 and FIG. Each message contains at least one 8-bit byte. The first byte contains a 4-bit group representing the message, and the second byte includes a 4-bit group representing the byte number in the message. Therefore, the ORIGINATE message in FIG. 10 contains the hexadecimal value "5". Where "0" indicates the initial message and "5" indicates that the message contains 5 bytes. The initial message indicates that the remote subscriber is off-hook. The second byte in the initial message includes a remote subscriber calling (ING) satellite line number (SLN). The third byte contains the assigned channel number, the fourth byte contains the "all channel busy" delay count, and the fifth byte contains the common line confirmation bit. At this time, the second, third, and fifth bits completely indicate the channel numbers on the calling common line and the spanning device 15.

FIG. 11 shows the control circuit of the call management program executed by the call processing system of US Patent Application No. 924,883 modified by adding the digital satellite unit 13 and the connecting device 14. In this calling program, a number of test sequences are set. These are generally shown in FIG. 11 as the order 31 in which call processing examines the ANI common line test queue and the order 32 in which the call processor examines the DNI queue. Order 33 is new and will describe this order 33 and other new orders. If the digital satellite interface 14 does not need to be repaired, the call processor uses a sequence 34 for detecting a PL event and a sequence 35 for determining whether a maintenance processor should be communicated. In this next step 31, the reciprocating operation is performed again.

Referring to sequence 33, if digital satellite interface 14 is to be repaired, it operates in a sequence of orders while the call processor decrypts the message, generates the message, and then transfers the message back to the digital satellite interface. This is transitioned. Step 36 decodes the message, and step 37 determines when the even odd circuit 1715 of FIG. 5 detects an even odd error. If no even odd error is detected, the message is processed within sequence 38. When the feedback message is transmitted to this connection device 14, the procedure 39 can transmit it in the procedure 40.

If an even odd error is detected in sequence 37, the sequence 41 determines whether three consecutive errors have been detected. With a few attempts, the order 41 is complete by transitioning the operation back to the order 34, and if the repair request is not fully repaired, the order 33 switches back to the order 36.

Figure 12 illustrates a number of registers that can be addressed by the call processor. These registers are used during transmission and reception of messages between the call processor and the digital satellite interface 14, as shown in more detail in FIG. If the order 33 of FIG. 11 indicates that the digital satellite connection 14 needs to be repaired, the call processor processes the order 36 shown in FIGS. 11 and 13A. In particular, in means 43, the call processor decrypts the CBI status register 1718 of FIGS. 5 and 12A. The CBI status register contains two 8-bit bytes. The most important bit is the "Repair Request" bit, which contains "1" if the corresponding digital satellite unit is to be repaired. Selecting this is done under the control of the DSI counter 1716 of FIG. In the means 44, the satellite number is accumulated in the SIZE DSI FORMATTER register 2524 of FIG. 12 in the circuit 2515 of FIG. 6 that includes the DSI number in the five least significant bits.

The call handler then decodes the data byte by performing a decryption operation from the output FIFO 2516 (mean 45). If this happens, the data byte is passed through the bus driver 2519 and through the CBI 17. It is sent to each call handler 408 via a data path. The call handler 408 decodes the first byte and immediately determines the length of the message. If many message bytes are received, means 46 branches back to means 45 to decode consecutive data bytes from output FIFO 2516. Once all messages have been transferred, the order 36 of FIG. 11 is complete and the order 37 tests for even odd errors.

The order 40 of FIG. 11 is set by means 47-51 of FIG. Once the message is forwarded, the call handler 408 again accumulates the DSI number in the least significant bit of the occupied DSI former register 2524 shown in FIG. 12 (means 47) and then the status register 2518 in the occupied former. ) Means (48). As shown in Fig. 12B, the least significant bit is a bit in a DSI call. If this bit is set, the message cannot be conveyed and means 49 bypasses means 50, 51 and 52. However, if the bit during the DSI call is cleared, the data byte is transferred to the input FIFO 2511 of FIG. In addition, since the first byte represents the number of all bytes in the message, the call handler knows when the additional message bytes are to be transferred. Once the additional message bytes have been transferred, the means 51 branches back to the means 50 until all message bytes have been transferred so that it branches to the means 52 so that the generator status register 2518 is decrypted. The generator status register 2518 is decrypted. The formatter state register 2518 is decrypted after the message has been transferred to the call handler according to the shunt of the means 46.

The formatter status register 2518 includes an even PARITY ERROR bit. If there are no even odd errors in this register, then means 53 branches to means 54 where the call processor decodes CBI status register 1718 of FIGS. 5 and 12A to detect even odd errors or hangs. The CBI status register 1718 includes even odd error bits and DSI latched bits. If neither of these bits is set, the means 55 branches to the means 56 such that the call processor sets the DONE bit in the former control register 2526 in the circuit 2515 of FIG. The data is then sent to a de-former register 2527 in the means 57. Writing operation to the address of the release generator register 2527 results in a release operation.

Assuming there is an even odd error indicated in the generator status register 2518, the means 53 branches to the means 58 where the CBI status register 1718 is decrypted again. If there are no even odd errors and there is no response stop indicated by bits 8 or 10 in the CBI status register 1718, the means 59 branches to the means 60 and is in the former control register 2526 in the circuit 2515. The retransmission bit is set. If this is not the third attempt, the means 61 branches back to the means 57. As a result, the active bit is not set in the former control register 2526. Therefore, the next selection of the CBI status register 2518 requires a transmission to the call handler.

If there is a response stop or even odd error detected by the means 55 or 59, the operation is transferred to the means 62 to set the retransmission bits in the former control register 2526 in the circuit 2515. In means 63, a test is made to determine if there is a third attempt to decrypt or write the register. If not, the means 63 branches to the means 64 so that an even odd error in the CBI error register 1719 or the appropriate one of the DSI latch bits in the same form as the CBI status register 1718 of FIG. 12A. The bit is cleared. This next means 64 transfers the motion back to the means 57. If three attempts are made to send a message to or receive a message from the digital satellite access device 14, the means 61 or 63 branch to the means 65, as the error is described later. It is recorded in the maintenance processor 300 via a communication path between the maintenance processor and the digital satellite access device 14.

D. Digital Satellite Interface-Remote Digital Satellite Unit Passage.

Referring back to FIG. 4, the communication path between the digital satellite connection 14 and the digital satellite unit 13 associated therewith is a buffer 29, a span device 21 to 23, and a span 15 at a central position. Instrument 24 of the telephone exchange station which connects the spanning device to (). The buffer 29 communicates between the processor 27 and the remote unit of the system using the " B " signaling bits, as shown in FIG. This is a conventional program connection adapter compatible with two span transmission circuits 2910 and 2911, two span reception circuits 2912 and 2913, a reception output control circuit 2914, and the processor 27 of FIG. A configured processor interface 2915.

Each of the transmitting circuits 2910 and 2911 has the same structure, and receives data from the processor 27 by the processor connection device 2915. These transmitters each include a FIFO with serial / parallel and input / output capabilities. Processor interface 2915 provides data signals in parallel, transfers data, and provides control signals to indicate the load of data. Each transmitting circuit 2910 and 2911 also receives an active input that controls data to be sent to span 0 transmitting circuit 2910 or span 1 transmitting circuit 2911. The SHIFT IN STROBE signal in the strobe causes the data to be loaded in parallel into the FIFO input registers and ripple through the FIFO to the output registers. Once the data is loaded, processor 27 issues a DATA LOADED signal that sets the latches per two transmitters to provide input to the span output active latch circuit.

The timing signal from the transmitter within the corresponding spanning device includes a synchronization signal that sets an output active latch on the first synchronization signal representing the data load signal. This activates the corresponding FIFO output in circuits 2910 and 2911 so that data is continuously transitioned on the strobe provided by the transmit end in the spanning device at a time corresponding to the " B " signaling bit time. Whenever the data load signal does not appear between two synchronization signals from the spanning device, the FIFO output is not activated in the transmitting circuits 2910 and 2911, so that an "I" indicating an idle (IDLE) message (Fig. 16). The order of is transmitted over the same span as the "B" signaling bits.

Span 0 receives circuit 2912 and span 1 includes the same circuit including a FIFO to receive input span data from the span device receiver in response to a STROBE signal provided by the receiver. Receive Another timing signal includes a sync pulse that clears the FIFO and its associated reception counter and represents a message received prior to receiving a span (SPAN) message. More specifically, a series of input data is transferred into the FIFO by the strobe signal. The receive counter is then incremented until all "B" signaling bits (24 bits in the particular embodiment of Figure 3) indicate that they have been received. If this happens, the span message receive signal will appear.

After each SYNC pulse has been received by the corresponding receiving circuits 2912 and 2913, the receiving output controller 2914 selectively activates the outputs of the receiving circuits 2912 and 2913 so that other than the idle messages are received. Examine other messages in. If this happens, the span span message ready signal is set in the processor connection device 2915. Each registered pulse from the two spans clears the span received message ready signal. When the processor 27 decrypts the processor connection device 15, the corresponding display character is cleared.

Processor connection device 2915 provides a processor 27 that indicates that the span has an input message. This is accomplished by a FIFO ENABLE signal which indicates the span 1 receiver circuit 2913 when it appears strong and the span 0 receiver circuit 2912 when it does not appear strong. Processor 27 obtains data by parallel extraction of the active FIFO output register. Each decryption operation is performed by transitioning the information in the corresponding FIFO under the control state of the SHIFT OUT pulse, so that a continuous bit group is received. Each transition stop pulse also sets the OUTPUT REGISTER EMPTY signal, causing the blank display counter to be incremented. The blank indication disappears after the next transition stop pulse unless all messages are extracted from the receiving circuit 2912 or 2913.

Telephone switchboard repeater 24 in FIG. 4 transparently displays all bus signals. These eliminate ground noise and ground potential differences caused by the non-contact arrangement of the connection devices. These include a differential receiver and a differential driver for transporting over the span device 15. Therefore, the repeater 24 no longer needs to be described in detail.

15 is a basic schematic diagram of a typical remote digital satellite unit. Each passage in span 15 is connected to span monitor 70. Span monitor 70 records an alarm condition when the waveform is wrong or frame synchronization is lost during pulse code modulation transmission. If one of the spans operates with a supplemental span, the span monitor 70 improves the circuitry for replacing the failed span with the frozen span while controlling messages from the digital satellite access device. It also responds to the input signal to generate the basic clock waveform needed to operate the unit.

The span monitor 70 is connected to the transmitter / receiver circuit 71. The transmitter section indicates the span channel carrying this information, receives the digital voice data signal from the new channel inter-conversion circuit 72 in the form of pin code and separates the data signal into the bit strings transmitted at span intervals at the appropriate channel time. Insert it. The transmitter also inserts a frame suitable for the registered signal as shown in FIG. The transmitter also derives the functions necessary for the data buffer 73, so that during frame number 6 and 12 of each super frame, the circuit can insert A and B signals and bits.

The receiver portion of each circuit 71 receives information from the span 15, inverts this information into a form compatible with the rest of the circuit, and derives the clock signal. Necessary timing functions are provided so that A and B signals and bits can be extracted. This receiver uses channel identification from line channel interconversion circuit 72 to send each 8-bit word into the appropriate accumulation position. This receiver generates a frame alarm at a time when it cannot detect the correct registration pattern.

The transmit / receive buffer 73 monitors hook status information from the line circuit controllers 74A and 74B and extracts information from the input information used by the satellite controller 75. The buffer 73 also responds to the selection operation by inserting bits into the data queue at the correct time to indicate the need for communication with the call handler, as described later.

The line channel interconversion circuit 72 controls the transmission of voice data signals between the multiplexer and demultiplexer circuit 76 and the transmit / receive buffer 73 and the transmitter / receiver 71. The line channel interconversion circuit 72 provides the time necessary to keep the channel and line consistent.

The line level mulplexer / demultiplexer circuit 76 collects data representing voice data received in digital form from a number of CODEC circuits 77 coupled to the line circuit group 78. In a particular embodiment, this circuit includes one or more circuits connected to the 48 line circuit 78. These circuits arrange this data in an 8-bit wide format that can be interrogated by the line channel interconversion circuit 72 through suitable addressing techniques. Similarly, the demultiplexer circuit in each line level mulplexer / demultiplexer circuit is transferred to a corresponding CODEC circuit 77 which is inverted in analog form to allow information to be sent to the remote subscriber via the appropriate line circuit 78. Converts the signals received from the line channel interconversion circuit 72 to the appropriate format. CODEC circuit 77 and pre-circuit 78 operate as described in US Pat. No. 924,883.

Messages from the digital satellite connection 14 are sent from the buffer 73 to the satellite controller 75. The satellite controller 75 decrypts these messages and sends the appropriate signals belonging to the remote channel allocation message to the line circuit controllers 74A and 74B. It also sends remote channel allocation and line disconnection messages to line channel interconversion circuit 72 and decrypts the information to be sent to maintenance and management circuitry 79. These messages are encoded in B signals and bits.

Line circuit controllers 74A and 74B perform a number of functions. These handle all requests that occur. That is, when the subscriber hangs up his phone, the corresponding line circuit controller 74 responds. Each line circuit controller 74 allocates channels on span and unconnected lines defined by digital satellite connectors 14. This circuit 74 also controls the joint acknowledgment processor and encodes the initial message with proper joint matching.

These process the incoming call, control ring movement, provide the hook status information to the digital satellite access device 14 by appropriately encoding the "A" signal and bits, and perform many other functions. In one particular embodiment, each line circuit controller 74 may be installed with up to 120 line circuits.

Each line circuit controller 74 is coupled to the line circuit 78 through a line circuit clock divide buffer circuit 80. This circuit continuously buffers data between the line circuit controller 74 and the line circuit 78.

As will be clear, each call processor 408, digital satellite connection 14, and remote digital satellite unit 13 have the ability to perform multiple functions independently and to communicate multiple information items. Have This information is communicated by a message carried over the span 15 between the digital satellite connection 14 and the remote digital satellite unit 13. We will now describe the contents of these messages and the general sequence of operations within each unit.

The digital satellite access device 14 operates by selecting all of the remote digital satellite units 13 connected to this device by sending a selection unit for each B signal and period. As can be seen from the foregoing description and from FIGS. 3, 16 and 17, each message contains 24 bits. Referring to FIG. 16, a POLL message includes 24 bits arranged in a 4-bit group represented in hexadecimal form. Since the POLLING message has the sign byte "1" followed by ten ones and ten zeros, it is represented as "FFCOO" in hexadecimal notation. All these POLL messages (i.e., "IFFCOO") are conveyed continuously through each remote digital satellite unit 13 and returned to the POLL RESPONSE message shown in FIG. 17 during the same frame. The position between each ten bits and each unit 13 is the same. If a particular digital satellite unit 13 wants to communicate with the digital satellite connection 14, this inverts the bits in the corresponding position in the POLL message. For example, if the third digital satellite unit 13 (eg, at position C of FIG. 1) is desired to be repaired, the selection response is " IDFC 80 ".

A TEST POLL RESPONSE message corresponding to a TEST POLL message is indicated by the symbol " 5 " The bit order accompanying the sign in the test selection message is the same as in the selection message. That is, the test selection message is "5 FFCOO". However, during the test selection, each digital satellite unit 13 changes its corresponding bit whether or not maintenance is required. If all ten remote units are connected, the test select response message will be "5003FF". Other messages will be described when describing the present invention.

FIG. 18 shows an easy understanding of the operation of the digital satellite access device 14 while transmitting and receiving selection and response messages. When the system is activated, the startup sequence is performed and the system begins to operate (means 81). While doing the first means 82 in the sequence " IRQP ", the processor 27 waits for the predetermined period corresponding to the intervention interruption ratio to be completed. The use of " IRQP " and other ellipses shown in the figure will be a confirmation point and will help to adjust the sequence of operations shown in detail in this figure and other figures.

Each time an interruption occurs, the means 82 branches to the means 83, so the processor 27 tests a number of states described later and sends or processes a message in response to these states (means 84). When the message is sent, the means 84 branches in the "HSKPG" order shown in FIG. 8B. On the other hand, control is transferred to the means 85 in the " RMS " order in which the processor 27 determines whether or not the transfer is to the maintenance processor 300. If this transfer occurs, the means 54 branches off in the "HSKPG" order of FIG. 8B.

If a test selection occurs, the selection order "PTPG" begins at the means 86. The test selection message "5FFCOO" is sent to the means 87 and the test selection response message "5003FF" is tested at the means 88. If a satisfactory result is obtained, the selection oath is completely over and control passes in the "HSKPG" sequence. On the other hand, the diagnostic processing is performed in the means 89 before the control passes in the "HSKPG" order.

If it is not the test selection time but the selection time (means 89), control passes from the means 86 of Fig. 18A to the means 90, so that the digital satellite connection 14 has a selection message (Fig. 16). "1FFCOO"). The selection response message shown in FIG. 17 is then tested in the means 91, and if the digital satellite unit 13 does not require maintenance, the operation is transferred in the "HSKPG" order.

Multiple reward requests may be present in the selection response message. The J program in the digital satellite unit 13 determines that multiple remote digital satellite units 13 can be used, which coordinate these multiple simultaneous contents and require maintenance. Each remote digital satellite unit 13 has a number assigned to this unit, which is called a remote group number. Therefore, when the contents are interpreted, the digital satellite access device 14 sends a POLL ASSIGNED message (FIG. 16) to the first byte of " 7 " The next byte is the remote group number representing one of the possible remote digital satellite units 13. The remaining bytes are all zeros. The designed remote digital satellite unit will only respond to select dividend messages.

The digital satellite unit 13 processes the returned message and transmits this message to the digital satellite access point 14 for the next 12th frame time of the next superframe. More specifically, when the POLL ASSIGN message of FIG. 16 is processed continuously, the remote digital satellite unit 13 sends an acknowledgment message ExOOO. Where "X" is "1" when transmitted over span 0 and "2" when transmitted over span 1, which is in the second byte of the OK message shown in FIG. Appears by setting the SO and SI bits. This message is then processed in the means 93.

After the means 63 or in response to another shunt as shown in FIG. Since the "HSKPG" sequence begins, the ALL CHANNELS BUSY counter and timer are renewed in the means 94 and the memory 28 is tested in the means 95. A number of indicators and timers are set or cleared to a specific number in the means 96 and then the system prepares for a new interruption in the means 97. When this is complete, control passes back to the " IRQP " sequence and means 82 shown in FIG. 18A.

E. Basic Call Processing

The telephone switching system will now be described in response to telephone calls originating on one of the remote subscriber lines 12 and arriving on one of the remote subscriber lines 12. First, suppose that one subscriber in the telephone network, that is, a calling party, calls another subscriber, that is, a called party. Line 11 of the calling party is a "call" line (CALLING, or 'ING), and the line of the called party is a "call" (CALLED, or' ED) line.

The digital central switch contains memory information that identifies all telephone numbers and confirms whether they correspond to one of the local line 11 or the remote line 12. For the remote line 12, the memory includes a satellite line number SLN for uniquely identifying each remote line 12.

In the case of a "called" line with a remote line 12, the call handler sends a 5-byte incoming message as shown in FIG. This message identifies the satellite line number of the called line and the port number of the calling line. It also contains other information used to complete the call. If the message is properly received, the digital satellite connection tests the ground start (GST) signal in the TERMINATE message indicating the ground start state. Once the bit is set, the digital satellite access device 14 sends a ground start message, particularly the unique DSI STATUS message “90”, to the call processor 408.

On the other hand, the connection device 14 processes the incoming message and sends a CONNECT message shown in FIG. This message has the command value "2" and contains 6 bytes. The second byte contains the called satellite line number and the third byte contains the assigned channel number identifying the time slot on the span 0 and span 1 device to be used. This dividend is made by the digital satellite connection device 14. The fourth and fifth bytes contain the calling port number of the DCO sent to the DSI in the incoming message. When the digital telephone switching center 10 of FIG. 1 and FIG. 2 establishes a path | route, the ring line message shown in FIG. 9 is sent. The ring line message identifies the called satellite line number and includes ringing control and ringing type bytes. The ringing control byte checks for called and called frequencies and the ringing byte checks for normal, emergency, replay ring, return or stop ring operation.

When this sequence is completed, the digital satellite access unit 14 sends an incoming message to the remote digital satellite unit 13. This message is shown with the symbol "8" in FIG. This includes the ring code, satellite line number, assigned channel number, and span number received from the ring diagram message of FIG. When this message is transmitted, the message completion message " 71 " of FIG. 10 is transmitted back to the call processor 408 by the digital satellite connection device 14. As shown in FIG.

At this time, the called line 12 is ringed. When the subscriber answers the telephone, the remote digital satellite unit 13 detects the off-hook signal and stops ringing. In addition, since the "A" signal and the bit transition to the off-hook value, the digital switching center connects the call line to the allocated channel on the T / span through the corresponding time slot in the port group trunk, thereby handling the call. do.

If the calling party hangs up, the corresponding remote digital satellite unit 14 requires repairs. When the POLL ASSIGNED message for this digital satellite unit is received, the OK message shown in FIG. 17 is not answered. An ORIGINATE message with the sign "2" is sent to confirm the satellite line number. This includes the Disconnect (DS) bit, Send try fail (SF), Shareware update (PU), and Shareware identification (PI) bits. In response, the digital satellite interface 14 determines whether the line load controller is operating properly. If not, the digital satellite connection 14 sends a pre-control message as shown in FIG. 16 with a Disconnect (DS) bit set. If the line load controller is operating properly, the digital satellite interface 14 determines whether all useful channels on the span are busy. In some ways, the satellite line number (SLN) is stored in the queue during all channel calls and is carried out of the queue as the channel is released.

Once the channel is available and selected by the digital satellite connection 14, it sends an outgoing response message with the sign " 8 " shown in FIG. 16 back to the remote digital satellite unit 13. This message includes satellite line number, span number, and channel number. Digital satellite unit connection 14 also sends an outgoing message (FIG. 10) having the first byte " 5 " to call processor 408. FIG. This message includes the calling satellite line number, the assigned channel number, the delay count during all channel calls, and party identification. If the automatic test is performed, the operation at this time is changed to the automatic test sequence described later if the automatic test described later is performed. On the other hand, the digital telephone exchange station wants to establish a passage for the dial tone.

When the remote subscriber receives the dial tone, the subscriber starts to dial and transmit the dial number. These numbers are encoded in the "A" signaling bits transmitted over the port group trunk in the "A" bits of the corresponding channel. At this point, the digital switching center completes the call processing by transferring the call to the called line. If the satellite line number requires a response supervision, the digital telephone exchange will send the LINE CONTROL message shown in FIG. 9 with the first byte value " 23 " which is different from the satellite line number. On the other hand, the process is complete and the call is processed.

If the remote subscriber line 12 is an originating line or an incoming line, the remote subscriber line must be disconnected from the call handler to complete the telephone call. In normal call processing, the call handler indicates whether a given telephone line is idle. When this determination is made and the included line is a remote subscriber line 12, the digital switching center transmits the unconnected message shown in FIG. 9 with the first byte " 12 " and the satellite line number. 14) to send. The DISCONNECT message shown in FIG. 9 is transmitted in this particular case, but the lines may be disconnected by a CHANNEL DISCONNECT and LINE CONTROL message. However, if there is a normal disconnected message, the digital satellite access device receives this message and determines whether channel allocation is sent to the remote digital satellite unit 13. If not, the digital satellite connection 14 transmits a line control message (signal " 9 ") with a set of Disconnect (DS) bits. If a channel allocation is sent, then the digital satellite connection 14 sends a line control message with a set of Remote line control disconnect (RD) and sets a single party line (SP) bit or Cree it. When channel allocation is sent to the remote digital satellite unit 13, the line control message sends a set of Disconnect (DS) bits and sets or clears a single common line bit.

Assuming that the remote digital satellite unit receives the indicated disconnected message by receiving an acknowledgment message, the digital satellite interface 14 sends a channel disconnected signal to the call processor. This message shown in FIG. 10 confirms the hypocrisy line number and the assigned channel number. Digital satellite access also makes a channel useful for subsequent calls. When the satellite line number is on-hook, the next processing by the digital satellite connection 14 is terminated. However, if the remote subscriber is still off-hook, the remote digital satellite unit 13 sends a particular outgoing message with a set of disconnected (DS) bits to operate as a disconnected message. At this time, the digital satellite access device 14 sends the RELEASE message shown in FIG. 10 to the call processor, and the call processor updates this control information by indicating that the satellite line number is now idle. This allows the disconnection process to finish completely.

F. Maintenance Processors-Digital Satellite Access Channels

The communication path between the digital telephone switchboard 10 and the digital satellite access device 14 shown in FIG. 4 for maintenance is provided with an MBI buffer 18 connected to a maintenance processor (MP) 300; And a front end circuit 30 for interconnecting the MBI buffer 18 and the bus bar 26. MBI buffer 18 is shown in schematic in FIG. 18. As with the call processor bus interface (CPI) 17, the MBI buffer 18 provides a buffered connection between the maintenance payer 300 and the digital satellite connection 14. This passage transfers the front end information between the digital satellite access device 14 and the maintenance processor 300 and loads the program from the maintenance processor 300 into the memory 28 of FIG. Each MBI buffer 18 may be connected to 30 digital satellite connectors 14. However, like the call processor bus bar connection circuit 17, the circuit operates distinctly in operation.

MBI buffer 18 has two operating modes. When the MBI buffer 18 is not used, a selection operation occurs. In FIG. 19, the address generator 1810 continuously generates an address corresponding to the front end circuit 30 in each digital satellite junction. The multiplexer 1811 operates in this select operation mode to couple the signal from the address generator 18101 to the front end circuit 30 via the driver 1812. If the corresponding digital satellite connection wants to send a message to the maintenance fold 300, it will respond to a marker signal that is detected to render the address generator 1810 inoperable until the interruption is repaired.

When the maintenance processor 300 wants to send information to the diagnostic circuit 30, it is sent to the diagnostic circuit 30 via the receiver 1813, the mulplexer 1815, the mulplexer 1811, and the driver 1812. Transmit signals passing by first.

When the digital satellite connection 14 wishes to send a message to the maintenance processor, it operates the receiver 1816 and the driver 1817, so that the message normally passes directly to the maintenance processor 300. However, if MBI buffer 18 challenges the selection operation when digital satellite interface 14 attempts to reach maintenance processor 300, receiver 1818 will latch and control the information until the selection is complete. By coupling the information into the circuit 1918, the selection operation is terminated and the driver 1820 transfers the information back through the receiver 1816 and the driver 1817.

Referring to FIG. 20, the message from the maintenance processor 300 to the digital satellite access device 14 is transmitted via the control register 3011, the address decoder 3012, and the receiver 3010 in the front end circuit 30. Pass to input FIFO 3013. Address decoder 3012 decodes the address. In other words, if this corresponds to its Digital Satellite Accessory (DSI) address, subsequent messages are conveyed to the input FIFO 3013 via the program connection adapter 3014 to the memory 28 of FIG. When processor 27 wants to send a message to maintenance processor 300, it passes data into output FIFO 3017 through data buffer 3015 and program connection adapter 3014. In this case, the output message may be transferred to the maintenance buffer connecting device 18 through the bus driver 3018.

Input and output FIFOs 3013 and 3017 operate in response to signals from FIFO control units 3019 and 3020, respectively. The diagnostic circuit 30 begins to operate via the interruption stop control circuit 3021, which produces a control signal through the bus driver 3022. Multiple control signals from the repair busbar connection buffer 18 are received by the receiver 2023. The program connection adapter 3016 is connected to the diagnostic circuit 30 and the control portion of the processor 27.

The diagnostic circuit 30 performs multiple functions and operates in multiple mode states. This transfers the message from the processor 27 through the maintenance processor 300 and sends the message back from the maintenance processor 300 to the processor 27. This is indicated in processor 27 or processor 300 when an input message becomes available to each processor or when an output message is sent from each processor. In addition, the diagnostic circuit 30 may transfer the program to the memory 28, in particular, the program RAM 2811 and the operation RAM 2812 in FIG. 8, or the processor 27 when an emergency or normal alarm condition exists. Or when the memory 28 is not connected, it sends a signal to the maintenance processor 300. When the maintenance processor begins to transfer information to the memory 28, a signal is sent to the processor 27 to perform a round trip test and examine the error test. Finally, the diagnostic circuit 30 stops the maintenance processor 300 and provides an interruption mask.

The message transfer function is important in the present invention and will be described with reference to FIG. 21 related to FIG. 19 and FIG. Referring first to FIG. 21A, the message occupies the MBI buffer 18 and the maintenance processor 300 by occupying the appropriate diagnostic circuit 30 in one of the digital satellite connection units connected to the MBI buffer 18. ) Is transferred to the digital satellite access device 14 from. This is done in the means 21A by addressing the MBI buffer 18 in the means 501 and occupying the MBI buffer 18. This is done when the address comparator 1814 in FIG. 19 decodes the address in the receiver 1813 corresponding to the MBI buffer 18. The buffer 18 may operate the receiver to continuously couple signals to the diagnostic circuit 30 through the mulplexer 1815, the mulplexer 1811, and the driver 1812. Next, in means 502, the maintenance processor 300 addresses the machining position in the MBI buffer 18 corresponding to the receiver 1813. This allows the continuous data to be transferred to the diagnostic circuit 30. Subsequently, the maintenance processor 300 addresses one digital satellite connection device in order to occupy it (means 503).

When a particular digital satellite interface 14 is occupied, the maintenance processor 300 decrypts the diagnostic status register 3024 shown in FIGS. 20 and 12A. If the DSI OUT OF SERVICE bit is set, the means 505 branches to the means 506 and the maintenance processor classifies the repair message. If the message cannot be conveyed at this time, branching to means 507, maintenance processor 300 addresses this buffer again to release the MBI buffer. We will now discuss the selection behavior.

Assuming the occupied digital satellite junction 14 is in the maintenance state, the means 505 means 508 to test bit 0 of the status register 3024, i.e., the INPUT FIFO BUSY bit. Branch to. If not in a call, means 508 branches to means 509 so that the maintenance processor clears the READ INPUT FIFO bit in diagnostic control register 3011 and then digitally in means 510 and 511. Send a multi-byte message to the satellite interface 14. Once all bytes have been sent, the means 511 branches to the means 512 so that the maintenance processor 300 can set the decryption input FIFO bits in the control register 3011, and the means 507, the MBI buffer 18 Release it.

The process for transferring a message from the digital satellite junction 14 to the maintenance processor 300 is performed by its digital satellite junction transferring the message into the output FIFO 3017 of FIG. 20 and shown in FIG. When the READ OUTPUT FIFO bit is set in the status register 3024, it begins at the means 513 of FIG. 21B. This state change causes the maintenance processor 300 to stop.

To repair this interruption, the maintenance processor addresses this buffer to occupy the MBI buffer 18 in the means 514 and then addresses the machining position in the means 515 to communicate with the diagnostic circuit 30. . These means correspond to means 502 and 503. The processor then addresses the next digital satellite connection to investigate the maintenance interruption at the means 516. If the decryption output FIFO bit in the corresponding diagnostic status register 3024 is set (means 517), one message byte is returned from the output FIFO 3017 at the means 518. Incidental bytes continue to be returned until the means 509 the maintenance processor 300 knows that the decryption output FIFO bit in the diagnostic status register 3024 is cleared. If this happens, the means 509 branches back to the means 507 to release the MBI buffer 18.

If the decryption output FIFO bit is not set in the means 517, then the control state goes to the means 520 of FIG. 21C. The maintenance processor 300 tests the DSI non-maintenance bits in the diagnostic status register 3024 shown in FIGS. 12A and 20. Assuming that the digital satellite connection is connected and in the maintenance state, the means 520 may return to the program memory (means 529) in the case where the RELOAD PROGRAMS bit is set and returned to the means 507 of FIG. 21A. Branches to means 521 to reload 2811. If the reload program bit is not set, maintenance processor 300 determines whether all digital satellite connections 14 have been examined (means 523). If so, the refurbishment processor is typed into the full-length typewriter 305 of FIG. 2 (means 524). If no irradiation has occurred, the control state goes back to means 516 in FIG. 21B.

If the identified digital satellite junction is in an unmaintained state, the control state indicates that the junction 14 indicates an unmaintained state at the means 526 and to operate the maintenance processor 300 to type a message at the means 524. Pass from means 520 to means 525. If this indication occurs, the control state goes to the means 523.

G. Auto Remote Line Test

In order to understand the operation and the test procedure, the automatic test circuit 20 will first be described, followed by the maintenance and management circuit 79 and remote digital satellite unit 13 of FIG. Basically, automatic testing is initiated when a message is sent from the maintenance processor 300 to the digital satellite connection so that the test call is scheduled and a test call is made. The list corresponding to the test call order is stored in the DSI memory 28. If this happens, the digital satellite connection 14 determines the usefulness of the automatic test line and begins sending phone calls to the automatic test circuit 20 through the call processor 408. After the call path is established, the automatic test circuit in the remote digital satellite unit 13 in which the automatic test circuit 20 is designed performs a simple three part test. First, the automatic test circuit 20 of FIG. 22 detects this tone as a remote voice automatic test circuit through the port group trunk as normal voice data, which is sent back to the automatic test circuit 20 and the dial pulse. Send. The automatic test circuit compares the timbre and dial pulses against frequency and timing criteria. This test passes, and the digital satellite connection 14 receives the call and sends a TEST COMPLETE message to the maintenance processor. However, if the call is not made continuously in series, the digital satellite interface begins to set its own shear means using successive test calls to isolate the fault without including the maintenance processor 300.

As shown in FIG. 2, the automatic test circuit 20 is connected to the relay line pot circuit in one pot group unit 402. As shown in FIG. In particular, as shown in FIG. 22D, the automatic test control circuit receives a DAA signal from a port group control (PGC) that indicates a quick detection watch bit that carries hook status information. . When the automatic test sequence is initiated, the digital switching center sets the path of the FASTSENSE bit, which is transferred from the remote line through the call handling system to the automatic test circuit 20 as a DAA signal. The ADS (−) pulse is a potent strobe pulse corresponding to the sample time slot assigned to a particular position of circuit 20 within the potent group unit 402.

The port group unit 402 includes a multiplexer and a demultiplexer for voice data and surveillance data. The DBA signal to the timbre receiver of FIG. 22B is the speech data recovered from the speech data demultiplexer. The DBM, DBC, and ADD signals to the frequency detector of FIG. 22C are timing signals recovered from the port group unit 402. The DBM signal in this particular embodiment is an 8 KHz sampling signal corresponding to the ratio at which the audible signal is sampled and converted to digital form by strobe the CODEC circuit in the line circuit. The DBC signal is a 128KHz base clock signal for the CODEC. CODEC circuits are separated into even and odd groups. Odd (ODD) signals select odd or even groups. The tone generator 22A generates an AEA signal corresponding to the digital form of voice data recovered from the CODEC in the local line circuit. In other words, this voice data is conveyed onto the port group trunk via the voice data mulletplexer. The frequency detector of FIG. 22C generates an ADV signal corresponding to SLOW SENSE information. In other words, this indicates that the automatic test circuit 20 exists. The DAC signal carries FAST SENSE monitoring information that signals the success or failure of a test within an automatic test circuit.

i. Automatic test circuit (20)

The DAA signal is strobe periodically to the latch circuit 2010 in FIG. 22d by the corresponding ADSC (-) or potent strobe pulse. When the signaling bit above the span indicates that the remote unit B is selected (ie off hooked) and the call is complete with the autotest circuit 20, the latch circuit 2010 is applied to the AND gate 2011 off. Set to generate an OfF-HOOK signal. The test flip-flop circuit 2012 has an internal ON generated by the OR gate 2013 in FIG. 22E when the power circuit 2014 is operated and an on-hook signal is generated from a set of counters 2015. -Cleared by an ON-HOOK signal. This is an internal status signal.

Referring to FIG. 22D, when the test flip-flop call is cleared, this also causes the status counter 2016 to clear and the decryptor 2017 to operate to issue a RESET signal. The reset signal operates the OR gate 2018 to cause the AND gate 2011 to operate. When the flip-flop circuit 2010 is set, the AND gate 2011 activates the AND gate 2019 to operate when no dial pulse detection (DP DETECT) signal is coming from the decoder 2107. As a result, AND gate 2019 operates NOR gate 2020 to cause counties 2022 and 2023 to begin counting. Since no reset counter (COUNTER) signal is issued, the parallel load input to the counter 2022 is not activated. The counter 2023 in series with the counter 2022 does not operate while the feed (CO) output of the counter 2022 is not coming out. Four millisecond pins are applied to the clock inputs of the counters 2022 and 2023.

When the latch circuit 2010 is set for 16 milliseconds, the output counter 2022 is clocked to set the test flip-flop circuit 2012. When the internal on-hook signal is activated, the inverted 4MS pulse from inverter 2024 causes AND gate 2025 to operate. However, during the test, since the on-hook signal does not come out, the most important cree signal is eliminated. When the test flip-flop circuit 2012 is set, the cree input to the state counter 2016 is removed and the input is responsive to the output of the state counter 2016 such that a continuous 4MS pulse advances the state counter 2016. The multiplexer 2026 is operated to make a selection.

During this first state, the reset signal from decoder 2017 is coupled to the dial pulse decoder of Figure 22e and to the frequency decoder of Figure 22c. Specifically, the reset signal operates the OR gates 2027 and 2028 in FIG. 22C, preventing the OR gate 2029 from operating and the counter 2030 starting counting from a preset value with an 8 millisecond pulse ratio. Let's do it. This count continues until a transfer (RCO) signal is generated, which defines a 97 millisecond test window. Referring to FIG. 22E, the reset signal clears the DP OK (flip) -flop circuit 2031.

The next 4MS pulse advances the state counter 2016, so the decoder 2017 generates an RSETFLG signal corresponding to the new state. Since the output from multiplexer 2026 continues to come out, the state counter 2016 advances to the next 4 MS pulse. During this state, the RSETFLG signal clears the frequency OK flip flop circuit 2032 in the frequency decoder of FIG. 22C.

When the count 2016 in FIG. 22d advances again, the decoder 2017 generates a RESET COUNTER signal and a corresponding state. The reset counter signal clears the counters 2022 and 2023 so that they start the next operation. The reset counter signal also passes through the multiplexer 2026 to operate the next 4 MS pulses to advance the state counter 2016 and set the SEND TONE state.

The transfer tone signal from the decoder 2017 operates the OR gate 2018 so that the AND gate 2011 is reactivated so that the counter 2022 advances a continuous 4MS pull. Since the detection tone and the DP detection signal do not come out, the OR gate 2034 is not operated and the counter 2035 is advanced in response to the even delay clock signal from the flip-flop circuit 2036.

Flip flop circuit 2036 responds to a signal derived from the DBM, DBC, and ADD signals. Specifically, buffer 2037 in FIG. 22C buffers these signals to produce sample, CCLOCK, and odd signals, respectively. Referring back to FIG. 22A, inverter 2038 produces an even signal applied to the D input of flip flop circuit 2036 and generates a fast CCLOCK pulse that clocks the flip flop 2036 at the beginning of each even period. . If this happens, the flip flop circuit 2036 clocks the counter 2035 to make an address.

At the beginning of each successive even period, additional addresses will occur sequentially.

Consecutive addresses from counter 2035 and cascade counter 2040 address contiguous locations in decryption memory 2041 that make a contiguous bit sequence corresponding to samples of the processed timbre. The samples are then clocked in response to the simultaneous generation of the even delay and CCLOCK signal sensed by the AND gate 2042 and transitioned to a series of forms under the control states of the CCLOCK, odd and sample signals applied to the NAND gate 2043. . A series of bits from memory 2041 is applied to the port group trunk as an AEA signal by AND gate 2044 and inversion driver 2045, which are operated for even bit time.

This tone is sent for a 1-2 period set by the counters 2022 and 2023. At the end of the 1-2 period, the CARRY output from the counter 2023 activates the selected input to the multiplexer 2026, so that the next 4 MS pulses will cause the status counter 2016 to enter the DETECT TONE state. Let's move forward. The counter 2016 is not operated again by the multiplexer 2026 when the frequency OK signal does not come from the flip-flop circuit 2032 in the frequency detector of FIG. The detection timbre signal from the decoder 2017 operates the OR gate 2034 and renders the timbre generator of FIG. 22a inoperative.

The digital representation of the timbre from the remote signal line is received as a DBA signal in a serial-to-parallel converter 2050 in the timbre receiver of FIG. 22B. These signals are continuously transitioned into the converter 2050 when the even delay, inverted CCLOCK, and even signals sensed by the AND gate 2051 respectively occur. Each time an odd (ODD) signal is emitted, the converter 2050 includes an overall digital representation of the timbre and the odd signal clocks this representation into the latch circuit 2052, so that the latched representation is one input of the comparator 2053. Is transferred to. Each odd signal also clocks an address counter 2054. However, this counter does not advance until a similarity is found. Therefore, comparator 2053 compares the identity between the first word and memory word from memory (ROM) 2055. The ROM 2055 is the same as the ROM 2041 in FIG. 22A. Once identity is established, the address counter 2054 begins to advance. If the received tone and the tone from the ROM are not in phase, the address counter 2054 is reloaded to the initial value through the OR gate 2056 because the comparison test fails. If the tones are in phase, the address counter 2054 continues to advance. The AND gate 2058 may or may not be selectively operated relative to the least significant bit from the counter 2054. After receiving a predetermined number of similarities, the counter 2057 produces a feed (RCO) output which is a TONE RECD signal. This prevents the AND gate 2058 from operating and another count.

In addition, the two most prevalent bits from the latch circuit 2052 include display information indicating zero crossing or tone frequency. These bits are fed through an AND gate 2059 which emits a SIGN signal when a positive indication is received. This display signal is sent to the counter 2060 in the frequency detector of FIG. 22C. The display signal changes at twice the tone frequency. The counter 2060 advances until the end of the 96 ms test window defined by the counter 2030, and the counter 2060 generates a transfer that activates the threshold device 2061 and disables the counter 2060. Let's do it. Typically two comparators 2062 and 2063 operate AND gate 2064 at the end of the test window, so the transfer output signal from the counter sets the frequency acknowledgment flip-flop circuit 2032.

Also, the tone receiving signal from the counter 2057 in FIG. 22B operates the OR gate 2065 in FIG. 22C. This operates the buffer 2037 to activate the DAC line providing a quick sense supervision signal to the pot accumulation area for the circuit 20.

The frequency OK signal is coupled back to the automatic test circuit in FIG. 22d, so the multiplexer 2026 causes the state counter 2016 to advance to create a DP detection (DECT) state. Here an input dial pulse is detected. If this happens, the multiplexer 2026 prevents the counter 2016 from operating again because there is no TSTCPLTE signal to support the end of the test. The DP detection signal is coupled to the tone generator of Fig. 22A and the dial pulse detector of Fig. 22E. Referring first to FIG. 22A, the DP detection signal operates the OR gate 2034 and causes the tone generator not to operate.

Referring to FIG. 22E, when the DP detection signal becomes strong, the AND gate 2070 is disabled and the counter 2105 is operated. In addition, the DP detection signal causes the Begin dial pulse timer (BEG DP TMR) flip-flop circuit 2071 to be clocked by the output from the counter 2015. This also causes the AND gate 2072 to generate a TSTCPLTE (test complete) signal when the DP test signal from the AND gate 2073 in the automatic test control circuit of FIG. 22d becomes strong later.

The off-hook signal, which represents the dial tone from the remote line, becomes strong during the dial pulse "break" tone period and not during the dial pulse "form" period. When the off hook signal is strong, the cascade counter 2015 may not advance, but may be advanced at a 4 ms pulse ratio when the off hook signal is not strong. Thus, counter 2015 measures the successive dial pulse "form" time. After the "build" signal ends for 16 ms, the counter 2015 clocks the flip flop circuit 2017. The final BEG DP TMR signal then causes the counters 2022 and 2023 to start moving forward. After 176 ms or 192 ms after the first dial pulse arrives, AND gate 2073 issues a dial pulse test (DP TEST) signal. This corresponds to the nominal period of two dial pulses.

When the DP TEST test signal becomes strong, the flip-flop circuit 2031 is irradiated. Comparator 2074 causes all "form" time of the dial pulses to be below the maximum. Comparator 2075 causes this time to be above the minimum. Therefore, if the AND gate 2076 is activated when the DP TEST signal is strong, the TEST CPLTE (test complete) signal from the AND gate 2082 becomes strong. Flip-flop circuit 2031 sets an indication that the received dial pulse is within tolerance.

The TSTCPLTE signal is combined back into the automatic test control circuit of FIG. 22d, and a dial pulse acknowledgment (DP OK) signal is received by the frequency detector of FIG. Referring first to FIG. 22C, the DP OK signal operates the OR gate 2065 such that the DAC signal representing the quick sense information bit conveys an indication of the success or failure of the port group control and the port group state. In the automatic test control circuit of FIG. 22, the TSTCPLTE signal activates the selected input of the multiplexer 2026 such that the next 4 MS pulses advance the state counter 2016 to the final state.

The 4MS and 8MS pulses are made by decoding even signals through the counters 2080 and 2081 and the decryption circuit 2082.

ii. Remote auto test circuit

Referring to FIGS. 23 and 23A-23F, the decoder and timing generator 7810 generates a start automatic test (COMAT) signal when an autotest command message is sent to the remote digital satellite unit. Referring to FIG. 23A, the COMAT signal is applied to an initial automatic test flip-flop circuit 7111 set in response to a 500 KHz clock signal to emit a Start auto test (SAT) signal. This SAT signal is coupled to the AND gate 7912, status register 7818, AND gate 7919, and OR gate 7828 of FIG. 23A. This operates counter 7915 in the timing circuit of FIG. 23B and various elements in the detector circuit of FIG. 23C.

Referring to FIG. 23A, the AND gate 7912 is operative to emit an Auto test reset (ATRR) signal coupled to the timing circuit of FIG. 23B and coupled to the alarm control and receiver reset circuit of FIG. 23E. do. The ATRR signal operates the OR gate 7913 in FIG. 23B to clear a test function timer that includes a C16 flip-flop circuit 7714 and a counter 7727. This also makes the RECRST signal strong as long as the NOR gate 7916 controls the flip-flop circuit 7917 so that the RST5S reset signal is not strong. When the REC RST signal is intensified, the circuit 7910 in FIG. 23 transitions the COMAT signal to a level that is not strong. However, the flip-flop circuit 7911 remains set because the ENDAT signal from the state transition register is not strong.

The SAT signal operates the counter 7918 in FIG. 23A. In addition, the NOR gate 7920 operates the AND gate 7919, so that the SAT signal is provided with an OR gate 7921 which can be operated by an enable tone detect (ETD) signal generated during a manual test. In operation, the ENABLE TONE DETECT flip-flop 7722 is set to generate a tone detect (TNDET) control signal.

The flip-flop circuit 7822, TNDET signal from, is coupled to the timing circuit of FIG. 23B, the detector circuit of FIG. 23C, and the dial pulse detector circuit of FIG. 23D. In FIG. 23B, the TNDET signal operates the AND gate 7924 to pass a clock pulse from the split JK flip-flop 7825 to the testable timer counter 7927 through the OR gate 7926 to the clock input. Activate OR gate 7723. This OR gate 7913 also activates an OR gate 7333 that advances the counter 7927. In FIG. 23D, the TNDET signal operates the gate 7932 to generate a TONE signal that is coupled to the detector circuit of FIG. 23C when the input tone from the automatic test circuit 20 is detected.

The SAT signal from the flip-flop circuit 7911 activates the OR gate 7928, which activates the relay coil 7927C in the test relay. When the relay coil is activated, two open relay contacts are connected to one side of the hybrid circuit to the TT1 and TR1 test lines of the test access relay of the combined line circuit. This test access relay disconnects the subscriber from the line circuit and causes the TST relay 7927 to construct the test circuit of FIG. OR gate 7928 activates another OR gate 7930 and activates coil 7131C of PL relay. The PL relay contacts 7191A of FIG. 23D are contacted so as to completely form a passage through the TST relay from the hybrid circuit of the automatic test circuit, and TT1 and TR1 are connected to the test access relay.

During this first state, the input signal is monitored. When the timbre is received, the timbre is combined via hybrid circuit 7930 and timbre detector circuit 7131. Once the timbre is detected, the AND gate 7932, operated by the TNDET signal, operates to produce a TONE signal that is coupled back to the detector circuit of FIG.

After a period defined by the counter 7927, the flip-flop circuit 7714 is set to generate a C16 signal. This generates an AND (793) signal in FIG. 23C to generate an event advance (EAV) signal and to set the tone detection flip-flop circuit 7937 to generate a tone detct output (TDO) signal. Operate. If this TDO signal is strong, the AND gates 7919-7921 and AND gate 7936 are regulated so that the flip-flop circuit 7722 sets the state transition register 7918 so that the EAV signal sets the first stage on the next clock change. It can be creeped while adjusting. Referring to FIG. 23C, the SAT signal causes the flip-flop circuit 7936 to be bistable in the set state when the tone transmission from the automatic test circuit 20 is received at the digital telephone exchange station 10. FIG. If this happens, the ADV 1 signal is generated. This ADV 1 signal clocks " 1 " into the first stage of state transition register 7918 to end the first or timbre means and enter the timbre generation state indicated by the active timbre transfer (ETS) signal. OR gates 7779 and 7938 are operated. Also, the ADV signal from the OR gate 7937 in FIG. 23A clears the counter 7779 and flip-flop circuit 7714 in FIG. 23B.

This transitions the C16 signal into a non-strong state, preventing the AND gate 7734 from operating to clear the time detection flip-flop circuit 7735 and the flip-flop circuit 7936. Clearing the flip-flop circuit 7714 also transitions the EAV signal in FIG. 23C into a non-strong state, adjusting the state transition register 7918 to shift its content in response to a clock wall.

In the tone generation state, the tone circuit of FIG. 23D generates a return tone coupled to the automatic test circuit 20 in FIG. 22 to perform the second test step. Specifically, the ETS signal operates the OR gate 7939 in FIG. 23C, causing the ENABLE TONE SEND flip-flop circuit 7940 to be set to operate the ST relay coil 7794C. This closes the ST 1 contact 7801A in FIG. 23D and allows the timbre from the buffered oscillator circuit 7802 to couple to the test access relay through the PL contact 7141A and the TST contacts 7927A and 7929B. In addition, when the SAT signals are generated simultaneously and the flip-flop circuit 7940 is set, the AND gate 7794 outputs an Auto test tone started (ATSTE) signal for operating the OR gate 7913 in FIG. 23A. In operation, a test function timer including a counter 7779 and a flip-flop circuit 7714 controls the period during which the timbre is transferred.

At the end of the predetermined period, the flip-flop circuit 7714 is set and the ENABLE TONE SEND flip-flop circuit 7940 is adjusted to cree through the OR gate 7944 and the ST relay coil 7794C is disabled. The C16 signal also disables the AND gate 7945 that sets the flip-flop circuit 7946 to generate the ADV 2 signal. The ADV 2 signal advances the test function transition register 7918 in FIG. 23A to a dial pulse generation state (DP GENERATING) and clears the test function timer through the final ADV signal from the OR gate 7779. This adjusts the circuit of FIG. 23 to finish the second test step and make the final dial pulsing step.

In this state, the first dial pulsing (STDP) signal is sent from the state transition register 7918 to the dial pulse circuit of FIG. 23f. The AND gate 7477 in FIG. 23F is operated by ESDP signals from other furnaces in the maintenance and management unit 79. The flop-flop circuit 7798 is therefore set and adjusted to generate an active dial pulsing (EDP) signal. This EDP system signal has a counter 7827 that is cleared, thereby activating the AND gate 7945 that controls the flip-flop circuit 7950, so that the decoder 7701 operates the AND gate 7945. This EDP signal also operates the AND gate 7172 in FIG. 23B. When the test function timer 7927 advances, its signals are fed to the decoder 7171 in FIG. 23F. When the counter 7927 reaches a "6" count, the decoder is adjusted to bistable flip-flop circuit 7950. When the counter 7927 reaches the "9" count, the AND gate 7172 loads the counter 7927 to clear this count. The clock frequency for the flip-flop circuit 7950 is selected such that the flip-flop circuit acts as a breakdown-forming flip-flop circuit that produces a calibration timing dial pulse. AND gate 7955 generates a dial pulse count (DPC) signal at a calibration frequency. Each time a 64DP signal comes out, this causes the PL relay 7913C to fail to advance the state transition register 7918 in FIG. 23A and break the DC path from the line circuit. Therefore, a first breakdown pulse occurs in the dial pulse train. After 60 milliseconds, the counter 7927 reaches 6 counts, so the decoder 7171 in FIG. 23F is adjusted to reset the formation-break flip-flop circuit 7950. If this happens, the formation-break flip-flop circuit 7950 is cleared and the PL relay coil 7191C in FIG. 23A is reactivated, so that the relay is closed again to form a break time. After 30 milliseconds, the decoder 7151 in FIG. 23F reaches 9 counts. This resets the flip-flop circuit 7950 and adjusts the AND gate 7945 by resetting the test function timer counter 7927 and starting the next breakdown period. This indicates that the second dial pulse begins and the first dial pulse ends and causes the transition register 7918 to advance to the second DP state. This same order occurs again. That is, the PL relay does not operate for a breakdown period of 60 milliseconds following the 30 millisecond formation period. At the end of this time, if the flip-flop circuit 7950 is set, the transition register 7019 advances to generate a dial pulse end (END DP) signal that causes another dial pulse to be sent. Following this dial pulse, the transition register generates an automatic test end signal (ENDAT) that adjusts the flip-flop circuit 7735 and the EDP flip-flop circuit 7798 of FIG. 23f to be cleared. This completes the sequence in the circuit of FIG.

Also shown in FIG. 23C is a tone failure flip-flop circuit 7970. FIG. If no timbre is detected at the end of the detection time, AND gate 771 adjusts to set flip-flop circuit 7970 to generate a TFO signal. The TFO signal clears the flip-flop circuit 7722 in FIG. 23A and causes the AND gate 7722 to operate, thus creating an MTFL signal that supports that the gusing failure to detect the tone during manual testing (ie, the SAT signal). Does not come out).

As described above, the timing circuit of FIG. 23B includes a five second timer that includes a counter 7915 and a flip-flop circuit 7780. As long as the SAT signal comes out, the counter advances. If the test does not end completely at the end of the 5 second period, the timer in OR in FIG. 23A generates an RST 5S signal that is activated by circuit 79 in FIG. The gate 7901 is operated. This RST 5S signal presets the flip-flop circuit 7917 in FIG. 23E.

H. Automatic Test Operation

By understanding the network within the automatic test circuit 20 and the maintenance and management circuit 79, a number of communication methods that occur during the automatic test can be described.

i. Complement handler behavior

As described above, the maintenance processor 300 starts an automatic test operation. 24 shows a maintenance processor 300 having a number of associated control modules (ie, programs). There are many other modules, but they are not described because they are not related to the present invention. The MBIIM, SYNCMM, LIM, DIAGC, FLD, and DIAGPR modules are all modules used in conventional digital telephone exchanges.

Multiple modules can be transfer controlled to a DSIFLD module. To start the automatic test, the EXEC module is located as a calling module. The DSIFLD module transitions to the DSIMO module, which determines if the EXEC module is a calling module, establishes a path to the digital satellite interface, and sends an automatic test message to the digital satellite interface. This should use the DSICOM module. The message may or may not be typed on the whole body typewriter 305 in FIG. 2 by the DSIMSG module as a result of this order, depending on the parameters set in the DSITMO module.

After the selected period, the digital satellite interface 14 sends a message to the maintenance processor indicating that the automatic test has been completed, which creates an interruption request. When the DSIHND module needs to print through the DSIFLD module, the DSIHND module changes its behavior to a DSICAL module called the DSIPR module. The DSIAT module checks the check-in of the calibration DSI. That is, in the case where the calibration DSI does not go through, a number of diagnostics are provided. The DSIPR module decrypts the input message, raises an alarm if necessary, and prints the appropriate message. This may then be transferred to the DSIOOS module to allow the digital satellite access device to complete maintenance before using the DSIMSG module to print a message on the operator panel.

FIG. 25 is a basic flow chart showing the maintenance processor's actions in response to information transfer between digital satellite access devices, continuous control and monitoring of automated tests, and automated tests. However, this emphasized the automatic test call arrangement process. 26 through 29 are flow charts showing the modules shown in detail in FIG. 24 used during this process by the processor 27. FIG.

Referring first to the means 500 in FIG. 25A, the maintenance processor examines the digital satellite connection status register to determine if an automatic test can be initiated. If the digital satellite connection is in a call, the means 501 branches to the means 502 and the operation transitions to a stationary test in the means 503. If a stop is detected, the means 503 transitions the operation back to the means 500 so that the test can be rescheduled. If a stop occurs, the means 503 branches to the means 504 to start a fault diagnosis.

If the identified digital satellite access device is not in a call, the maintenance processor 300 starts an automatic test and resets the identified digital satellite access device in the means 505 for resetting the timer in the maintenance processor used in the means 503. Send a message.

Means 500-505 are shown in more detail in FIGS. 26-29. FIG. 26 is a distribution diagram showing details of the DSIFLD module. As mentioned above, this module first determines the calling module. Specifically, means 600 determines whether the DSIHND module calls it, means 601 determines whether the busbar diagnostic module calls it, and means 602 determines whether it is called in response to an even odd error. Decide If the EXEC module calling it fails to start an automatic test and these tests do not produce any positive results, control passes to the means 603 for the maintenance processor to determine whether the repair bus is used. When this happens, nothing further happens. Otherwise, the mother bus is set to the busy state at the means 604 and the IDSTMD module is called into the means 605 to start an automatic test. Once the DSITMO module has been processed, control is invoked into the means 605 to cause the DSIFLD module in FIG. 26 to begin an automatic test. Once the DSITMO module has been processed, control returns to the DSIFLD module in FIG. 26 so that means 606 no longer interrupts the intervention, releases the MBI buffer 18, and takes any other appropriate action before completing the task completely. Processing is performed.

27 is a distribution diagram showing the details of the DSITMO module. This module can be used for multiple times in some cases. During the first time (ie, while performing the function of the means 500 in FIG. 25), the means 610 clears the FIRST TIME indicator within the means 611 and returns to the means 612. The branching is performed to set the counter to the maximum number corresponding to the plurality of digital satellite connection devices connected to the MBI buffer 18 shown in FIG. The means 613 tests the first number to determine if there is a corresponding digital satellite connection. If this device is not present, the means 614 and 615 cause each of the overhead connections to be selected in sequence. If the select action is not taken successfully, the DSITMO module finishes its action and returns to its calling normal procedure. However, if a digital satellite access device corresponding to the counter number is found, control transfers to means 616 where the address for the digital satellite access device is stored in the DSIUDT register. Control then transfers to the DSIEQ sequence shown in Figure 27b, which starts the automatic test.

If the DSITMO module is called after the first time, the sequence is determined by a number of bus stops (e.g., FIG. 25), as the means 501 detects that the digital satellite connection is busy or after continuous failure. Branches in the starting order in the means 620 for operating the stop). Suppose that the digital satellite access device examines a maintenance processor (in means 621) that determines whether manual testing is required in means 622. This causes the means 623 and 624 to be tested.

This particular invention relates to an automatic test that is initiated automatically, wherein means 622 are transferred to means 625 to determine whether the final digital satellite connection is interrogated. The means 626 then clears the DSIUDT register. On the other hand, the DSIUDT register is augmented to the point of the next digital satellite junction to be examined within the means 627. Then in either of these cases, control transfers to the DSIEQ order in Figure 27b.

Referring to FIG. 27B, the maintenance processor is again tested to determine if the call processing system is equipped with a digital satellite connection designed in the means 630. FIG. If not, the DSICIN indicator is cleared at stage 631 and the bus stop timer is disabled at the means 632. If the system is equipped with a corresponding digital satellite access device, whether the "repair" test in the means 633 is branched back to the means 631 and 632 or the means 634 to recover the DSI number from the DSIUDT register. Determine. The maintenance processor 300 then uses the means 635 to call the DSICOM module shown in FIG. 28 to gain access to the appropriate digital satellite connection. Assuming that the DSICOM module operates properly, no error occurs, so the means 636 branches to the means 637. At this time, the automatic test command, i.e., "B8FFO180" in hexadecimal form in this particular embodiment, is sent to the input FIFO 3017 in the diagnostic circuit 30. At this time, in means 638, the maintenance processor 300 sets the DSI CN marker to indicate that the MBI buffer 18 is released and that the automatic test has started (means 639). The RETRY indicator is cleared at the means 640 and the bus stop timer is disabled at the means 641. As shown in FIG. 27B, if an error is detected in the means 636, control passes directly to the means 641 to completely terminate the DSITMO module.

When the DSITMO module calls the DSICOM module in the means 635, the DSICOM module in FIG. 28 operates the maintenance processor 300 as an auxiliary process in the means 650. Then, using the recovered DSI number in means 624 of FIG. 27B, processor 300 attempts to obtain a digital satellite access device in means 651. Firstly, it determines whether the identified digital satellite connection is in a call (means 652), if on a call, it attempts to obtain the digital satellite access device again via means 653. If the second attempt is unsuccessful, an error ERROR indicator is set in the means 654 and a return to the call regular process of FIG. 27B occurs. The error test in means 636 then switches control to means 641. If the digital satellite access device is not in a call, processor 300 determines whether the identified digital satellite access state actually includes the device needed by means 655. If this device is not included, the error marker is set at the means 654. In means 656, the complement processor determines whether the error marker is set, and in means 657, this determines whether the digital satellite connection is masked. If one of these two tests produces a positive result, an error marker is set in the means 654. If a number of tests make the appropriate responses, then control transfers to means 658, so that the maintenance processor 300 cracks the REAL INPUT FIFO bit in the control register 3011.

In the means 659, the maintenance processor obtains the digital satellite unit by sending its number and sets the WRITE CONTROL bit in the status register. In addition, the maintenance processor 300 tests the digital satellite access device to determine when the digital satellite access device is in a call at the means 660 using the means 661 for controlling the second attempt, and means 662. ) Test the presence of the device and the other error in means 663. If the digital satellite access device is busy, not equipped, or received an error in two tests, control transfers the means 664 to set the error marker before a return occurs. If these test sets indicate that a digital satellite connection is useful, then means 663 branches to means 665.

At this point, the message begins to communicate. In means 665-667, the digital satellite connection and the MBI buffer 18 are addressed to communicate with the particular diagnostic circuit 30 of FIG. Next, the maintenance processor 30 clears the control register 3011 of FIG. This determines whether the input FIFO 3013 is empty. If not empty, the message is ready for printing at the means 670 and the DSIMSG module is called to actually print the message at the digital switchboard (mean 671). If the input FIFO 3013 is empty, control passes from the means 669 to the calling module.

The DSIMSG module is shown in FIG. In this module, error messages are placed in the index table in the means 680. This tests the error in the means 681. If no error exists, the useful data area is cleared in means 681 and the program is returned. Therefore, when the DSICOM module is completely finished, the digital satellite interface 14 is obtained and the input FIFO 3013 in FIG. 20 allows the message in advance. Control is then transferred back to the means 637 in FIG. 27B, so that the autotest message is loaded into the input FIFO 3011 and the MBI buffer is released as described above. Automated testing begins at the digital satellite interface and the process is at means 505 in FIG.

Ii. Auto test operation

Referring back to FIG. 25, the means 506 causes the message to be received and decrypted and updates a number of status indicators. The decryption function is basically shown at 18 degrees. Specifically, during the time interruption, the system reaches the means 83. The digital satellite interface 14 then tests a number of adjustments and finds that there is an input message in the diagnostic circuit 30 in FIG. At this time, the digital satellite access device 14 starts an automatic test process.

Figure 25 shows the basic functions of the automatic test sequence to indicate the basic means generated. However, this description described in the drawings makes it possible to configure a large number of modules to be stored in the memory 28 for use by the digital satellite connection processor 27.

In means 507, processor 27 in digital satellite connection 14 selects a channel and selects a satellite line number to be tested from an internal table. Then, in means 508, this determines whether this satellite line number is in a call with the telephone call. If busy, the automatic test attempt is stopped at the means 509 and in turn the next satellite line number is set in the schedule before the test is completely finished.

If the subscriber line combined with the satellite line number is not busy, the processor 27 in FIG. 10 sends a LINE CONTROL message as shown in FIG. 16 with a set of test access opening (TA) bits. This test access relay operates to disconnect the line circuit 78 in FIG. 15 from the subscriber line and to connect it to the TT 1 and TR 1 lines shown in FIG. 23d. Processor 27 then sends a manual maintenance command in FIG. 16 to the designed satellite line number. The manual repair command includes a sign that causes the maintenance and management circuit 79 to begin the automatic test sequence. This forces the line circuit in the state that the maintenance and management circuits are testing off-hook and initiates a call sequence corresponding to the sequence already described.

This call is detected in the remote digital satellite connection such that a POLL RESPONSE message is sent over a continuous POLL message from the digital satellite connection 14 to the remote digital satellite unit 13. The POLL ASSIGN is then transferred and an ORIGINATE message is generated by the remote digital satellite unit 13. If this happens, the digital satellite connection 14 knows that the line is in a test state and sends a TEST CALL CONTROL message shown in FIG. 10 to the call processor 408. This test call control message includes satellite line number, assigned channel, and test indication. For automatic testing, the test indicator has a value of "0". Other values are used for manual testing. Sending this test call control message corresponds to the means 511 in FIG.

The call handler 408 responds to the test call control message and completely forms a passage through the call handler to the automatic test control circuit 20 shown in FIG. In addition, they establish passages for rapid detection supervision signals from the line under test conditions. These signals convey the state of the hook switch to the automatic test control circuit as FAST CONTROL monitoring information, in particular the DAA signal in FIG. 22D starting to operate the automatic test circuit 20.

The call processor 408 also sets a six second timer in means 512. During this period, all automated tests should be conducted. If the call processor 408 fails to establish the path of the automatic test circuit 20, the means 512 transitions the control state so that the call processor 408 can send a DISCONNECT message from the means 514. Means 515 can be prepared to test the same satellite line number when the next test is planned.

The means 516 corresponds to sending an ORIGINATE message to the digital satellite access device 14. This digital satellite connection device 14 responds to this message by sending an ORIGINATE RESPONSE message as shown in FIG. 16 identifying the span and channel challenging the automatic test.

The means 518 in FIG. 25 directs the transfer of the hook switch status signal through the call processor 408 to the autotest circuit over the "A" signaling bit of the span to begin operation.

As a result, the automatic test circuit generates a timbre appearing in means 519, receives the timbre appearing in means 520 and 521 and at least two dial pulses, and records these results in means 522. Specifically, at the end of the one second period, the dial pulse test (DP TEST) signal is generated in Fig. 22d, so that the dial pulse acknowledgment from the flip-flop circuit 2031 is indicated to indicate that the automatic test was successful. The DP OK) signal and the TONE RECEIVED signal provide the DAC signal to the port group control circuit.

30 to 32 illustrate the operation of the digital satellite interface 14 during the means 83 in FIG. 18A and the means 507 to 523 in FIG. 30 shows a number of adjustment states that can be tested in the means 83. For example, in the means 700 of FIG. 30A, the digital satellite interface 14 determines whether the formatter input FIFO 2511 in FIG. 6 includes a message from the control call processor 408. . This message is decrypted and processed by means 701 and 702. The means 03 transitions to the assumption (HSKPG) regular process in FIG. 18B when the message is sent to the remote digital satellite unit. The means 704 branches to the ACBE order in FIG. 30B when the message is sent to the call processor 408 or the maintenance processor 300. Meanwhile, the means 704 branches back to the means 705 to perform another test. If the formatter input FIFO 2511 does not contain a message, the means 700 branches directly to the means 705.

The ORIGINATE queue is a means for determining whether or not the queue includes an unmaintained ORIGINATE message received from a number of remote digital satellite units for subsequent processing by the digital satellite interface 14. Is tested at 705. If not empty, the means 706 recovers the oldest satellite line number waiting for a response and sends a message to the formatter 25.

The means 707 is a test for confirming that a message such as a message for starting an automatic test appears at the input FIFO 3013 of the diagnostic circuit 30 (FIG. 20). If the input FIFO 3013 does not contain a message, the means 707 branches to the means 708 to determine when a repair message is sent from the means 709 to the maintenance processor 300. The system is then transported in the ACBE order in which all channel busy queues are examined by means 71. Every channel busy queue indicates whether the channel is available on the spanning device. If on the phone, the means are taken irrespective of the present invention. If it is left blank and the channels become available, control transfers back to the means 85 to be tested to see if the output FIFO 3017 in the diagnostic circuit 30 of FIG. 20 contains a message.

Referring back to FIG. 30A, if the input FIFO 3013 contains a message, the processor 27 moves the message from the means 711 to the message buffer in the memory 28 during the LORMR order and moves the message from the means 712. Process this message in MPMD order. If the message is sent to the remote digital satellite unit, the means 713 branches off in HSPKG order. Meanwhile, the means 714 determines whether the message is sent to the call processor 408 or the maintenance processor 300. If this message is sent, control reverts back to the ACBE order indicated by means 71. If no such message is sent, control passes to means 708. Therefore, in FIG. 30A, the processor 27 is a number of means indicated by means 707, 711, 712, 713 and 714 to recover the message from the diagnostic circuit 30, such as the means 506 portion in FIG. Use order.

The transfer and processing of messages during the LDRMR and MPMD sequence shown in the means 711 and 712 is shown in detail in FIG. The index register for the processor 27 receives a value corresponding to the address of the message buffer in the memory 28 in the means 720 of FIG. 31A. In the means 721, the NMPM indicator is cleared and the DSI BUSY indicator in the diagnostic status register 3024 is set. The message register byte (MESSAG REGISTER BYTE) counter in memory 28 is then cleared by means 722. This causes processor 27 to begin transferring message bytes from input FIFO 3013 in diagnostic circuit 30 to the message buffer identified by the index register. After this transfer has occurred in the means 723, the message register byte counter is incremented in the means 724 and a test is made to determine whether many bytes are transferred in the means 725. Once the message is complete, control transfers to means 726 for clearing the READ OUTPUT FIFO bit in status register 3024.

If the input FIFO 3011 has another byte (means 725) and the message meets the maximum length request (means 727), the means 728 determines whether the maintenance processor 300 sends a new message to the input FIFO 3011. Decide This message invalidates the previous message. If no new message is sent, control transfers back to means 723 in FIG. 31A so that the next message byte can be obtained. If the message length exceeds the maximum, an error occurs, so the means 727 may set the INVALID MESSAGE ALARM bit and transfer the missing data from the buffer in memory 28 to clear the message ( 729). Control is then transferred back to the means 725 and control is transferred to the means 730 via means 726 because the input FIFO 3011 does not have an additional message byte. If the invalid message alarm bit is set in the means 729, it is moved back to the control HSPKG order. However, if the message is received validly, control transfers to the MPMD order shown in part in FIG.

The MPMD sequence decodes the header of the input message from the complement processor. Specifically, in FIG. 32, the fixed mode timer test at the means 740 typically transfers the control state to the means 741 to recover the first message byte from the buffer in the memory 28. At this time a set of consecutive decryption means is processed. The first of these decryption means 742 examines the beginning of the message to determine if a LOOP AROUND message has been sent. If so, the message is processed at the means 743 before control is transferred back to the HSKPG order.

The automatic test sequence begins with the message "B8FFO1" as described above. This front part is optionally decoded in the test sequence in the means 744. Due to the automatic test start message, the means 745 shifts the control state in ATST order. This sequence causes the digital satellite access device to operate to begin the means 507 to 523 in FIG.

Iii. Successful automated test response

As already described, the FAST SENSE bit in the pot accumulation area for the automatic test circuit 20 indicates whether the automatic test sequence was successful or failed. As described in U. S. Patent No. 924,883, the accumulation of the FAST SENSE bits creates an event that interrupts the call handler operation. In response, the call handler determines whether the test passed or failed. If this happens, the call processor sends a TEST REPONSE message shown in FIG. 10 to the digital satellite connection 14 indicating success or failure. The test response message contains the Remote Line Satellite Line Number (SLN) under test conditions and the test results. A test result of "1" indicates success and a test result of "2" indicates failure. This message is then received in the digital satellite connection 14 and the result is tested in the means 526 shown in FIG.

If the automatic test is successful, the digital satellite connecting device 14 transfers the LINE CONTROL message (means 527) shown in FIG. 16 to the remote digital satellite unit 13 under the test condition in which the bit is cleared. Let's do it. This causes the test access collector to be opened so that the line circuit is reconnected to the subscriber line and disconnected from the maintenance and management circuit 79. The disconnected (DS) marker is then set to indicate that the remote subscriber is on-hook. The digital satellite interface 14 then sends a RELEASE message, shown in FIG. 9, to the call processor 408, which can indicate that the line of the remote subscriber is idle and useful for making a call. . If the automatic test is successful, the ATD REQUIRED indicator is cleared, so that means 530 branches to means 531. At this time, the digital satellite connection device 14 sends a TEST COMPLETE message to the maintenance processor (means 531) having a BO front part followed by a sign indicating that the automatic test is completed.

Iii. Response of Auto Test Failure

If the test response message indicates a failure, then means 526 in FIG. 25 branches to means 522 to set the ATD request indicator and test the state of the ORIGINATE bit in means 533. The outgoing bit is set when the outgoing message is sent, indicating whether a first means for placing the call occurs (ie, the outgoing message is processed in means 511). If this message is not sent, the line control message is sent to the remote digital satellite unit to release the TA relay (means 534) and then control is transferred to the means 529, so that the digital satellite interface 14 is called a call processor. Send a release message to 408. When an outgoing message is sent, normal disconnection processing of the means 527 to 529 occurs. In either of these cases, the means 530 branches to the means 535 to begin an automatic test diagnostic sequence using successive automatic tests through different cross sections of the remote digital satellite unit to isolate the cause of the failure. do. Therefore, the means 536 transfers control back to the means 507 to start another test call. When the sequence is complete, the means 536 branches to the means 537 so that the digital satellite interface 14 has a message indicating failure and diagnostic results. This message is sent to the maintenance processor before being sent to the means 531.

In other failure modes, the automatic test sequence does not end entirely within the selected time. In this mode, the MP timer in the maintenance processor 300 is stopped so that the maintenance processor 300 clears the INPUT FIFO EMPTY bit in the status register 3011 of the diagnostic circuit 30 in FIG. To be tested (means 541). This bit is set when the digital satellite connection 14 does not allow the previous message (means 542), so it starts operating again in the processor processor 543. If this is the first stop, the means 544 branches and a new automatic test begins at the means 545. However, if a second stop occurs or a stop occurs in the means 503, control passes to the means 504. If the input FIFO non-blank bit is cleared after the first stop (means 541), control is transferred from the means 546 to the means 547 so that the maintenance processor 300 stops the automatic test. Will be able to send messages. After the second stop, the means 547 is viewed directly with the means 504 to begin the necessary failure diagnosis.

Iii. Automatic test result message of maintenance processor

Once the automatic test result of the call handler 408 is obtained, it sends a message to the maintenance processor 300. Since the DSIHND module in the maintenance processor 300 shown in FIG. 24 sets the display characters, the DSIFLD module in FIG. 26A branches off from the means 600 to call the DSICAL module shown in FIG. . The DSICAL module first determines whether the message is an automatic test result (means 801). If so, a "procedure" (DSIAT) subnormal procedure is invoked in the means 802. Referring to FIG. 34, the maintenance processor 300 first determines whether the digital satellite interface, which is recorded as having completed the automatic test function, is in the process automatic test state. If in this state, the means 803 branches to the means 804 to clear the procedure (DSI CIN) indicator and transfer the control state back to the means 805 in FIG.

If the recorded interface number (i.e., DSI number) is not correct, a number of means shown in FIG. 34 provide a number of tests to isolate the cause of this error. First, the maintenance processor 300 sets a period for testing in the means 807 by accumulating numbers in the means 806 and operating the maintenance processor timer. The maintenance processor 300 then uses the DSICOM module in FIG. 28 to obtain a connection that is assumed to be under test (mean 808). If errors are detected, the means 809 branches to fully process the DSIAT module. If the loop test in the means 810 is successful, control transfers back to the call normalization process in the means 811. Since the DSICIN indicator is cleared and the error index is set along the DSI number in the means 812, the DIAG2 diagnostic module can be used to identify the cause of the incorrect procedure (means 813).

In the normal procedure, control returns from the DSIAT module to the means 805 in FIG. 33 to begin the message control sequence. The DSIPR order is called in the means 820 to print such a message on a printing press, such as the telegraph typewriter 305 in FIG. If the message is not printed, control passes to means 820 to see if a LOOP AROUND PRINT indicator has been set. Meanwhile control passes to means 822 to see if a LOOP AROUND message is sent. If not sent, the module is completely terminated. If so, then control is passed to means 823, where the print perimeter of the loop is cleared and transferred to means 806 to invoke the DSIPR module to print the message.

Iii. Auto test diagnosis

The response to the indication of automatic test failure is shown in means 516 to 537 in FIG. 25 and in detail in FIG. In the means 900, the digital satellite connection 14 is tested to determine if it is useful for automatic testing. If not useful, the means 901, 902 and 903 ascertain what action is taken. If useful, a test is made to determine if this is a second attempt to continue the automatic test operation. If this is the second attempt, means 904 branches to means 905 to set the ATD REQUIRED bit. Automated tests, on the other hand, continue to be conducted. If this test is successful, a set of means 906 similar to means 901-903 sets up a message to be sent to the maintenance processor 300 and then disconnects the line. If it fails, the means 907 corresponding to the means 532-534 in FIG. 25 test the ORIGINATE bit to set the ATD request bit, release the test access relay, and disconnect the wire.

According to another aspect of the invention, the remaining means in FIG. 35 perform a successful automated test. However, these tests are carried out on the passage through the remote digital satellite unit 13, which is shown in the schematic diagram of FIG. 15 different from the originating passage of the first automatic test call. In order to understand the specific inherent characteristics of this diagnostic test, each line circuit 78 in the digital satellite connection is one of a number of even or odd cells or groups of lines corresponding to the even and odd divisions of the local telephone line 11. It is the same as being one. This is described in US Patent 924,883. Therefore, at the means 910, the digital satellite connection 14 determines whether other lines in the same half (i.e. even or odd half) of the line containing the originating circuit are useful when making the test. A message with a result code "9" is sent to the maintenance processor 300 indicating that no line is available at the means 911 and that an automatic test is performed on this line at the means 912. If the automatic test is successful, the digital satellite connection device 14 disconnects this line and sends a result code "1" indicating that the outgoing line circuit 78 has failed.

If the automatic test performed at the means 912 fails, the digital satellite interface 14 determines whether the transmission line has a shared channel over the span. If so, a message is sent from the means 915 to the maintenance processor indicating the failure and the fact that the outgoing line is a shared channel. If the channel is not public, the ORIGINATE bit is tested at the means 916. If the originating bit is set, the second line circuitry detects the call and indicates that the line associated with the second call is disconnected.

If the remote digital satellite unit includes two " half " (i.e., both even and odd half), the means 920 can operate the processor 27 to check whether the line is useful in this other half. Branch to means 921. If such a line is not useful, a result code "OA" is sent from the means 922 to the maintenance processor indicating that the other line is not useful. On the other hand, the line in the other half is tested in the means 923. The success of this test indicates that the transmission line circuit clock dividing buffer 80 in FIG. 15 is defective. If it fails, the wires included in this second test are disconnected.

If the second test fails or cannot be conducted, the third test determines whether the line level multiplexer / demultiplexer has failed. Specifically, another line in another cell of the same digital satellite connection is selected at the means 926. This should place the call through the other circuits 76A, 76B, etc. in FIG. If such a line is not useful, the means 927 means that the line is not useful in another cell (result sign "OC") but does not have another cell to which the remote digital satellite unit is assigned (result sign "OB"). Create a message that directs you to If the line is available, the automatic test is carried out again (mean 930). If this automatic test passes, the circuit in line level multiplexer / demultiplexer 76 in FIG. 15 used in the next outgoing call is bad, so that a message with result code " 03 " If the automatic test at the means 930 fails, the line used in this third attempt is disconnected at the means 932.

The utility of the outgoing line through other channels on the communication line is then tested in means 933. "Other channels" means where the originating line is assigned the "odd" channel, so this test shall be carried out on the "even" channel. If such a channel is not useful, test result codes indicating that such a channel is not useful over the same span (i.e., "OD") or that the outgoing line is passing (i.e., "17") are combined in the message of the maintenance processor. (Mean 934). If such a channel is available, the automatic test is again carried out on the calling line (mean 935). If the test is successful, then a message is sent from the means 936 to the maintenance processor 300 indicating that the line channel interchange circuitry causes a malfunction (ie, the result sign "4"). When unsuccessful, the originating line is disconnected (means 9400).

In the fourth test, the test call is placed over another span of the outgoing line. The usefulness of other spanning channels is tested in the means 941. Otherwise, a message is sent to the means 942 indicating that the channel is not useful over the next span (ie result code "OE") but that the calling line is busy (ie result code "17"). . If the next span is available, the channel is selected and the automatic test is continued on means 943. If this test is successful, the transmitter / receiver fails and the result code "5" is combined in the maintenance processor message. If the test fails, then the line channel mutual change circuit 76 is again instructed to be bad and a corresponding result code "14" is sent. In other words, it is different from the result code "4" which is sent to the means 936 to discriminate between the two tests which indicate a line channel interconversion failure. In either case, processor 27 disconnects the transmission line at the means 945. This completes this shunt of automatic test diagnostics, so the processor 27 uses the means 537 in FIG. 25 to send a message and sends the means 531 to send a TEST COMPLETE message. Use

Referring back to the means 916, the test access relay is released at the means 950 when the ORIGINATE bit is not set. The system then tests to determine if another remote line circuit controller 74 is useful (means 951). If nothing is useful, a message with the result sign "OF" is sent (mean 952). When another remote line circuit controller becomes available and the line becomes unavailable (means 953), a message with a result code "10" is sent to indicate that the line is not useful in the same remote digital satellite unit. When the line is available, automatic testing continues in this other line in another remote line control circuit of the same remote unit. If the test passes, the line circuit control circuit is instructed to fail, and a message with result code "6" is sent from the means 966 to the maintenance processor. If this test fails, the originating bit is released again in means 957. Once the originating bit is set, the line is disconnected in the means 959 to prepare for another test.

In either of these cases, if there is one or more remote groups with one or more digital satellite units, the means 96 are moved to the means 961 to determine if lines are available in these units. If there is only one remote group, a message with result sign "13" is sent (meaning 962). If the line is not available at another remote digital satellite unit, a message with result code "12" is sent (mean 963). If the line is useful, another automatic test is continued at the means 964. Passing this test will cause problems in the circuit controller, maintenance and management circuitry 79, transmitter / receiver 71, or elsewhere, indicating that the original remote digital satellite unit is in an unmaintained state. A message with result sign "7" is sent (mean 965). If the test on means 964 fails, a message with a result code "15" is sent because of a problem with the digital switching center (means 966), after processing means 965 or after processing means 966. The processor 27 disconnects the wires used during the final test.

In short, there have been various levels of detail of telephone circuitry using digital telephone exchanges suitable for supporting remote digital satellite units connected to remote subscriber lines. Specifically, this description relates to the parts of the circuit that make it easy to test a remote digital satellite unit by a simple "stop-going" test. For this test, a simple passage must be established between the test circuit of each remote digital satellite unit and the automatic test circuit of the digital telephone exchange. If the connection is made with conventional call processing techniques or any other technique, the automatic test circuit sends the timbre and the timbre from the remote digital satellite unit which can be monitored to determine whether the timbre and dial pulses fall within the specified specification. And wait to receive a dial pulse. If the tone and dial pulses fall within the specification, the test is passed. Otherwise, the test circuit can be used for diagnostics performed by the digital satellite interface. This process uses ancillary tests that call other parts of the circuit, if possible, to isolate the cause of the problem.

The invention is shown in the figures as a schematic diagram, a flow diagram and a logic circuit diagram. With the above description, logic circuit designers can design the network and programmers can write plans for operating a particular processor even if they are inexperienced. In addition, while the foregoing description has been described with respect to the embodiments, many other circuits and logic mechanisms may be provided so that one automatic test circuit may be provided to test all telephone circuitry to communicate with a maintenance processor. The automatic test circuit 20 in FIG. 2 is connected to the port group unit in the call processing system. However, other applications may not have this connection. For example, one such circuit can be connected with a connection corresponding to each digital satellite connection, thus requiring a number of circuits, but can invoke a parallel test from a digital switching center. In such a system, another device such as an output device connected to each connection device can be used for recording. Therefore, the appended claims include all such changes and modifications that may be made within the principles and background of the present invention.

Claims (4)

Digital switching centers with call processing units carrying voice data and monitoring data, communication lines between remote port units and digital switching centers, and automatic communication for communication via remote test paging devices and connecting devices in each remote port unit. A method for testing a circuit in a telephone network comprising a test call device, the method comprising: means for establishing a communication path between a remote test call device and an automatic test call device, remote test call through a connecting device in response to communication being established; Means for generating a first voice in the automatic test call device for transferring it as voice data to the device, and transferring it as voice data to the automatic test call device through the connecting device in response to receiving the first voice from the automatic test call device. Second tone for remote test call device Means for generating, at the remote test call device, a signal corresponding to a dial pulse for transferring as monitoring data to the automatic test call device through the connecting device in response to completion of the second tone, second tone and dial pulse signal. Means for testing in an automatic test call device and means for generating an indication of the success or failure of the test in the automatic test call device in response to the test. Digital switching center device having call processing unit for carrying voice data and monitoring data, remote port device connected to remote subscriber line at a distance from this digital switching center device, between this remote port device and digital switching center device To confirm that communication is established between the remote port device and the automatic test call device in order to communicate with the communication line device through the communication line device of the communication line device, the connection device connected to the communication line device and the call processing device. Device, a tone generator for generating a first tone for transfer as voice data through the interface in response to communication being established, an input signal from the interface for testing a second tone signal and a dial pulse signal The test apparatus in response to the above and the above time to indicate that the test was successful. An automatic test call device comprising a device connected to the device and disposed in each of the remote port devices, the automatic test to generate a second tone for transfer to the automatic test call device through the connection device. Dial pulses responsive to completion of the second tone to generate a signal corresponding to receiving a first tone from the caller and a signal corresponding to a dial pulse for transfer to the automatic test caller through the connection device. A telephone network comprising a remote test call device comprising a generator. Digital switching center device having call processing unit for carrying voice data and monitoring data, remote port device connected to remote subscriber line at a remote location from the digital switching center device, the remote port device and digital switching center An automatic test call device for easily testing a telephone network including a communication line device between a device and a connecting device connected to the communication line device, wherein the automatic test call device is connected to the communication line device through a connecting device. A device connected to communicate, for confirming that communication is established between the remote port device and the automatic test call device, for generating a first tone for transfer as voice data through the connection device in response to the communication being selected. To test the tone generator, second tone signal and dial pulse signal Automatic test call device characterized in that it comprises a device connected to the access point to indicate that the testing apparatus and tested for response to the input signal from the access success. A digital telephone switchboard unit having a call processing unit for carrying voice data and monitoring data, a remote port unit connected to a remote subscriber line at a distance from the digital telephone station unit, the remote port unit and the digital telephone exchange station A remote test call device for easily testing a telephone network including a communication line device between devices and a connection device connected to the communication line device, wherein the automatic test call device comprises a remote port through the connection device and the communication line device. A device for generating a first tone for transfer to a device, wherein the remote test call device is connected to a remote port device and a communication line device, and a second for transferring to the automatic test call device through the connection device. Receive first voice from auto test call device to generate sound And a dial pulse generation device responsive to completion of the second tone to generate a signal responsive to a dial pulse for transfer to the automatic test call device through the connection device. Remote test calling device.

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