JPH06260910A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To attain transmission of selection information through a data transmission line only by preparing a non-signal period and updating the selection signals every time the data are divided into a prescribed number of pieces at and after the time point when the non-signal period is through. CONSTITUTION:When a selection signal B falls, the output signals of L levels are generated by a monostable multivibrator 4 for a prescribed time. When the generation of output signals of the multivibrator 4 is over, the output signal received from a V/F converter 2 is sent to a transmission line from an AND circuit 5 and supplied to a 1/m counter 6. The counter 6 transmits the overflow signals every time the input signal of the counter 6 is divided into (m) pieces. As a result, an AB counter 3 is set in a count-up state and the selection signals A and B are updated in each count-up state of the counter 3. A multiplexer 1 selects one of input terminals d1-d4 and transmits a data signal. Therefore the selection periods of all channels equal to the periods when (m) pieces of output of the circuit 5 are generated. Thus it is possible to know the selection state at the receiver side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit for sequentially selecting a plurality of analog input signals and transmitting the selected signals in a format capable of discriminating a data group currently transmitted at the receiving side. is there.

[0002]

2. Description of the Related Art Conventionally, for example, the one shown in FIG. 5 has been used for transmitting by switching a plurality of analog signals. This is for switching the analog signals supplied to the terminals d1 to d4 by the multiplexer 1, converting the output to pulse data by the V / F converter 2, and transmitting the pulse data.

In this case, the select signals A and B generated by the counter 3 are also transmitted at the same time in order to inform the receiving side which one of the channels d1 to d4 is selected. That is, as shown in FIG. 6, select signals A and B
And three types of signals of data S are transmitted.

[0004]

However, when a metal cable is used for the transmission line and the transmission distance is short, this is sufficient, but when the transmission distance becomes long, the cost increases due to the increase in the number of transmission lines. Further, in recent years, optical cables have been used even at short distances in order to prevent interference with others due to problems such as EMC and to prevent interference with oneself.

Optical cables are more expensive than metal cables, and connectors and input / output interfaces are also more expensive than metal cables, and the increase in the number of wires and the increase in cost are in proportion to each other, and the increase in the number of wires is economical. It had the problem of making it worse.

The present invention has been made in view of such a situation, and is such that select information can be transmitted only through a transmission line for data transmission.

[0007]

In order to solve such a problem, the present invention provides a pulse regulating circuit for stopping the transmission of the pulse for a predetermined time when the input signal has been selected once, and an end of the predetermined time. Divide the pulse sent out later,
A selection circuit for selecting an input signal each time a predetermined frequency division value is reached is provided.

[0008]

The data is frequency-divided after the data interruption time which is generated in synchronization with the cycle of the select signal, and the counter is counted up and the select signal is switched every time the predetermined frequency division number is reached.

[0009]

1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 5 use the same symbols. Figure 2
When the signal B of the counter 3 falls at the time t1 of (b), an output signal of L level is generated from the monomulti 4 for a predetermined time t as shown in (c). As a result, the AND gate 5 does not output the output of the V / F converter 2 only during the period t in which the output signal is generated as shown in (d).

When the output signal of the mono-multi 4 ends, V /
Since the output signal from the F converter 2 is sent from the AND circuit 5, it is sent to the transmission line as the data S from the time t2 as shown in (d) and is divided by the counter 6.

The counter 6 sends out an overflow signal as shown in (f) every time the input signal is divided by m, so that the counter 3 counts up.
The select signal is updated each time as shown in (a) and (b), and the multiplexer 1 selects the analog signal of the next channel.

As a result, the output of the AND circuit 5 is input terminal d each time the select signal is switched as shown in (e).
One of 1 to dn is selected and a data signal obtained by converting an analog signal supplied to the terminal into a pulse signal is transmitted. The input of the monomulti 4 is set to the signal B in order to obtain the timing of one round of the select signal.

During the period when the input signal d1 is selected as shown in FIG. 2E, after (c) becomes H level,
(E) From the generation of the first output pulse to the output of the mth pulse.

When m pulses are generated, 1 /
The output of the m counter 6 is generated, the counter 3 counts up, and the period of the input signal d2 is entered. As a result, the select period of all the channels is a period in which m outputs of the AND circuit 5 are generated, so that the receiving side can know the selecting status by receiving the signal sent from the transmitting side.

The analog values of the input signals d1 to d4 are the instantaneous values, and the average values are shown in FIG.
It can be known by the cycle of (a). Where V /
It is assumed that the pulse output repetition period of the F converter 2 is set to be shorter than the pulse width of the monomulti 4 even in the longest period. However, FIG. 2 is not necessarily such a diagram due to the limitation of the size of the paper.

As described above, according to the configuration shown in FIG. 1, since m pulses are sent during each select period of the input signals d1 to d4, the receiving side restores the select signal by the circuit shown in FIG. can do. Figure 4
While the input signal shown in (a) is being supplied, the retrigger monomulti 7 sends out an H level signal as shown in (b), but when the data stop period t comes, the data stops. After a period tr from, the L level signal is transmitted. This resets the counter 8 and the counter 9.

When the data stop period t ends and the data S is input as shown in (a), the retrigger monomulti again sends an H level signal, and the counters 8 and 9 start operating. .

As a result, the counter 8 sends an overflow signal each time the input signal is divided by m, and the quaternary counter 9 counts up each time. The output signals A and B of the quaternary counter 9 are synchronized with the select signals A and B generated on the transmitting side. Therefore, if the output signal of the quaternary counter is used as the select signal on the receiving side, the same select signal used on the transmitting side can be reproduced on the receiving side.

Although the embodiment has been described with an example of four channels, this is an example and the number of channels can be set arbitrarily. Further, although the transmission line is described as a metal or an optical fiber cable, the same applies to a wireless transmission line, and in this case, the economic effect is particularly remarkable.

[0020]

As described above, according to the present invention, when data is transmitted while sequentially selecting a plurality of input data so as to make one cycle at a predetermined cycle, all the pulse groups of each channel are transmitted in the same predetermined number. In addition, the no-signal time is provided in the data in one cycle, and the select signal is updated every time the data is divided by the predetermined number from the end of the no-signal time. Since the select signal can be easily restored and the select signal can be sent only through the data transmission line, and the select signal can be transmitted without increasing the number of transmission lines, the transmission line can be economically constructed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a circuit diagram showing a configuration of an embodiment on a receiving side.

FIG. 4 is a time chart showing the operation of FIG.

FIG. 5 is a circuit diagram showing a configuration of a conventional example.

6 is a time chart for explaining the operation of FIG.

[Explanation of symbols]

 1 multiplexer 2 V / F converter 3, 8, 9 counter 4 monomulti 5 AND circuit 6 counter 7 retrigger monomulti

Claims (1)

[Claims] 1. A data transmission circuit for sequentially selecting a plurality of types of analog input signals at a predetermined cycle and transmitting both a signal having a pulse number corresponding to an input signal level and information selected at that time, A pulse regulating circuit that stops the output of the pulse for a predetermined time when the input signal is selected once, and a pulse that is sent after the end of the predetermined time is divided, and the frequency division result reaches a predetermined value. A data transmission circuit comprising a selection circuit for selecting different input signals.