JPH06259892A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To stabilize oscillation frequency of a voltage control oscillator being a component of a PLL circuit by eliminating pulses which are positioned at a preceding stage of a reproducing PLL circuit and whose time intervals are shorter than the prescribed time interval caused by a defect of an information recording medium or the like. CONSTITUTION:This circuit is constituted of a gate circuit 1 which outputs a prescribed time gate signal from individual pulse edges of a digital signal pulse train, and a pulse restricting circuit 2 to which a digital signal train and a gate signal is inputted and which eliminates either of adjacent pulses in the digital signal train. Thereby, oscillation frequency of a voltage control oscillator being a component of a PLL circuit of a post stage is stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention eliminates the occurrence of short-duration pulses in the digital signal pulse train due to defects in the recording medium, writing errors, etc. in a recording device that handles digital signals such as optical disks, magnetic disks, and VTRs. Signal processing circuit.

[0002]

2. Description of the Related Art In recent years, a method of recording information such as voice and image on a recording medium such as a disk or tape is changing from a conventional analog recording method to a digital recording method. Generally, a PLL circuit is used for reproducing a digital recording signal. FIG. 9 shows a block diagram of a digital signal reproducing circuit using such a PLL circuit.

In FIG. 9, an analog reproduction signal (a) obtained by reproducing a recording medium such as a disk or a tape from the information reproducing device 6 is applied to the waveform shaper 1.
It is digitized by (5) and is input to the phase comparator 16 together with the output signal (C) from the voltage controlled oscillator 18, (A),
A phase error signal (D) obtained by phase comparison of (C) is input to the low-pass filter 17, and this output (E) is input as the control voltage of the voltage controlled oscillator 18 to obtain P
An LL (PHASE LOCKED LOOP) circuit is configured to generate a data clock (c) synchronized with the reproduction signal (a) and generate clock-synchronized data based on this. However, the phase comparator 16 here is configured to output the error signal only when the digitized reproduction signal (a) is input.

[0004]

As described above, the PLL circuit is often used to extract the data clock from the reproduction signal during the reproduction of the digital recording information. A case where the reproduced signal is disturbed by mixed noise or the like will be described. If there is a disturbance in the reproduced signal due to a defect in the recording medium, a large phase error signal will be generated in the phase comparator due to this influence, and a large voltage fluctuation will occur in the control voltage that is the input of the voltage controlled oscillator. The phenomenon that the frequency of the clock output from the oscillator fluctuates greatly occurs. Clock frequency fluctuations cause data demodulation errors such as bit shifts. As a means for avoiding this, it is conceivable to increase the time constant of the low-pass filter of the PLL circuit to suppress the frequency fluctuation of the clock output from the voltage controlled oscillator. There was a limit because it was connected.

In the magnetic recording medium and the like, a method of removing an error caused by a defect of the recording medium is often used by utilizing the characteristic of magnetic recording and monitoring the amplitude and polarity of the reproduction signal.

However, in a recording medium such as an optical disk other than the magnetic recording, the magnetic characteristics (polarity) cannot be used, and accordingly, appropriate measures must be taken against defects in the recording medium. The pulse edge recording method is often used to increase the density of disks. In the pulse edge recording method, the edge position of the pit formed on the disc is the playback P
It is necessary to be accurate because it becomes the phase information of LL. If the pit edge position deviates from the original position due to a defect or an error on the disk, a large phase error signal is generated at the output of the phase comparator of the PLL circuit, and the frequency of the clock output from the voltage controlled oscillator is generated. Fluctuates greatly.

Here, when the density of the disk is increased,
Defects etc. on the disk tend to occur in a direction that becomes shorter than the minimum inversion interval when the recording wavelength is short. In the RLL (RUN LENGTH LIMITED) encoded signal that is often used in digital recording, the minimum inversion interval and the maximum inversion interval. Noting that each modulation method is determined by each modulation method, if an error occurs on the recording medium and a harmful pulse of less than the minimum inversion interval of the RLL code is generated, a device for erasing the harmful pulse is placed in the front stage of the PLL circuit. The frequency fluctuation of the clock output from the voltage controlled oscillator can be effectively suppressed.

In view of the above point, the present invention has an object to provide a signal processing circuit for stabilizing the oscillation frequency of the voltage controlled oscillator of the PLL circuit.

[0009]

A signal processing circuit according to the present invention is located in a front stage of a PLL circuit, and when adjacent pulse intervals in a digital signal pulse train are a predetermined time T or less, one of the adjacent pulses is removed. This is the configuration.

Further, the signal processing circuit of the present invention is located in the preceding stage of the PLL circuit, and is configured to remove both pulse pairs having adjacent pulse intervals of a predetermined time T or less in the digital signal pulse train.

[0011]

Since the present invention can effectively eliminate an error caused by a defect in the disc when reproducing recorded information, the present invention reduces the response of the entire reproducing system if it is placed before the PLL circuit. PL without
It is possible to stabilize the frequency of the clock output from the voltage controlled oscillator of the L circuit, and it is possible to stably reproduce the recorded information.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The signal processing circuit of the present invention will be described in detail below with reference to the drawings. In the embodiment of the present invention,
As an example, the digital signal pulse train has a minimum inversion interval and a maximum inversion interval determined in advance by a predetermined modulation method, and the signal processing circuit is located in the preceding stage of the PLL circuit.

First, a signal processing circuit according to a first embodiment of the present invention will be described with reference to the block diagram of FIG. 1 and the timing diagram of FIG. The digital signal pulse train (a) that is the input in FIG. 1 is input to the gate circuit 1, and the gate signal (b) is output for a predetermined time T from each pulse edge of the digital signal pulse train (a).

Next, the pulse limiting circuit 2 of FIG. 1 outputs the digital signal pulse train (a) only while the gate signal (b) is at the Hi level, and obtains the signal (c) in which the short time interval pulse is erased. There is. Depending on the time T to apply the gate (c)
The minimum time of the pulse interval obtained by is determined.

A signal processing circuit according to the second embodiment will be described with reference to the block diagram of FIG. 3 and the timing chart of FIG. In the digital signal pulse train (d) that is input in FIG. 3, the detection circuit 3 detects the presence of a pulse pair whose time interval is a predetermined time T0 or less. In FIG. 4, the pulse interval is T1 (≦
The detection output (e) is generated at the portion T0). In addition, the delay circuit 4 outputs the digital signal pulse train (d) for a predetermined time D.
A delay of (> T0) is given (f). When the detection circuit 3 detects the occurrence of a pulse pair with an interval of T0 or less, the pulse erasing circuit 5 erases both the pulse pair with an interval of T0 or less from the delayed digital signal pulse train (f) (g).

A signal processing circuit according to the third embodiment will be described with reference to the block diagram of FIG. 5 and the timing diagram of FIG. The analog reproduction signal (h) obtained by the information reproducing device 6 is sliced into a binarized signal (i) by the binarization circuit 7 at a constant DC level. The edge detection circuit 8 detects the rising edge and the falling edge of the binarized signal (i), and the pulse data (j) is output by using both the falling edge and the rising edge as a trigger. The trailing edge of the pulse data (j) is used as a trigger to operate the monostable circuit 9 to generate the gate signal (k) for a predetermined time T.

In the integrating circuit 10, the logical product of the pulse data (j) and the gate signal (k) output from the monostable circuit 9 is calculated to obtain a predetermined time from the fall of the pulse data (j). A short-interval pulse removal signal (l) is generated by removing pulses generated within T.
By placing this signal processing circuit in the front stage of the PLL circuit for extracting the data clock from the digital recording information,
Since it is possible to effectively remove an error caused by a defect in the disk, it is possible to prevent a large error signal from being generated in the phase comparator and to prevent the control voltage of the voltage controlled oscillator 18 from largely fluctuating. It is possible to effectively suppress the frequency fluctuation of the output clock.

A signal processing circuit according to the fourth embodiment will be described with reference to the block diagram of FIG. 7 and the timing chart of FIG. The analog reproduction signal (m) obtained by the information reproducing device 6 is sliced at a constant DC level in the binarization circuit 7 to be a binarized signal (n). The binarized signal (n) is detected by the edge detection circuit 8 as rising and falling edges, and pulse data (o) is output using both rising and falling edges as triggers.
First triggered by the falling edge of pulse data (o)
The monostable circuit 11 is operated to generate the first gate signal (p) which rises for a predetermined time T from the fall of the pulse data (o).

In the first integrating circuit 12, the pulse data (o) is ANDed with the first gate signal (p) output from the first monostable circuit 11 to obtain the pulse data ( A short interval pulse generation signal (q) indicating that a pulse exists within the predetermined time T from the trailing edge of o) is generated. The second monostable circuit 13 is operated by using the falling edge of the short-interval pulse generation signal (q) as a trigger to generate the second gate signal (r) which falls only during G (> T) for a predetermined time. generate.

Further, the logical product of the delay signal (s) obtained by delaying the pulse data (o) by the delay circuit 4 by the predetermined time D (> T) and the second gate signal (r) is calculated as the second product.
The short-circuit pulse pair removal signal (t) is generated by calculation in the integration circuit 14 of FIG. By placing this signal processing circuit in the front stage of the PLL circuit for extracting the data clock from the digital recording information, it is possible to effectively eliminate the error caused by the defect of the disk and the like, so that a large error signal is generated in the phase comparator. It is possible to prevent the generated control voltage of the voltage controlled oscillator 18 from largely fluctuating, and it is possible to effectively suppress the frequency fluctuation of the clock output from the voltage controlled oscillator 18.

In the first and second embodiments, the pulse which is later in time among the adjacent pulses is removed. However, since the delay device for delaying the digital signal pulse train is provided, It is possible to remove only the earlier pulse. Moreover, the short-time interval pulse removing methods shown in the first, second, third, and fourth embodiments are examples, and other configurations may be used as long as they perform the same operation.

[0022]

As described above, the signal processing circuit of the present invention is
When the adjacent pulse interval in the digital signal pulse train, which is located in the preceding stage of the PLL circuit, is less than or equal to the predetermined time T, one or both of the adjacent pulses are removed to thereby perform voltage control which is a constituent element of the PLL circuit. It is a circuit that stabilizes the frequency of the oscillator, and can remove short-duration pulses of the digital signal pulse train that are caused by defects in the recording medium, writing errors, etc., and reduce the response of the entire reproduction system when reproducing recorded information. It is possible to stabilize the frequency of the clock output from the voltage-controlled oscillator of the PLL circuit without performing the operation, and it is possible to stably reproduce the recorded information.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal processing circuit according to a first embodiment of the present invention.

FIG. 2 is a timing diagram of the first embodiment of the present invention.

FIG. 3 is a block diagram of a signal processing circuit according to a second embodiment of the present invention.

FIG. 4 is a timing diagram of the second embodiment of the present invention.

FIG. 5 is a block diagram of a signal processing circuit according to a third embodiment of the present invention.

FIG. 6 is a timing diagram of the third embodiment of the present invention.

FIG. 7 is a block diagram of a signal processing circuit according to a fourth embodiment of the present invention.

FIG. 8 is a timing diagram of a fourth embodiment of the present invention.

FIG. 9 is a block diagram of a conventional digital signal reproducing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 gate circuit 2 pulse limiting circuit 3 detection circuit 4 delay circuit 5 pulse erasing circuit 6 information reproducing apparatus 7 binarization circuit 8 edge detection circuit 9 monostable circuit 10 integrating circuit 11 first monostable circuit 12 first integrating circuit 13 Second monostable circuit 14 Second integrating circuit 15 Waveform shaper 16 Phase comparator 17 Low pass filter 18 Voltage controlled oscillator

Claims (5)

[Claims] 1. When the adjacent pulse interval in the digital signal pulse train is located in the preceding stage of the PLL circuit and is shorter than a predetermined time T, one of the adjacent pulses is removed to be a constituent element of the PLL circuit. A circuit for stabilizing the frequency of a voltage controlled oscillator, the gate circuit outputting a gate signal for a predetermined time from each pulse edge of the digital signal pulse train, and the digital signal train using the digital signal pulse train and the gate signal as inputs. 2. A signal processing circuit, comprising: a pulse limiting circuit for removing one of the adjacent pulses. 2. The frequency of a voltage controlled oscillator, which is a constituent element of the PLL circuit, is stabilized by removing both pulse pairs that are located in the preceding stage of the PLL circuit and have adjacent pulse intervals of a digital signal pulse train that are equal to or less than a predetermined time T. A detection circuit that receives the digital signal pulse train as an input, detects a presence of a pulse having an adjacent pulse interval of a predetermined time T or less in the digital signal pulse train, and outputs presence information; A delay circuit for giving a delay of a predetermined time D (D> T), and a pulse erasing circuit for erasing together a pulse pair having a pulse interval of the predetermined time T or less from the digital signal pulse train with the detection circuit output and the delay circuit output as inputs. A signal processing circuit comprising: 3. The gate circuit is composed of a monostable circuit which receives a digital signal pulse train as an input and outputs a gate signal by using an edge of the digital signal pulse as a trigger, and the pulse limiting circuit is composed of a logic circuit. The signal processing circuit according to claim 1, wherein the signal processing circuit is a signal processing circuit. 4. A first monostable circuit which receives a digital signal pulse train as an input and outputs a first gate signal by using an edge of the digital signal pulse as a trigger, the digital signal pulse train and the first monostable circuit. Of the gate signal, and outputs a short-time pulse detection signal. The pulse erasing circuit uses the pulse edge output from the first logic circuit as a trigger to generate a second gate signal. A second monostable circuit that outputs a signal, and a second pair that receives the delay circuit output and the second gate signal as an input and erases a pulse pair having a pulse interval of a predetermined time T or less in the digital signal sequence The signal processing circuit according to claim 2, wherein the signal processing circuit comprises a logic circuit. 5. The phase comparator of the PLL circuit operates only when either one of the rising edge and the falling edge of the digital pulse signal train is input. Signal processing circuit.