JPH06259117A - Operational error processing method for programmable controller - Google Patents

Abstract

PURPOSE:To omit the confirmation of a flag after execution of the four rules of arithmetic by transmitting an interruption signal to an operation processor from another to process an error of data. CONSTITUTION:A buffer 211 of a 2nd operational processor 210 receives sequence instruction of a computing subject, and a decoder 213 identifies the type of the instruction and gives an instruction to a selector 212. The selector 212 sends the sequence instruction to one of arithmetic circuits 214A-217A in accordance with the type of the instruction. Thus an arithmetic operation is carried out in response to the sequence instruction. When an overflow error is detected by one or error detecting circuits 214B-216B, an interruption signal is supplied to a 1st interruption terminal of a 1st operational processor 200. Thus the processor 200 processes the overflow error by the interruption processing. If a zero error occurs in a division mode, an error detecting circuit 217B supplies an interruption signal to a 2nd interruption terminal of the processor 200. Thus the zero error is processed in terms of interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic error processing method for a programmable controller in which arithmetic data check processing and error pair processing at the time of error detection are performed by separate arithmetic processors.

[0002]

2. Description of the Related Art Programmable controller (hereinafter referred to as PC
The control content executed by (abbreviated as) is roughly classified into sequence control and numerical operation control. Initially, the PC only performed the sequence control (so-called control of bit unit logic of ON / OFF) which is the function of the relay board, but most of the recent PCs have a numerical operation control function (so-called). , Or rather, it controls the quantity in word units), and from the viewpoint of economy, it has also added computer functions such as data processing functions.

Of these, the numerical operation control function is A
There are so-called logical operations represented by ND and OR, and so-called arithmetic operations such as four arithmetic operations. For the purpose of speeding up the control processing of the PC, a second arithmetic processor (comprising an arithmetic circuit) that specializes in arithmetic operations and a first arithmetic processor (CP that executes system control processing).
U) and two are provided to perform parallel processing.

The second arithmetic processor checks whether or not an error has occurred in the arithmetic data or the arithmetic result, and delivers the check result to the first arithmetic processor. For this reason, conventionally, as shown in FIG. 2, a flag information storage circuit 110 is provided between the first arithmetic processor 100 and the second arithmetic processor 120. The flag information is information indicating the presence or absence of an error by 1/0 bit, and is determined for each type of operation.

Conventional processing of addition and division of the four arithmetic operations will be described in detail with reference to FIGS.

FIG. 3 shows an example of a machine language which is roughly divided into an operation code 1 and an operand, and a decoding circuit 2 of an operation code section in the second arithmetic processor 120. As a decoding result, an addition instruction 3 and a division instruction 4 etc. are shown. Are identified and output to the corresponding arithmetic circuit.

The hardware configuration of the add instruction is shown in FIGS.
FIG. 4 shows a generally known two-input one-output adder, which has a carry-out 5 which becomes "1" when a carry is carried. This is the addition instruction 3 and A as shown in FIG.
ND (AND) is made to become the OF (overflow flag) setting condition 6, the clock 7 indicating the end of the instruction is set in the flip-flop 8, and the overflow flag 9 is set. FIG. 8 shows an addition processing flow using these basic hardware configurations. As described above, after executing the addition instruction 15 on the second arithmetic processor 120 side, the first arithmetic processor 100 side confirms 16 the overflow flag 9 corresponding to the adder in the flag information storage circuit 110, and an overflow occurs. If so, the error processing 17 needs to be performed. The error processing 17 at the time of overflow depends on the system, but, for example, the addition result data is rewritten to arbitrary data (for example, all bits are set to “1” or “0”), and the overflow occurrence history is left. Perform error handling.

Next, the processing of the division instruction will be described.
In FIG. 6, the data corresponding to the divider 10 and the division number is “0”.
Zero verification circuit (zero error detection circuit) to verify whether or not
11 is shown. If the number to divide is zero, zero signal 12
Becomes "1". This is the division instruction 4 as shown in FIG.
Is set to the EF (error flag) setting condition 13, which is set in the flip-flop at the clock 7 indicating the end of the instruction and becomes the error flag 14. FIG. 9 shows a division processing flow using these basic hardware configurations. Similarly to the addition instruction, the first processor 100 checks the error flag 14 after executing the division instruction 18 by the second processor 120, and if an error occurs, the error processing 2
Perform 0. The error process 20 is the same as the case of the addition process.

[0009]

In the conventional arithmetic processing,
In order to determine the error in the calculation process and the verification result of the calculation data, it is necessary to confirm the calculation flag on the first calculation processor side, and on the second calculation processor side after the confirmation on the first calculation processor side is completed. , The next arithmetic processing was started, so the high speed execution of sequence arithmetic could not be performed in the entire system.

Therefore, an object of the present invention is to provide an arithmetic error processing method for a programmable controller that does not require confirmation of flags after arithmetic operations.

[0011]

In order to achieve such an object, the invention of claim 1 executes the four arithmetic operations defined by a sequence instruction by a second arithmetic processor and uses the arithmetic operations. When a data error occurs in the data or the arithmetic result of the four arithmetic operations, in the arithmetic error processing method of the programmable controller that performs error-related processing in the first arithmetic processor, when the data error occurs, the second arithmetic operation is performed. An interrupt signal is transmitted from the processor to the first arithmetic processor, and the first arithmetic processor performs the error-related processing in an interrupted manner in response to the input of the interrupt signal.

According to a second aspect of the invention, in addition to the first aspect of the invention, the second arithmetic processor sends a code signal indicating the content of the data error when the interrupt signal is transmitted.
And the first arithmetic processor identifies the content of the error-related processing to be executed from the code signal prior to the error-related processing.

[0013]

The present invention focuses on the fact that when the arithmetic processing is normally performed on the second arithmetic processor side, it is not necessary to confirm the arithmetic flag on the first arithmetic processor side.

Therefore, according to the first aspect of the invention, when the second arithmetic processor detects a data error due to an error in the arithmetic process or a verification result of the arithmetic data, an error signal is executed to the first arithmetic processor by an interrupt signal. Let Therefore, the first arithmetic processor does not need to confirm the flag after the arithmetic operation of the second arithmetic processor.

According to the second aspect of the present invention, since the code signal indicating the content of the data error is given to the first arithmetic processor, a plurality of kinds of error-related processing can be executed by one interrupt signal on the first arithmetic processor side.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a circuit configuration of a second arithmetic processor 210. In FIG. 1, the buffer 21
1 receives a sequence command (calculation command) to be calculated. The decoder 213 identifies the type of sequence instruction,
The selector 212 is instructed to deliver the sequence command to the arithmetic circuits 214A to 217A corresponding to the type.

Error detection circuits 214B, 215B, 21
6B detects an error whether or not the data to be calculated (subtraction data) and / or the data after calculation (addition result, multiplication result) overflow. Error detection circuit 21
7B determines whether or not there is an error whether or not the denominator data is zero.

Error detection circuits 214B, 215B, 21
When an overflow error is detected by 6B, the overflow interrupt signal is sent to the first arithmetic processor (CPU) 2
00 is input to the first interrupt terminal INT1. When the error detection circuit 217B detects a zero error, a zero error interrupt signal is input to the second interrupt terminal INT2.

When an interrupt signal is input to the first interrupt terminal INT1 of the first arithmetic processor 100, the control procedure of FIG. 10B is executed, and the interrupt signal is input to the second interrupt terminal INT2. Then, the control procedure of FIG. 11B is executed.

In such a configuration, the second arithmetic processor receives the sequence instruction and executes the operation indicated by the sequence instruction in the corresponding arithmetic circuit. If no data error occurs, no interrupt signal is input to the first arithmetic processor 200, so the first arithmetic processor 2
00 executes general system processing.

On the other hand, when an overflow error is detected by any of the error detection circuits 214B to 216B, an interrupt signal is input to the first interrupt terminal of the first arithmetic processor 200. As a result, the first arithmetic processor 200 executes the same error processing as the conventional one by the interrupt processing of FIG.

When a zero error occurs during division, an error detection circuit 217B sends an interrupt signal to the second interrupt terminal of the first arithmetic processor 200. Therefore, the first arithmetic processor 200 interrupts the error processing corresponding to the zero error according to the procedure of FIG.

In addition to this embodiment, the following example can be carried out.

<Second Embodiment> In the above embodiment, two interrupt signals are provided corresponding to two types of error processing.
In the case where the first arithmetic processor executes the process of merely warning that an error has occurred, only one interrupt signal is required. FIG. 12 shows an example of a circuit for generating an interrupt signal.

In FIG. 12, the second arithmetic processor 21
When the addition circuit selection signal ADD of 0 and the overflow error detection signal carryout for the addition circuit are both generated, or when the division circuit selection signal div and the zero error detection signal zerodedetect are both generated, the latch 21 performs the first operation. An interrupt signal “interrupt” is sent to the processor 200. The first arithmetic processor 200 interrupts error processing by this interrupt signal.

<Third Embodiment> First arithmetic processor 200
FIG. 13 shows a third embodiment in which only one interrupt signal is supplied to the first arithmetic processor to inform the first arithmetic processor of the kind of error.

In FIG. 13, the second arithmetic processor 21
The latch 21 of 0 generates an interrupt signal interrupt to the first arithmetic processor 200 when a data error occurs in either the adder or the divider. The latch 23 latches the data error detection signal of the arithmetic unit in which the error has occurred, and turns on the level of the corresponding output signal of q1 or q2.
The first arithmetic processor 200 uses the interrupt signal interrup
In response to the input of t, the control procedure of FIG. 14 is executed in an interrupted manner. That is, the output of the latch 23 is read, the error content is identified from the code indicated by the output (step 26), and the corresponding error processing is executed.

<Fourth Embodiment> The third embodiment has two arithmetic circuits.
For example, when the second arithmetic processor has a large number of arithmetic circuits, as shown in FIG. 15, the error detection signal group is decoded by the decoder 24 to generate a code signal indicating the error content, and the latch 23 is generated. It is good to output from.

In addition to the above embodiment, the following example can be implemented.

1) In the present embodiment, an example in which the second arithmetic processor is composed of a plurality of arithmetic circuits has been shown, but the present invention can be applied to a processor which performs arithmetic by software. In this case, after the second arithmetic processor detects the data error, it activates the interrupt signal generating circuit as shown in FIGS. 12, 13, and 15 to cause the first arithmetic processor to execute the interrupt processing.

[0032]

As described above, according to the present invention, there is no need for the processing for confirming the presence or absence of a data error, which is conventionally required on the side of the first arithmetic processor, and the data error presence / absence information is transferred. Since a flag storage circuit for doing so is unnecessary, it is possible to contribute to speeding up and simplification of the programmable controller.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a conventional example.

FIG. 3 is a circuit diagram showing a partial configuration of a second arithmetic processor of a conventional example.

FIG. 4 is a circuit diagram showing a partial configuration of a second arithmetic processor of a conventional example.

FIG. 5 is a circuit diagram showing a partial configuration of a second arithmetic processor of a conventional example.

FIG. 6 is a circuit diagram showing a partial configuration of a second arithmetic processor of a conventional example.

FIG. 7 is a circuit diagram showing a partial configuration of a second arithmetic processor of a conventional example.

FIG. 8 is a flowchart showing a conventional arithmetic processing procedure.

FIG. 9 is a flowchart showing a conventional arithmetic processing procedure.

FIG. 10 is a flowchart showing a calculation processing procedure according to the embodiment of the present invention.

FIG. 11 is a flowchart showing a calculation processing procedure according to the embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of an interrupt signal generation circuit of a second embodiment.

FIG. 13 is a block diagram showing a configuration of an interrupt signal generation circuit according to a third embodiment.

FIG. 14 is a flowchart showing an interrupt processing procedure of the first arithmetic processor of the third embodiment.

FIG. 15 is a block diagram showing a configuration of an interrupt signal generation circuit of a fourth embodiment.

[Explanation of symbols]

 100,200 1st arithmetic processor 110,210 2nd arithmetic processor

Claims (2)

[Claims] 1. When the second arithmetic processor executes the four arithmetic operations defined by the sequence instruction and a data error occurs in the data used for the four arithmetic operations or the arithmetic result of the four arithmetic operations, the first arithmetic processor. In the arithmetic error processing method for a programmable controller that performs error-related processing, when the data error occurs, an interrupt signal is transmitted from the second arithmetic processor to the first arithmetic processor, and the first arithmetic operation is performed. The arithmetic error processing method for a programmable controller, wherein the processor performs the error-related processing in an interrupted manner in response to the input of the interrupt signal. 2. The second arithmetic processor sends a code signal indicating the content of the data error to the first arithmetic processor when the interrupt signal is transmitted, and the first arithmetic processor processes the error-related processing. 2. The arithmetic error processing method for a programmable controller according to claim 1, wherein the contents of error-related processing to be executed are identified from the code signal prior to the above.