JPH06253552A - Load communication type inverter - Google Patents

Abstract

PURPOSE:To enhance operability by actuating a starting circuit based on AND conditions of commutation failure and commutation margin time while sustaining operation of converter without tripping an inverter for a commutation failure due to variation of load impedance at the time of abrupt variation of load thereby operating the inverter again. CONSTITUTION:A commutation margin time detecting circuit 6 comprising a resistor 6a and a photocoupler 6b is connected between P, N terminals of a DC circuit. A detected commutation margin time is compared with a reference value in order to detect deficiency of commutation margin time thus permitting restart when AND condition of commutation failure detection and commutation margin time defficiency is, satisfied. Subsequently, U and Y phase gate pulses and a restart pulse for an inverter 3 are generated based on AND conditions of a bypass pair state signal for the inveter 3 and the gate pulses for U and Y phases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load commutation type inverter device, and more particularly to a load commutation type inverter device which is restarted when commutation fails to improve the operation rate. .

[0002]

2. Description of the Related Art FIG. 7 is a main circuit diagram of a conventional load commutation type inverter device.

In the figure, 1 is a forward converter, 2 is a DC reactor, 3 is an inverse converter constituted by a bridge connection of thyristors 3U to 3Y, 4 is a starting circuit which operates only when the inverter is started, and 5 is a parallel circuit. With resonance load.

The start-up circuit 4 operates by rectifying the separate power source 4h by the rectifier 4e and charging the precharge capacitor 4c. The start-up thyristor 4a discharges the electric charge of the precharge capacitor 4c, which is fired by the start-up signal and completed charging, to the inverse converter 3
And the parallel resonance load 5 is discharged. Next, the activation of the load commutation type inverter device will be described with reference to FIG.

At the same time as applying an ignition signal to the forward converter 1, all the thyristors 3U to 3Y of the inverse converter 3 are ignited (hereinafter, this state is referred to as BPP), and the current flowing through the DC reactor 2 reaches a predetermined value. When it starts up, the charge of the precharge capacitor 4c, which has ignited the start-up thyristor 4a of the start-up circuit 4 and completed the charging, is transferred to the inverse converter 3 and the parallel resonance load 5
To discharge against.

For the inverse converter 3, the precharge capacitor 4c → thyristor 3Y → thyristor 3X → start thyristor 4a → reactor 4b → precharge capacitor 4c and precharge capacitor 4c → thyristor 3
V → thyristor 3U → starting thyristor 4a → reactor 4b → precharge capacitor 4c discharge loop is formed, and thyristors 3V and 3X of the inverse converter 3 are reverse biased and turn off. By pouring a direct current into the parallel resonant load 5, a high frequency voltage is induced in the parallel resonant load 5 and the parallel resonant load 5 starts oscillating. This completes the startup of the inverter device.

As the parallel resonant load 5, a high frequency induction furnace,
There is a high-frequency heater, but it is known that the load impedance fluctuates greatly when the material to be melted is put into the furnace, or when the material to be melted flows into and out of the coil, at any load. . In order to ensure stable continuous operation of the inverter device, it is sufficient to grasp the change width of the commutation overlap angle during load change described above in advance so that commutation failure does not occur even when the load changes suddenly. It is desirable to have a sufficient time for commutation.

However, if a sufficient commutation margin time is secured against load fluctuations, the power factor of the inverter device decreases and it becomes uneconomical. During low impedance due to a sudden sudden change in load, commutation failure occurs due to a shortage of commutation margin time due to a sharp increase in commutation overlap angle. In the case of the conventional example, in this case, the commutation failure is detected and the inverter device is stopped by tripping.

[0009]

In the conventional example, when the inverter device is tripped due to a commutation failure during a sudden load change, the system is temporarily stopped, and the inverter device is switched to the inverter device due to a commutation failure in order to prevent the accident from spreading. Since the system is restarted after investigating whether or not any abnormality has occurred, there is a drawback that a loss time occurs from the system stop to the restart, resulting in a decrease in operating rate.

Therefore, according to the present invention, when the load changes suddenly and the commutation failure due to the load impedance change does not cause the inverter device to trip, the forward converter keeps operating and the commutation failure occurs. An object of the present invention is to provide a load commutation type inverter device which can eliminate the above-mentioned drawbacks by operating the starter circuit under the AND condition of insufficient commutation margin time and restarting the operation.

[0011]

In order to achieve the above object, an inverse converter for converting direct-current power of a forward converter according to claim 1 of the present invention into alternating-current power and supplying alternating-current power to a parallel resonant load in advance. The load commutation type inverter device provided with a precharge capacitor that is charged from another power source and discharges the charged electric charge to the inverse converter by igniting the starting thyristor to release the bypass pair state, is the inverse converter. Means for detecting a commutation failure, a means for detecting a commutation margin time shortage of the inverse converter, both means operating, and the inverse converter being in a bypass pair state, the inverse conversion And a means for generating a gate pulse and a restart pulse synchronized with the gate pulse of the device, the restart pulse being supplied to the starting thyristor, and the gate pulse being supplied to the inverse converter. Ah .

In order to achieve the above object, the reverse converter for converting the DC power of the converter into the AC power and supplying the AC power to the parallel resonance load according to the second aspect of the present invention, and the charging in advance from another power source. A load commutation type inverter device equipped with a precharge capacitor that discharges the charged electric charge to the inverse converter by firing the starting thyristor and releases the bypass pair state is a commutation failure of the inverse converter. Of the reverse converter by the means for detecting, and the fact that the predetermined time has elapsed after the operation of the means and the reverse converter is in a bypass pair state.
A means for generating a restart pulse and a gate pulse synchronized with the gate pulse is provided, and the restart pulse is given to the start thyristor and the gate pulse is given to the inverse converter.

Further, in order to achieve the above object, a load commutation type inverter device according to claim 3 of the present invention comprises at least the restart pulse and the gate pulse according to claim 1 or 2. It is characterized in that it is provided with commutation margin time forced expansion means for forcibly advancing for a fixed time period in accordance with the output of the flow failure detection means.

[0014]

According to the first aspect of the present invention, if the reverse converter fails in commutation due to lack of commutation margin time, means for detecting failure in the reverse converter and commutation in the reverse converter. Both of the means for detecting the shortage of spare time operate. At this time, since the inverse converter is in the bypass pair state, a restart pulse and a gate pulse synchronized with the gate pulse of the inverse converter are generated,
By applying the restart pulse to the start thyristor, the charge of the precharge capacitor is changed to the thyristor 3 of the inverse converter.
Since V and 3X are discharged in the reverse bias direction, BPP
The gate pulse generated at the same time as the restart pulse is given to the thyristors 3U and 3Y of the inverse converter.
The operation can be restarted without stopping the operation device.

According to the second aspect of the present invention, most of the commutation failure of the inverse converter is caused by the lack of commutation margin time. If the reverse converter fails to commutate without providing any means for detection,
If the means for detecting the commutation failure of the inverse converter operates, at this time, the restart pulse and the gate pulse synchronized with the gate pulse of the inverse converter are generated because the inverse converter is in the bypass pair state. However, by giving a restart pulse to the start thyristor, the charge of the precharge capacitor discharges the thyristors 3V and 3X of the reverse converter in the direction of reverse biasing, so that BPP is released and it occurs at the same time as the restart pulse. The gate pulse is the thyristor 3U of the inverse converter,
Since it is applied to 3Y, restarting is possible without stopping the inverter device if commutation fails.

Further, according to the invention of claim 3, in the invention of claim 1 or the invention of claim 2 in which the inverter device is restarted due to a commutation failure, a restart pulse and a gate are further added. -Providing a commutation margin time compulsory expansion means for forcibly advancing the gate pulse at least for a fixed time period according to the output of the commutation failure detection means, and advancing the gate pulse of the inverse converter for a predetermined time at restart, It is possible to prevent commutation failure that may occur repeatedly.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. 1, 2 and 3.

FIG. 1 is a block diagram of a main circuit of a load commutation type inverter device showing an embodiment of the present invention. Components having the same functions as those of the conventional example shown in FIG. The description is omitted. FIG. 2 is a control block diagram showing an embodiment of the present invention from detection of commutation failure to restart.

FIG. 3 shows the waveform of each part of FIG. 2 for explaining the operation of the present invention. FIG. 1 shows a load commutation type inverter device of a conventional example, in which a commutation margin time detection circuit 6 including a resistor 6a and a photo coupler 6b is added between PN of the DC circuit of FIG. The switch 4f is deleted so that the di-capacitor 4c can be constantly charged, and a starting thyristor 4j is added so that the output voltage of the inverter device is not superimposed on the pre-charge capacitor 4c.

The operation from commutation failure to restart will now be described with reference to FIGS. The commutation margin time 7e is detected by the photo coupler 6b in FIG. 2 and 3
From the gate pulse 7d of the inverse converter 3 to the on-delay 7f
Thus, the time is delayed by a time corresponding to the maximum commutation overlap time during the preset operation of the apparatus, and the commutation margin time reference value 7g is set up to the zero point of the next waveform. The gate pulse 7d 'of the inverse converter 3 is a black pulse in FIG. 3, and is a pulse given to the thyristors 3U and 3Y forming the inverse converter 3.

Commutation margin time reference value 7 g and commutation margin time 7
Comparing e, commutation margin time reference value 7g> commutation margin time 7
In the case of e, the commutation margin time shortage detection 7h is performed. At this time, A of commutation failure detection 7j and commutation margin time shortage detection 7h
When the ND condition is satisfied, the restart is permitted by a signal (not shown).

When the restart is permitted, the BPP status signal 7
k and U of the inverse converter 3 and AN of the Y-phase gate pulse 7d '
Uy phase gate pulse 7m to the inverse converter 3 depending on D condition
Then, a restart pulse 7l is generated.

Since the restart pulse 7l is given to the start thyristors 4a and 4j of the start circuit 4, the inverse converter 3 which has already been in the BPP 7k due to the commutation failure is released from the BPP by the restart pulse 7l. On the other hand, at the same time, the inverse converter 3 is restarted by the UY phase gate pulse 7m to the inverse converter 3.

FIG. 4 is a control block diagram from commutation failure to restarting, showing the essential parts of another embodiment of the present invention. Further, FIG. 5 is a waveform for explaining the operation of the embodiment of FIG.

When a commutation failure 7j occurs in the load commutation type inverter device shown in FIG. 1, restarting is permitted by a signal (not shown) after a time delay without the condition of insufficient commutation margin time. . If restart is allowed, BPP status signal 7
k and U of the inverse converter 3 and AN of the Y-phase gate pulse 7d '
According to the D condition, a gate pulse 7m is given to the U-phase thyristor 3U and the Y-phase thyristor 3Y of the inverse converter 3, and in synchronization with this, the restart pulse 7l is supplied to the start thyristors 4a, 4a of FIG.
The reverse converter 3 which has formed the BPP due to the commutation failure is released from the BPP and the inverter is restarted.

In this embodiment, when the commutation failure is detected, the restart is started after the time delay. Therefore, the power factor is restarted without expanding the commutation margin time against a transient load change. You can drive well, and there is no loss of operation due to trips. FIG. 6 is a control block diagram from commutation failure to restarting, showing the essential parts of still another embodiment of the present invention.

When a commutation failure occurs in the load commutation type inverter device of FIG. 1, commutation failure detection 7j or commutation margin time shortage detection 7h causes a predetermined time and commutation margin time to be forced from that point. The expansion is operated to advance the gate pulse 7d of the inverse converter 3. As a result, at the time of restart, U of the inverse converter 3
The gate pulse 7m given to the phase thyristor 3U and the Y-phase thyristor 3Y also advances, and the commutation margin time can be extended for a fixed time period at the time of restart.

If the load pattern resulting from the operation method has a lower impedance than the normal load pattern, commutation failure may occur repeatedly, so this embodiment should be used. In the case where the commutation fails once, the commutation margin time is forcibly expanded for a certain period of time to prevent repeated commutation failures.

[0029]

As described above, according to the first aspect of the present invention, in a high frequency induction furnace in which a load commutation type inverter is often used, when the molten material burns down or the material is charged into the furnace. Even if the commutation fails due to a temporary sudden load change, such as during operation, the system can be operated without stopping.

According to the second aspect of the present invention, it is also possible to unconditionally restart by commutation failure when commutation fails without providing commutation margin shortage detection means. Furthermore, according to the present invention of claim 3, when it is known in advance that the impedance of the furnace has a low impedance unlike the normal melting, such as during sintering and melting of the furnace, the commutation margin If the time compulsory expansion means is provided, the commutation margin time is widened when the commutation failure is restarted, and the second commutation failure does not occur, so that the system can be operated stably without stopping.

From the above, when commutation fails, the inverter does not trip and stop as in the conventional case.
Lost time due to stoppage and lost time required for system inspection and investigation at the time of trip are eliminated, so the operating rate can be improved.

[Brief description of drawings]

FIG. 1 is a main circuit configuration diagram showing an embodiment of a load-load commutation type inverter device according to the present invention.

FIG. 2 is a control block diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of [FIG. 2].

FIG. 4 is a control block diagram showing a main part of another embodiment of the present invention.

FIG. 5 is a waveform diagram for explaining the operation of [FIG. 4].

FIG. 6 is a control block diagram showing a main part of still another embodiment of the present invention.

FIG. 7 is a main circuit configuration diagram of a conventional load-load commutation type inverter device.

[Explanation of symbols]

 1 ... Forward converter 2 ... DC reactor 3 ... Inverse converter 4 ... Start-up circuit 4a, 4j ... Start-up thyristor 4b ... Reactor 4c ... Precharge capacitor 4d, 4g ... Resistor 4e ... Rectifier 4h ... Separate power supply 5 ... Parallel resonant load 6 ... Photo coupler

Claims (3)

[Claims] 1. A reverse converter for converting direct current power of a forward converter into alternating current power to supply alternating current power to a parallel resonant load, and an inverse converter charged in advance from another power source to ignite a starting thyristor to reverse the charged electric charge. In a load commutation type inverter device equipped with a precharge capacitor that discharges the converter and releases the bypass pair state, a means for detecting a commutation failure of the inverse converter and a commutation margin of the inverse converter. The means for detecting the shortage of time, the operation of both the means, and the fact that the inverse converter is in the bypass pair state, the gate of the inverse converter is detected.
Load commutation type, characterized in that it comprises means for generating a restart pulse and a gate pulse synchronized with the gate pulse, and applying the restart pulse to the starting thyristor and applying the gate pulse to the inverse converter. Inverter device. 2. A reverse converter for converting direct current power of a forward converter into alternating current power to supply alternating current power to a parallel resonant load, and an inverse converter which is charged in advance from another power source to ignite a starting thyristor to reverse the charged electric charge. In a load commutation type inverter device equipped with a precharge capacitor that discharges the converter and releases the bypass pair state, means for detecting a commutation failure of the inverse converter and a predetermined time after the means operates. Since it has elapsed and the inverse converter is in the bypass pair state, the restart pulse and the gate synchronized with the gate pulse of the inverse converter are obtained.
A load commutation type inverter device comprising means for generating a gate pulse, the restart pulse being supplied to the starting thyristor, and the gate pulse being supplied to the inverse converter. 3. The restart pulse and the gate pulse are timed at least for a certain period according to the output of the commutation failure detection means,
3. The load commutation type inverter control device according to claim 1, further comprising commutation allowance time forced expansion means for forcibly advancing.