JPH06252888A - Non-coherent delay lock loop - Google Patents

Abstract

PURPOSE:To simplify a circuit configuration without need of a differential amplifier and to improve the performance of a phase locked loop by eliminating a synchronization component. CONSTITUTION:Rectifiers 1, 2 rectify a signal into different sign voltage such that positive voltage rectification by the rectifier 1 and negative voltage rectification by the rectifier 2. A correlation signal inputted to the rectifier 1 is rectified and smoothed by a smoothing circuit 3 and inputted to an adder 5. Similarly a correlation signal inputted to the rectifier 2 is rectified and smoothed by a smoothing circuit 4 and inputted to the adder 5. Thus, the smoothing circuits 3, 4 form output signals of different sign, it is not required to make subtraction and a difference of the amplitudes of the two correlation signals is extracted through addition.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a non-coherent delay locked loop, and more particularly to a non-coherent delay locked loop as a synchronizing circuit for pseudo noise (PN) signals in spread spectrum communication. For example, it is applied to wireless communication.

[0002]

2. Description of the Related Art In spread spectrum communication, a transmission system spreads an information signal by a pseudo noise signal (PN signal) and transmits it. The receiving system is a communication system that receives this signal and despreads it with the same PN signal as the PN signal used in the transmitting system to demodulate information. In this communication system, it is necessary for the receiving system to generate a PN signal that is in phase with the PN signal included in the received signal. Therefore, a synchronous circuit called a noncoherent delay locked loop is usually used.

FIG. 9 is a block diagram of a conventional noncoherent delay locked loop, and particularly shows an IΔ type noncoherent delay locked loop. In the figure, 11 to 14 are multipliers (mixers), and 15 and 16 are bandpass filters (B).
PF), 17 and 18 are envelope detection circuits, 19 is an adder,
Reference numeral 20 is a voltage control clock (VCC), 21 is a local oscillator, 22 is a loop filter (LF), and 23 is a PN signal generator. The PN signal generator 23 has a PN signal (on time signal) serving as a reference and a PN signal (early signal) advanced in phase by 1/2 chip, and the on time signal and 1/2 chip. Only the phase sent PN
Generates a signal (late signal). Mixer 11-
14 serves to multiply the two signals. The local oscillator 21 generates an oscillation signal for dropping to an intermediate frequency.

Next, the operation will be described. The PN signal generator 23 is driven by the clock signal from the voltage control clock 20 to generate an early signal and a late signal. The early signal generated from the PN signal generator 23 is multiplied by the mixer 11 with the oscillation signal of the local oscillation signal 21. Further, the mixer 13 multiplies the received signal and the band-pass filter 15 so as to obtain the correlation between the received signal and the early signal. When there is a correlation between the received signal and the early signal, a signal having a certain amplitude is obtained, and when there is no correlation, the signal cannot be obtained. Similarly, the rate signal is also multiplied by the oscillation signal generated by the local oscillation signal 21 in the mixer 12. Further, the mixer 14 multiplies the received signal and the band-pass filter 16 so as to obtain the correlation between the received signal and the late signal. When there is a correlation between the received signal and the late signal, a signal having a certain amplitude is obtained, and when there is no correlation, the signal cannot be obtained.

As described above, when the phase of the PN signal generated in the synchronizing circuit leads the PN signal of the received signal, the bandpass filter 15 outputs a correlation signal,
If it is delayed, it is output from the bandpass filter 16. Envelope detectors 17 and 18 extract these two signals from the amplitude component of the correlation output, subtractor 19 takes the difference, and inputs the difference as a control signal for voltage control clock 20 to form a synchronous circuit. is doing.

In a conventional DLL (Delay Locked Loop),
In order to obtain the control signal of the voltage control clock, envelope detection of two correlation signals is performed, and further, two detection outputs are input to a differential amplifier circuit such as an operational amplifier to perform subtraction. FIG. 10 is a configuration diagram of an envelope detection unit and a subtractor of a conventional delay locked loop. D1 and D2 are diodes, R1 and R2 are resistors, C1 and C2 are capacitors, and E1 is an operational amplifier. The signal rectified by the diode D1 is smoothed by the smoothing circuit composed of the resistor R1 and the capacitor C1, and the amplitude component is extracted. Similarly, the signal rectified by the diode D2 is smoothed by the resistor R2 and the capacitor C2, and the amplitude component is extracted. The difference between these amplitude components is extracted by the operational amplifier E1. in this way,
Since the conventional circuit requires a differential amplifier circuit, the circuit becomes complicated, and when the frequency of the input signal becomes higher, the CMRR (common mode rejection ratio) of the operational amplifier deteriorates, that is, the in-phase of the two signals. There was a defect that the components were output.

[0007]

[Object] The present invention has been made in view of the above-mentioned circumstances, and the output of one correlator is output as a positive signal and the output of the other correlator is output as a negative signal. The difference between the two correlator components is taken out by adding them together, the circuit is simplified without the need for a differential amplifier, and the in-phase component is prevented from being output. Incorporation of two diodes compensates each other for stable detection with respect to temperature. In addition to temperature compensation by two transistors, the operating point of the transistors is shifted to eliminate detection loss. In addition, since two transistors with uniform characteristics are used, they should be temperature-compensated with each other, and stable operation against temperature changes should be expected. It is possible to apply the same bias to the bases of the two transistors so that the loss due to the detection can be reduced. Furthermore, since the detection circuit was conventionally composed of a passive circuit, the detection output is attenuated. Although there was a drawback such as doing so, configuring a grounded emitter amplifier circuit of the transistor so that the detection output can be amplified and obtained,
Since it is necessary to add only the positive (or negative) control signal to the voltage control clock of the synchronous circuit, conventionally, after detecting the correlation signal and taking the difference, add the offset voltage and then add it to the voltage control clock. Although the signals were input, one of the correlation signals was rectified and an offset voltage was added, and the other of the correlation signals was rectified only, and these two rectified signals were added.
The purpose of the present invention is to provide a non-coherent delay locked loop that eliminates the need for a circuit that adds an offset voltage after the addition circuit of two signals, simplifies the circuit configuration, and keeps the cost low. is there.

[0008]

In order to achieve the above object, the present invention provides (1)
In a spread spectrum communication receiving system, a pseudo noise signal whose phase is advanced within 1 chip from a reference pseudo noise signal (PN signal) and a pseudo noise signal whose phase is delayed within 1 chip from the reference pseudo noise signal A multiplier that multiplies each with the received signal, a bandpass filter that obtains a correlation signal from the output of the multiplier, one takes out the positive component of the correlation signal and smoothes it, and the other one negative component of the correlation signal. Is taken out and smoothed, and each is added, and a signal component of the difference between the two correlation outputs is taken out by the adder, the signal is input as a control signal, and the voltage control for driving the pseudo noise signal generation circuit is performed. And (2) the anode side of the first diode (D1) is the input end of one correlation signal, and the cathode side is grounded at one end. A smoothing circuit composed of a first capacitor (C1) and a first resistor (R1) whose one end is grounded is connected, and the cathode side of the second diode (D2) serves as an input end of one correlation signal and the anode side. Is connected to a smoothing circuit composed of a second capacitor (C2) whose one end is grounded and a second resistor (R2) whose one end is grounded, and further connected to the cathode end of the first diode (D1) and The circuit in which the anode end of the second diode (D2) is connected to the adding circuit is used as the envelope detection circuit and the subtracting circuit, and (3) the first NPN type transistor (Q
The base of 1) is biased to a positive voltage by the base-emitter voltage, and the first coupling capacitor (C3)
Becomes the input terminal of the correlation signal via the collector, the collector receives the voltage supply from the positive voltage source, and the emitter has the first capacitor (C1) whose one end is grounded and the first resistor (R1) whose one end is grounded. And a smoothing circuit consisting of
The base of the P-type transistor (Q2) is biased to a negative voltage by the base-emitter voltage, becomes the input terminal of the correlation signal via the second coupling capacitor (C4), and the collector is from the negative voltage source. Upon receiving the voltage supply, the emitter is connected to a smoothing circuit including a second capacitor (C2) whose one end is grounded and a second resistor (R2) whose one end is grounded, and further, the emitter of the first transistor (Q1) is connected. Using a circuit in which the emitter and the emitter of the second transistor (Q2) are connected to an adding circuit as an envelope detection circuit and a subtracting circuit, or (4) a pseudo reference that is used as a reference in a spread spectrum communication receiving system. Noise signal (PN signal)
From the output of the multiplier and the multiplier that multiplies the received signal by each of the pseudo noise signal whose phase is advanced within 1 chip and the pseudo noise signal whose phase is delayed within 1 chip from the reference pseudo noise signal A bandpass filter for obtaining a correlation signal, one for extracting and smoothing the positive component of the correlation signal, the other for extracting and smoothing the negative component of the correlation signal, and an adder for adding each and a In the non-coherent delay locked loop, the signal component of the difference between the two correlation outputs is extracted, the signal is input as a control signal, and a voltage control clock for driving the pseudo noise signal generation circuit is used. NPN
-Type transistor (Q1) has its emitter grounded, and its base has a resistor (R10) connected between its collector and base to allow a base current to flow to such an extent that a collector current hardly flows, and a resistor (R11) and a coupling capacitor. It becomes an input terminal of the first correlation signal via (C3), the collector is connected to the positive voltage source via the resistor (R9),
Further, a smoothing circuit composed of a resistor (R1) whose one end is grounded and a capacitor (C1) whose one end is grounded is connected,
The emitter of the second PNP type transistor (Q2) is grounded, and the base of the second PNP transistor (Q2) is connected to between the collector and the base (R13) so that the base current flows to the extent that almost no collector current flows. Via the coupling capacitor (C4) to the input end of the second correlation signal, the collector is connected to the negative voltage source via the resistor (R14), and one end is grounded to the resistor (R2). Is connected to a smoothing circuit composed of a capacitor (C2) grounded, and an adder circuit for adding the collector voltage of the first transistor and the collector voltage of the second transistor is used as an envelope detection circuit and a subtraction circuit. Further, (5) the emitter of the first NPN transistor (Q1) is grounded through the resistor (R16), and the base is the base. Only the voltage between the emitters is biased to a positive voltage, becomes the input terminal of the first correlation signal via the first coupling capacitor (C3), and the collector is connected to the positive voltage source via the resistor (R15). Further, a capacitor (C1) whose one end is grounded is connected, and the emitter of the second PNP type transistor (Q2) has a resistor (R
18), grounded, the base biased to a positive voltage by the base-emitter voltage, the second coupling capacitor (C3) through which the second correlation signal is input, and the collector (R18). ) To a negative voltage source, and one end of which is grounded (C
2) is connected, and the adder circuit for adding the collector voltage of the first transistor and the collector voltage of the second transistor is used as an envelope detection circuit and a subtraction circuit, and further, (6) the first The NPN-type transistor (Q1) has its emitter grounded via the resistor (R16), its base biased to a positive voltage by the base-emitter voltage, and the first via the first coupling capacitor (C3). Of the second PNP type transistor (Q2), the collector of which is connected to the positive voltage source through the resistor (R15), and the capacitor (C1) whose one end is grounded is connected. The emitter of is a resistor (R
18), grounded, the base biased to a positive voltage by the base-emitter voltage, the second coupling capacitor (C3) through which the second correlation signal is input, and the collector (R18). ) Is connected to a negative voltage source, and one end of which is grounded (C
2) is connected, and an adding circuit for adding the collector voltage of the first transistor and the collector voltage of the second transistor is used as an envelope detection circuit and a subtraction circuit. Hereinafter, description will be given based on examples of the present invention.

FIG. 1 is a block diagram for explaining an embodiment (claim 1) of a non-coherent delay locked loop according to the present invention. In the figure, 1 and 2 are rectifier circuits and 3 and 4 are smoothing circuits. Reference numeral 5 is an adder circuit. For example, if the rectifier circuit 1 rectifies to a positive voltage, the rectifier circuit 2 rectifies to a negative voltage, and the rectifiers 1 and 2 are rectified to voltage sides having different signs.

Next, the operation will be described. The correlation signal input to the rectifier 1 is rectified, smoothed by the smoothing circuit 3, and input to the adder 5. Assuming that the input correlation signal is as shown in FIG. 4A, the signals at A and C in FIG.
The waveforms shown in FIGS. 4B and 4D are obtained. Similarly, the correlation signal input to the rectifier 2 is rectified, smoothed by the smoothing circuit 4, and input to the adder 5. Assuming that the input correlation signal is as shown in FIG. 4A, the signals at B and D in FIG.
The waveforms shown in FIGS. 4C and 4E are obtained. Therefore, since the output waveforms of the smoothing circuits 3 and 4 are output signals having mutually different signs, there is no need to perform subtraction, and the difference between the amplitudes of the two correlation signals can be extracted by adding.

Next, claim 2 will be described. Figure 2
Shows a circuit configuration diagram when a diode is used for the rectifier. D1, D2 are diodes, R1, R2, R
3 and R4 are resistors, and C1 and C2 are capacitors.

Next, the operation will be described. The diode D1 performs half-wave rectification for outputting a positive signal component of the input correlation signal. A smoothing circuit is configured by C1 and R1, and the rectified signal from the diode D1 is smoothed. Similarly, the diode D2 performs half-wave rectification for outputting a negative signal component, and C2 and R2 smooth the signal. As an adder, here 2
It is composed of two resistors R3 and R4. If the values of R3 and R4 are sufficiently larger than the values of R1 and R2, they function as an adder. Therefore, the two smoothed signals are added by R3 and R4 and output as a control signal. Further, at this time, the diode D1 and the diode D2 compensate each other for temperature, so that the diode becomes stable with respect to temperature.

Next, claim 3 will be described. Figure 3
FIG. 3 is a diagram showing an example in which claim 1 is configured by using a transistor. Q1 is an NPN transistor, Q2 is a PN
It is a P transistor. R5, R6, R7 and R8 are resistors, and C3 and C4 are capacitors. In the figure, parts having the same functions as those in FIG. 2 are designated by the same reference numerals.

Next, the operation will be described. 2 is different from the operation in FIG. 2 in the rectifying portion, so only the rectifying portion will be described. The base of the transistor Q1 is connected to the base-emitter voltage V _BE1 (usually _0.5 V) by R5 and R6.
The bias voltage is set to a voltage as high as 6 to 0.7 V). C3 is a coupling capacitor, which is cut off from the correlation signal input terminal in terms of direct current. Transistor Q1
_Does not operate unless a voltage higher than V _BE1 is applied to the base, so that only the positive signal component of the input correlation signal appears on the emitter side and rectification is performed.

Similarly, on the side of the transistor Q2, the base potential is set to the base-emitter voltage V by the resistors R7 and R8.
Only _BE2 is set to a voltage lower than the ground level. And by the coupling capacitor of C4,
It is cut off from the correlation signal input terminal in terms of direct current. Therefore, only the negative signal component of the input signal appears on the emitter side and rectification is performed. In the circuit of FIG. 2, the diode reduces the correlation signal due to the forward voltage drop, but in the case of this circuit, since the base potential is biased, the effect of the voltage drop due to the base-emitter voltage of the transistor can be reduced. There is an advantage. Further, when the correlation signal input in the circuit of FIG. 2 becomes small, there is signal distortion due to the nonlinearity of the diode, but the circuit of FIG. 3 has an advantage that the distortion becomes small.

Next, claim 4 will be described. Figure 5
[Fig. 6] is a diagram showing a configuration example of the circuit of claim 4. Q in the figure
Reference numeral 1 is an NPN type transistor, and Q2 is a PNP type transistor. C1, C2, C3, C4 are capacitors, R1, R2, R3, R4, R9, R10, R1
Reference numerals 1, R12, R13, and R14 are resistors, and other parts having the same functions as those in FIG. 3 are denoted by the same reference numerals.

Next, the operation will be described. In this circuit, a transistor Q1 and a transistor Q2 each form a grounded-emitter amplifier having a voltage feedback type bias circuit. In the transistor Q1, a positive voltage is applied to the base by the bias resistor R10. At this time, the resistance R10 is set so that the base current I _B1 hardly flows.
Is set. Therefore, when the correlation signal input through the coupling capacitor C3 and the resistor R11 is positive, the transistor Q1 causes about R10 / R1.
It is multiplied by 1 and output to the collector side. When the correlation signal is negative, the base potential becomes lower than the base-emitter potential, so that the transistor Q1 is cut off. Therefore, an inverting and amplified half-wave rectified signal having a positive offset by the collector-emitter voltage appears at the collector. The half-wave rectified signal is smoothed by the resistor R9 and the capacitor C1.

Similarly, in the transistor Q2, a negative voltage is applied to the base by the bias resistor R12. At this time, the resistor R13 is set so that the base current I _B2 hardly flows. Therefore, like the transistor Q1, the inverted amplified half-wave rectified signal having a negative offset by the collector-emitter voltage appears at the collector of the transistor Q2. At this time, the rectified signal is smoothed by the resistor R14 and the capacitor C2.

The collector outputs of the transistors Q1 and Q2 are added by an adder circuit composed of resistors R3 and R4. At this time, if the collector-emitter voltage of the transistor Q1 and the collector-emitter voltage of the transistor Q2 are equal in magnitude, they cancel each other out, and the signal from this adder circuit outputs a component of the difference in amplitude between the correlation signals. It will be. This example is shown in FIG.
A description will be given using (a) to (f). The correlation signal input to the transistor Q1 is E, and the correlation signal input to the transistor Q2 is L. Here, the case where correlation signal E> correlation signal L is considered. The correlation signal E is shown in FIG.
The correlation signal L is shown in FIG. The collector potential of the transistor Q1 has the waveform shown in FIG. 8C, and the collector potential of the transistor Q2 has the waveform shown in FIG. 8D. Therefore, the sum of these two potentials cancels each other out if the collector-emitter voltage has the same magnitude and the sign is different.
A difference component of the amplitude of the correlation signal remains as in (e). In this configuration example, the voltage feedback type bias circuit is used, but of course, the bias circuit may be configured using a fixed bias circuit (a circuit that applies a bias voltage to the base by a resistor directly from a voltage source).

Next, claim 5 will be described. Also,
Although the voltage feedback type bias circuit is used in the fourth aspect, it can be realized by using a current feedback type bias circuit. An example of this configuration is shown in FIG. In the figure, portions having the same functions as those in FIG. 5 are designated by the same reference numerals. R5, R6, R
8, R7, R15, R16, R17 and R18 are all resistors. Since the point different from claim 4 is how to apply the bias, only this part will be described. Transistor Q1
Then the base-emitter voltage V is generated by the resistors R5 and R6.
It is biased to a voltage as high as _BE1 (usually 0.6-0.7V). Since the transistor Q1 does not operate unless a voltage higher than V _BE1 is applied to the base, only the positive signal component of the input correlation signal appears on the emitter side and rectification is performed. Similarly, on the transistor Q2 side, the base potential is generated by the resistors R7 and R8, and the base-emitter voltage V _BE2
Only set to a voltage lower than ground level. Therefore, only the negative signal component of the input signal appears on the emitter side and rectification is performed.

Next, claim 6 will be described. Further, although the offset voltage is canceled in claims 4 and 5, it is not always necessary to cancel it. Normally, the control signal input to the voltage control clock must be a positive voltage change (or a negative voltage change). Therefore, in the conventional synchronous circuit, when the discrimination characteristic is obtained, the offset is added to it. A sixth aspect of the present invention is an example in which the transistor Q1 is a grounded-emitter circuit and the transistor Q2 is an emitter-follower circuit for envelope detection. The structure is shown in FIG. In the figure, parts having the same functions as those in FIG. 6 are designated by the same reference numerals.

Next, the operation will be described. The transistor Q1 operates in the same manner as in claim 5. Therefore, the collector potential thereof has the waveform shown in FIG. On the other hand, the transistor Q2 takes the output from the emitter,
Since it is smoothed, the offset voltage is not output, and is output with the same amplitude as the negative component of the input correlation signal. This is shown in FIG. Therefore, by multiplying the amplification factor on the transistor Q1 side by 1, the sum of collector potentials of the two transistors becomes (difference between two correlation outputs) + (offset).

[0023]

As is apparent from the above description, the present invention has the following effects. (1) Effects corresponding to claims 1 and 4: The output of one correlator is output as a positive signal and the output of the other correlator is output as a negative signal, and these are added together. Since the difference between the two correlator components is taken out by the above, a differential amplifier is not required, therefore the circuit is simplified, the common mode component is eliminated, and the performance of the synchronous loop is improved. (2) Effects corresponding to claims 2 and 6: Further, in the conventional envelope detection, it was necessary to attach a temperature compensation circuit, but in claim 2, since two diodes were incorporated,
Mutually compensated, it became possible to perform stable detection with respect to temperature. That is, the conventional envelope detection has a drawback that the operating point fluctuates with respect to a change in temperature, but since the two transistors compensate each other for temperature, the stability against temperature is improved. Then, by shifting the operating point of the transistor, the loss due to detection can be reduced. (3) Effect corresponding to claim 3: Furthermore, in addition to the temperature compensation by the two transistors, by shifting the operating point of the transistors, the loss due to detection can be reduced. (4) Effects corresponding to claims 4 and 5: Further, since the transistor is configured as an amplifier to perform detection, it is possible to perform detection and amplification. (5) Effect corresponding to claim 6: Since the detection component is added while leaving the offset component of one transistor, it is not necessary to separately prepare an offset voltage adding circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a non-coherent delay locked loop according to the present invention.

FIG. 2 is a diagram for explaining a second aspect of the present invention.

FIG. 3 is a diagram for explaining claim 3 according to the present invention.

FIG. 4 is a diagram showing signal waveforms of respective parts in FIG.

FIG. 5 is a diagram for explaining claim 4 according to the present invention.

FIG. 6 is a diagram for explaining the fifth aspect of the present invention.

FIG. 7 is a diagram for explaining claim 6 according to the present invention.

FIG. 8 is a diagram showing a signal waveform of each part in claims 4 to 6 according to the present invention.

FIG. 9 is a block diagram of a conventional non-coherent delay locked loop.

FIG. 10 is a configuration diagram of an envelope detection unit and a subtractor of a conventional delay lock loop.

[Explanation of symbols]

1, 2 ... Rectifier circuit, 3, 4 ... Smoothing circuit, 5 ... Adder circuit.

Claims (6)

[Claims] 1. In a receiving system of spread spectrum communication,
A multiplier for multiplying the received signal by each of the pseudo noise signal whose phase is advanced within 1 chip from the reference pseudo noise signal and the pseudo noise signal whose phase is delayed within 1 chip from the reference pseudo noise signal; A band-pass filter for obtaining a correlation signal from the output of the multiplier, one for extracting a positive component of the correlation signal for smoothing, the other for extracting a negative component of the correlation signal for smoothing, and adding them together And a voltage control clock for driving the pseudo noise signal generation circuit by extracting a signal component of the difference between the two correlation outputs by the adder, inputting the signal as a control signal, and a non-coherent delay. Rock loop. 2. A smoothing circuit having an anode side of the first diode as an input end of one correlation signal and a cathode side of a first capacitor having one end grounded and a first resistor having one end grounded. The cathode side of the second diode serves as an input terminal for one correlation signal, and the anode side is connected to a smoothing circuit including a second capacitor whose one end is grounded and a second resistor whose one end is grounded. 2. A circuit in which the cathode end of the first diode and the anode end of the second diode are connected to an adder circuit is used as an envelope detection circuit and a subtractor circuit.
Noncoherent delay locked loop as described. 3. The base of the first NPN-type transistor is biased to a positive voltage by the base-emitter voltage, becomes the input terminal of the correlation signal via the first coupling capacitor, and the collector is a positive voltage source. Is connected to a smoothing circuit including a first capacitor having one end grounded and a first resistor having one end grounded, and the base of the second PNP transistor is a base-emitter. The second capacitor, which is biased to a negative voltage by the inter-terminal voltage, becomes the input terminal of the correlation signal via the second coupling capacitor, the collector receives the voltage supply from the negative voltage source, and the emitter is grounded at one end. And a second resistor whose one end is grounded are connected to each other, and the emitter of the first transistor and the emitter of the second transistor are added to each other. The non-coherent delay locked loop according to claim 1, wherein the circuit connected to is used as an envelope detection circuit and a subtraction circuit. 4. In a receiving system of spread spectrum communication,
A multiplier for multiplying the received signal by each of the pseudo noise signal whose phase is advanced within 1 chip from the reference pseudo noise signal and the pseudo noise signal whose phase is delayed within 1 chip from the reference pseudo noise signal; A band-pass filter for obtaining a correlation signal from the output of the multiplier, one for extracting a positive component of the correlation signal for smoothing, the other for extracting a negative component of the correlation signal for smoothing, and adding them together And a voltage control clock for driving the pseudo noise signal generation circuit by extracting a signal component of the difference between the two correlation outputs by the adder, inputting the signal as a control signal, and a non-coherent delay. In the lock loop, the emitter of the first NPN-type transistor is grounded, and the base of the first NPN-type transistor is The base current flows to the extent that almost no current flows, and becomes the input terminal of the first correlation signal via the resistor and coupling capacitor, the collector is connected to the positive voltage source via the resistor, and one end is grounded. Connected to a smoothing circuit consisting of a connected resistor and a capacitor whose one end is grounded, the emitter of the second PNP-type transistor is grounded, and the base is mostly connected by the resistor connected between the collector and the base. The base current flows to such an extent that it does not exist, becomes the input terminal of the second correlation signal via the resistance and the coupling capacitor, the collector is connected to the negative voltage source via the resistance, and one end is connected to the grounded resistance. A smoothing circuit including a capacitor whose one end is grounded is connected, and the collector voltage of the first transistor and the collector voltage of the second transistor are connected. Non-coherent delay-locked loop, characterized in that an adder circuit adding the voltage, was used as the envelope detection circuit and a subtraction circuit. 5. The emitter of the first NPN-type transistor is grounded via a resistor, the base is biased to a positive voltage by a base-emitter voltage, and the first via a first coupling capacitor. It becomes the input terminal of the correlation signal of
The collector is connected to a positive voltage source through a resistor, and a capacitor whose one end is grounded is connected to the second P
The emitter of the NP-type transistor is grounded via a resistor, the base is biased to a positive voltage by the base-emitter voltage, the second correlation signal is input via the second coupling capacitor, and the collector is An adder circuit connected to a negative voltage source via a resistor and further connected to a capacitor whose one end is grounded, and an adder circuit for adding the collector voltage of the first transistor and the collector voltage of the second transistor to each other. The noncoherent delay locked loop according to claim 4, wherein the noncoherent delay locked loop is used as a detection circuit and a subtraction circuit. 6. The first NPN-type transistor has an emitter grounded via a resistor, a base biased to a positive voltage by a base-emitter voltage, and a first correlation via a first coupling capacitor. It becomes the input end of the signal,
The collector is connected to a positive voltage source through a resistor, and a capacitor whose one end is grounded is connected to the second P
The emitter of the NP-type transistor is grounded via a resistor, the base is biased to a positive voltage by the base-emitter voltage, the second correlation signal is input via the second coupling capacitor, and the collector is An adder circuit connected to a negative voltage source via a resistor and further connected to a capacitor whose one end is grounded, and an adder circuit for adding the collector voltage of the first transistor and the collector voltage of the second transistor to each other. The noncoherent delay locked loop according to claim 4, wherein the noncoherent delay locked loop is used as a detection circuit and a subtraction circuit.