JPH06252657A - Low distortion amplifier - Google Patents

Abstract

PURPOSE:To form a low distortion amplifier circuit without increasing the number of components and power consumption by providing a FET, an input matching circuit and an output matching circuit in a unit amplifier and adjusting the output matching circuit so as to minimize output distortion of the FET. CONSTITUTION:An output impedance of each of output matching circuits Bout1- Boutn of each of unit amplifiers A1-An is matched so as to provide an optimum intercept point to each of FETs Q1-Qn. The intercept point provides a gain of 33dBm and the distortion of the FET is effectively reduced by widening the gate width. However, the gate width of the FET is limited by a signal band. In this low distortion amplifier, the plural FETs Q1-Qn are operated in parallel to attain the same performance as that of the case when the gate width is extended. Thus, each FET whose gate width corresponds to a required operating frequency band is adopted. Thus, the intercept point is much more improved by adjusting optimizingly the output impedance of each of the unit amplifiers A1-An.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a low distortion amplifier. More specifically, the present invention relates to an amplifier used in a compound semiconductor integrated circuit such as GaAs, and particularly to a novel amplifier configured to reduce distortion.

[0002]

2. Description of the Related Art An integrated circuit intended for high frequency operation in the microwave band is a field effect transistor (hereinafter referred to as "FE").
T ") and Si bipolar transistor and other passive elements, and resistors, capacitors, inductors and other passive elements.

Further, when an amplifier with less distortion is required,
A so-called push-pull configuration is generally configured to cancel the secondary distortion and add a feedforward circuit to reduce the tertiary distortion.

[0004]

However, when the distortion is reduced by adding the compensating circuit as described above, the circuit scale of the compensating circuit becomes larger than that of the original amplifier, which is effective. The packaging density of various circuits is reduced. Further, since the compensation circuit is added, the number of active elements to be used increases and power consumption also increases.

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art and to construct a low distortion amplifier circuit without increasing the number of elements and power consumption.

[0006]

According to the present invention, a power divider that divides an input into a plurality of inputs, a plurality of unit amplifiers that individually receive the outputs of the power dividers, and the outputs of the unit amplifiers are combined and output. A power combiner, the unit amplifier includes a field effect transistor, an input matching circuit, and an output matching circuit, and the output matching circuit is adjusted so that output distortion of the field effect transistor is minimized. A low distortion amplifier is provided.

[0007]

The low distortion amplifier according to the present invention is characterized mainly in that the distortion characteristic of the amplifier is improved without using an additional compensation circuit.

That is, in the conventional low distortion amplifier, the low distortion amplifier is constructed by adding a circuit for compensating the distortion between the input and the output of the amplifier. Therefore, it is unavoidable that the number of active elements increases, which leads to an increase in power consumption.

On the other hand, in the low distortion amplifier according to the present invention, a plurality of unit amplifiers each having an input matching circuit, an output matching circuit, and an FET are operated in parallel, and the output distortion of the FET is increased in each unit amplifier. By matching the output impedance so that
It is not necessary to add a third-order distortion compensation circuit. Therefore, an increase in the number of active elements and an increase in power consumption due to the addition of the compensation circuit are suppressed.

That is, the intercept point IP ₃ which is the intersection of the fundamental wave output power characteristic line and the third-order distortion output power characteristic line with respect to the input power of the FET becomes higher as the element in the FET has smaller distortion. On the other hand, FE with a certain gate width
FET whose gate width is n times the constant input power applied to T
, The operating state of the FET at this time can be regarded as equivalent to the case where 1 / n input power is applied to each of the n FETs, and the distortion generated in the FET is [3].
n] dBm is reduced. Therefore, an FET with a gate width n times
Is an FET with an extremely high intercept point IP _3.
Can be considered.

However, the gate width of the FET that can be used in the amplifier is limited by the frequency band used. For example, if a band of 2 GHz is required, the gate width can only be used up to 250 μm. Therefore, a low-distortion amplifier corresponding to a desired frequency band can be configured by inserting a power divider and a power combiner into the input section and the output section of the amplifier and driving a plurality of FETs in parallel.

Another cause of distortion in the FET is output impedance mismatch. That is, F
If there is an impedance mismatch in the output part of the ET, the microwave is reflected there and returns to the inside of the FET again, and signals having different phases interfere with each other to cause distortion. Therefore, in the amplifier according to the present invention, the output impedance of each FET is adjusted so that the intercept point IP _3, which is closely related to the S parameter S ₂₂ ^* of the FET, is maximized. Incidentally, S
The parameter expresses the characteristics of the circuit network paying attention to the amount of reflection and transmission of electric power, and S ₂₂ represents the output coefficient when the input side of the circuit is terminated with a predetermined impedance.
S ₂₂ ^* means the complex conjugate of S ₂₂ .

Hereinafter, the present invention will be described more specifically with reference to examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention.

[0014]

1 is a diagram schematically showing the basic structure of a low distortion amplifier according to the present invention.

As shown in the figure, this low distortion amplifier has a power divider 1 for receiving input power and a plurality of unit amplifiers A _{1 to} A _n for individually receiving the input power divided into n by the power divider 1. And a power combiner 2 that receives the outputs of the unit amplifiers A _{1 to} A _n and combines them.

The unit amplifiers A _{1 to} A _n include FETs Q _{1 to} Q _n as amplifying elements and input matching circuits B (in) _{1 to} B (i).
n) _n and output matching circuits B (out) _{1 to} B (out) _n . As the power divider 1, it is possible to use a circuit having a well-known configuration such as a Wilkinson type or a resistance division type, and the same applies to the power combiner 2.

In the low distortion amplifier configured as described above, the output matching circuits B (out) ₁ to of the unit amplifiers A _{1 to} A _n are
B (out) _n is set so that the optimum intercept point IP ₃ described below is given to the FETs Q _{1 to} Q _n .
The output impedance is matched.

FIG. 2 is a graph showing the input / output characteristics of a certain FET (gate width Wg). As shown in the figure, when the input power is -30 dBm, the output power of this FET is -10 dB.
m, third-order distortion output is -90 dBm. At this time, an intercept point I for comparing the magnitude of distortion with output power
P ₃ is 30 dBm. In addition, intercept point I
P ₃ becomes higher for FETs with smaller distortion.

Considering a FET having a gate width n times that of the FET having the above-mentioned characteristics, the operating state of the FET is, for example, when the input power of -30 dBm is input to the FET having a gate width of 2 Wg. 2 FEs with width Wg
It is considered to be equivalent to the state where half the input power of −33 dBm is input to each T.

Here, the output power of the third-order distortion of the FET has a relationship of 3: 1 with the output power, and the FET of the gate width Wg is
Output power of −13 dBm and third-order distortion output of −99 dBm, respectively, can be obtained. Considering this for an FET having a gate width of 2 Wg, an output power of −10 dBm and a third-order distortion output of −96 dBm can be obtained.

That is, the intercept point IP ₃ is 33
dBm, and effective FE by expanding the gate width
It can be seen that the distortion of T has been reduced. However, the gate width of the FET is limited by the signal band, and for example, when the band of 2 GHz is required, the gate width is limited to 250 μm. On the other hand, in the low distortion amplifier according to the present invention, a plurality of FEs are
By operating T in parallel, the same performance as when the gate width is expanded is realized. Therefore, as the individual FETs, those having a gate width corresponding to the required operating frequency band can be used.

FIG. 3 is a graph showing the relationship between the output impedance of an FET having a gate width of 280 μm and IP ₃ .

As shown in the figure, the output impedance at which IP ₃ is maximum is deeply related to the S parameter S _{22 of the} FET. That is, the output impedance is set to this optimum I
By matching P ₃ , the distortion of the FET can be minimized.

As described above, when the output impedance of each unit amplifier A _{1 to} A _n in the circuit shown in FIG. 1 is optimally adjusted, the intercept point IP ₃ is improved by [3n] dBm in the entire low distortion amplifier. It

[0025]

As described above, the low distortion amplifier according to the present invention operates a plurality of unit amplifiers in parallel,
Output impedance matching is performed so that each FET operates at the best intercept point IP ₃ , and the generation of distortion in the FET itself is suppressed in principle. Therefore, 2
The output distortion of the amplifier can be reduced without an additional circuit for compensating for the second distortion and the third distortion.

According to the present invention as described above, an optical analog communication requiring a low distortion operation is provided, which provides an amplifier that operates with a low distortion without increasing the number of active elements used and without increasing power consumption. It can be advantageously used in a system or the like.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a low distortion amplifier according to the present invention.

FIG. 2 is a graph showing input / output characteristics of FETs.

FIG. 3 is a graph showing the relationship between the output impedance of the FET and the intercept point IP ₃ .

[Explanation of symbols]

1 ... Power divider, 2 ... Power combiner, A _{1 to} A _n ... Unit amplifier, B (in) _{1 to} B (in) _n ... Input matching circuit, B (out) _{1 to} B (out) _n・ ・ ・ Output matching circuit, Q _{1 to} Q _n・ ・ ・ FET

Claims (1)

[Claims] 1. A unit amplifier comprising: a power divider that divides an input into a plurality of units; a plurality of unit amplifiers that individually receive the output of the power divider; and a power combiner that combines and outputs the outputs of the unit amplifiers. Includes a field effect transistor, an input matching circuit, and an output matching circuit, and the output matching circuit is adjusted so that the output distortion of the field effect transistor is minimized. .