JPH06252364A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the drop of resistance to soft error and the change of the threshold voltage of a driving transistor and the inferiority of element isolation while stabilizing the threshold voltage of the film transistor being the load element of a memory cell. CONSTITUTION:The ions 37 of impurities are implanted by oblique ion implantation method into the gate electrode 15a of the PMOS film transistor as the load element of a memory cell. So, even if the dosage of the ions 37 at the section excluding the bottom of a contact hole 36 is increased out of the gate electrode 5a, the dosage of the bottom of the contact hole 36 is small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a TFT load type SRAM.
The present invention relates to a method for manufacturing a semiconductor memory device called as.

[0002]

2. Description of the Related Art FIGS. 4 and 5 show a planar structure and an equivalent circuit of a memory cell of a TFT load type SRAM. The flip-flop 11 of this memory cell is an NMO for driving.
The S-transistors 12 and 13 and the load PMOS transistors 14 and 15 form a memory cell. The flip-flop 11 and the transfer NMOS transistors 16 and 17 form a memory cell.

A ground line 21 is connected to the source regions of the NMOS transistors 12 and 13, and a power supply line 22 is connected to the source regions of the PMOS transistors 14 and 15. Further, the word line 23 serves as the gate electrodes of the NMOS transistors 16 and 17, and these NMOs are
True complementary bit lines 24 and 25 are connected to one source / drain region of each of the S transistors 16 and 17.

Of the transistors 12 to 17, the NMO
The S transistors 12, 13, 16 and 17 are bulk transistors in which a channel region is formed in a semiconductor substrate, while the PMOS transistors 14 and 15 are polycrystalline Si stacked on top of the NMOS transistors 12 and 13 and the like.
It is a thin film transistor (TFT) in which a channel region is formed in the film.

3 and 2 are bottom gate type TFTs.
A load type SRAM and a manufacturing method thereof are shown. In this manufacturing method, first, as shown in FIG. 3, an N well 27 is formed in a Si substrate as a P type semiconductor substrate 26, and a P well 28 is further formed in this N well 27. Then, as shown in FIG. 2A, a field insulating film 31 and a gate insulating film 32 are formed of a SiO ₂ film on the surface of the semiconductor substrate 26.

After that, the NMOS transistors 12 and 13
Gate electrodes 12a, 13a, ground line 21, and word line 2
3 and 3 are formed of a polycide film which is the first conductive film on the semiconductor substrate 26. Then, the N ⁺ type diffusion layer 33 as the source / drain regions of the NMOS transistors 12, 13, 16 and 17 is formed in the P well 28.

The gate electrode 12a has a diffusion layer 33 as a drain region of the NMOS transistor 13 and an N layer.
A buried contact is made with the other diffusion layer 33 as the source / drain region of the MOS transistor 17. Further, the gate electrode 13a is buried in contact with the common diffusion layer 33 as the drain region of the NMOS transistor 12 and the other source / drain region of the NMOS transistor 16. Further, the ground line 21 is also buried and contacted with the diffusion layer 33 as the source region of each of the NMOS transistors 12 and 13.

After that, an interlayer insulating film 34 is deposited on the entire surface, and the contact holes 3 reaching the gate electrodes 12a and 13a are formed.
5 and 36 are opened in the interlayer insulating film 34. Then, in the polycrystalline Si film which is the second conductive film on the semiconductor substrate 26,
Gate electrodes 12a, 1 through contact holes 35, 36
PMOS transistors 14 and 15 contacting 3a
Gate electrodes 14a and 15a are formed.

Impurity ions 37 are implanted into the gate electrodes 14a and 15a at an incident angle of about 0 to 7 °, as shown in FIG. When the gate electrodes 14a and 15a are of P type, for example, BF ₂ ⁺ is accelerated with an acceleration energy of 30 keV and 1
^{Implanted at} a dose of × 10 ¹⁵ cm ^-2 to form a gate electrode 14
When making a and 15a N-type, for example, Phos ^{+ is set} to 2
Implantation is performed at an acceleration energy of 5 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 2B, a gate insulating film 41 is formed of a SiO ₂ film or an ONO film, and contact holes 42 and 43 reaching the gate electrodes 14a and 15a are formed in the gate insulating film 41. Make a hole. Then, the active layer 14 of the PMOS transistors 14 and 15 which is the third-layer conductive film on the semiconductor substrate 26 and contacts the gate electrodes 14 a and 15 a through the contact holes 42 and 43.
b and 15b and the power supply line 22 are formed.

Next, as shown in FIG. 2C, the active layer 14
Photoresist 4 so as to cover the portions of the transistors b and 15b that should be the channel regions of the PMOS transistors 14 and 15.
4 is patterned, and using the photoresist 44 as a mask, ions 45 of a P-type impurity such as BF ₂ ⁺ are implanted into the active layers 14b and 15b and the power supply line 22. As a result,
The PMOS transistors 14 and 1 are provided on the active layers 14b and 15b.
The source / drain region 5 is formed, and the resistance of the power supply line 22 is reduced.

Next, as shown in FIG.
4 is removed, an interlayer insulating film 46 is formed on the entire surface, and NM
Contact hole 4 reaching diffusion layer 33 as one source / drain region of each of OS transistors 16 and 17
7 and 48 are opened in the interlayer insulating film 46 and the like. Then, a refractory metal film 51 such as a tungsten film having a pattern that contacts the diffusion layer 33 through the contact holes 47 and 48 and extends to the upper layer of the word line 23,
52 is formed.

After that, a flat interlayer insulating film 53 is formed on the entire surface, and contact holes 54 and the like reaching the refractory metal films 51 and 52 in the upper layer of the word line 23 are opened in the interlayer insulating film 53. Then, the bit lines 24 and 25 contacting the refractory metal films 51 and 52 through the contact holes 54 and the like are formed by Al.
The TFT load type SRAM is completed by forming a film and then a surface protective film (not shown) and the like.

[0014]

By the way, as described with reference to FIG. 6, as the ions 37 implanted into the gate electrodes 14a and 15a of the PMOS transistors 14 and 15, P-type impurity ions such as BF ₂ ⁺ are used. When used, when the dose amount of the ions 37 is large, the P-type impurity diffuses from the gate electrodes 14a and 15a to the gate electrodes 12a and 13a.
As a result, the impurity concentrations of the gate electrodes 12a and 13a change, and the threshold voltages of the NMOS transistors 12 and 13 change.

Further, the P-type impurities diffused into the gate electrodes 12a and 13a are diffused to the N ⁺ -type diffusion layer 33 through the buried contact, the impurity concentration of the diffusion layer 33 is lowered, and this diffusion layer 33 Junction capacitance is reduced. As a result, the charge storage capacity at the storage node of the memory cell decreases, the time constant decreases, and the soft error resistance of the memory cell decreases.

When N-type impurity ions such as Phos ⁺ are used as the ions 37 to be implanted into the gate electrodes 14a and 15a of the PMOS transistors 14 and 15, if the dose amount of the ions 37 is large, the N-type impurity will be removed. Electrode 1
4a, 15a to the gate electrodes 12a, 13a, and further to the N ⁺ type diffusion layer 33 through the buried contact. As a result, the junction of the diffusion layer 33 becomes deeper, resulting in defective element isolation.

Furthermore, if the contact resistance between the gate electrodes 14a, 15a and the gate electrodes 12a, 13a becomes too low due to the N-type impurities implanted in the gate electrodes 14a, 15a, the storage nodes of the memory cells will also be affected. The time constant becomes small, which also reduces the soft error resistance of the memory cell.

On the other hand, 1 × 1 for the gate electrodes 14a and 15a regardless of whether it is a P-type impurity or an N-type impurity.
The threshold voltage of the PMOS transistors 14 and 15 cannot be stabilized unless the impurity concentration of the gate electrodes 14a and 15a is increased by introducing it at a sufficient dose amount of about 0 ¹⁵ cm ^-2 or more. Therefore, the above-described manufacturing method of the conventional example cannot manufacture the TFT load type SRAM excellent in both characteristics and reliability.

[0019]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, wherein a memory cell is formed by using a flip-flop 11, and the memory cell is arranged in an upper layer of the driving transistors 12, 13 of the flip-flop 11. The thin film transistors 14 and 15 are connected to the flip-flop 11.
Of the thin film transistor 14,
The semiconductor films 14a and 15a forming the gate electrode 15 and the gate electrodes 12a and 13a of the driving transistors 12 and 13
In the method of manufacturing a semiconductor memory device in which and are connected to each other through contact holes 35 and 36, the impurity 37 is introduced into the semiconductor films 14a and 15a by an oblique ion implantation method.

A method of manufacturing a semiconductor memory device according to claim 2 is
The method of manufacturing a semiconductor memory device according to claim 1, wherein the semiconductor films 14a and 15a are the thin film transistors 14 and 1, respectively.
It is characterized in that it is a gate electrode of No. 5.

A method of manufacturing a semiconductor memory device according to claim 3 is
The method of manufacturing a semiconductor memory device according to claim 1 or 2, wherein an incident angle of the impurity 37 by the oblique ion implantation method is 30 ° or more.

[0022]

According to the method of manufacturing the semiconductor memory device of the present invention,
Semiconductor film 1 forming the thin film transistors 14 and 15
Even if the impurities 37 are introduced in a sufficient dose amount with respect to 4a and 15a, due to the shadow effect by the oblique ion implantation method, the dose in the bottom portions of the contact holes 35 and 36 in the semiconductor films 14a and 15a is reduced. The quantity is small. Therefore, while increasing the impurity concentration of the semiconductor films 14a and 15a forming the thin film transistors 14 and 15, the semiconductor films 14a and 15a and the driving transistors 12 and 1 are formed.
It is possible to prevent the contact resistance between the third gate electrodes 12a and 13a from becoming too low.

Further, since the dose amount of the impurity 37 in the bottom portions of the contact holes 35 and 36 of the semiconductor films 14a and 15a forming the thin film transistors 14 and 15 is small, the gate electrodes of the driving transistors 12 and 13 are small. The diffusion of the impurities 37 into the diffusion layer 33 of the semiconductor substrate 26 via the gate electrodes 12a and 13a and the gate electrodes 12a and 13a is also small. Therefore, it is possible to prevent the impurity concentrations of the gate electrodes 12a and 13a from changing, the junction capacitance of the diffusion layer 33 to decrease, and the junction of the diffusion layer 33 to deepen.

[0024]

EXAMPLES Below, a TFT load type S which is a bottom gate type
An embodiment of the present invention applied to the manufacture of RAM will be described with reference to FIG. In addition, the same reference numerals are given to the components corresponding to the above-described conventional example described with reference to FIGS.

Also in this embodiment, the PMOS transistor 14,
Except for the implantation of the ions 37 into the gate electrodes 14a and 15a of the gate electrode 15, substantially the same steps as the above-described conventional example described with reference to FIGS. That is, in the above-mentioned one conventional example, the ions 37 are implanted at an incident angle of about 0 to 7 ° as shown in FIG. 6, but in the present embodiment, 30 ° or more, usually shown in FIG. Similarly, the ions 37 are implanted at an incident angle of about 60 °.

Therefore, as apparent from FIG. 1, the contact holes 35 and 36 of the gate electrodes 14a and 15a are formed.
Even if the dose amount of the ions 37 in portions other than the bottom portion of the gate electrode is the same as that of the conventional example, the dose amount of the ions 37 in the bottom portions of the contact holes 35 and 36 of the gate electrodes 14a and 15a is due to the shadow effect. Less than one conventional example.

Therefore, it is possible to prevent the contact resistance between the gate electrodes 14a and 15a and the gate electrodes 12a and 13a from becoming too low while increasing the impurity concentration of the gate electrodes 14a and 15a, and to diffuse the diffusion layer 33. It is also possible to prevent a decrease in the junction capacitance. Further, it is possible to prevent the impurity concentration of the gate electrodes 12a and 13a from changing, and prevent the junction of the diffusion layer 33 from becoming deep.

The shadow effect described above is due to the contact holes 35,
It is effective when the aspect ratio of 36 is about 1 or more, but since the aspect ratio is generally about 1 or more, the shadow effect is effective in most cases. In order to increase the aspect ratio of the contact holes 35 and 36, if the size of the contact holes 35 and 36 is constant,
The thickness of the interlayer insulating film 34 may be increased. Even if the aspect ratio is about 1 or less, the shadow effect becomes effective by increasing the incident angle of the ions 37.

As is clear from the equivalent circuit of FIG. 5, in the top gate type TFT load type SRAM, PM
Gate electrodes 14a and 15 of the OS transistors 14 and 15
a is once brought into contact with the drain regions of the active layers 15b and 14b of the other PMOS transistors 15 and 14, and these drain regions are connected to the NMOS transistor 1
The gate electrodes 12a and 13a of 2 and 13 may be contacted.

Therefore, although the present invention is applied to the manufacture of the TFT load type SRAM of the bottom gate type in the above embodiment, the TFT load type SRA of the top gate type is applied.
The present invention can be applied to the case where impurities are introduced into the active layers 14b and 15b of the PMOS transistors 14 and 15 in manufacturing M.

[0031]

According to the method of manufacturing a semiconductor memory device of the present invention, the contact resistance between the semiconductor film and the gate electrode of the driving transistor is low while increasing the impurity concentration of the semiconductor film forming the thin film transistor. It is possible to prevent excessive decrease and to prevent the junction capacitance of the diffusion layer of the semiconductor substrate from decreasing, so that it is possible to prevent the soft error resistance from decreasing while stabilizing the threshold voltage of the thin film transistor. be able to.

Further, since it is possible to prevent the impurity concentration of the gate electrode of the driving transistor from changing,
Since it is possible to prevent the threshold voltage of the driving transistor from changing and further prevent the junction of the diffusion layer of the semiconductor substrate from becoming deep, it is possible to prevent defective element isolation. Therefore, the method of manufacturing a semiconductor memory device according to the present invention can manufacture a semiconductor memory device having excellent characteristics and reliability.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention and is an enlarged side sectional view of a main part in the step of FIG.

FIG. 2 shows a general manufacturing method of a bottom gate type TFT load type SRAM in the order of steps, and is taken as S-S in FIG.
It is a sectional side view in the position which follows a line.

FIG. 3 is a side sectional view showing a bottom gate type TFT load type SRAM, taken along a line S-S in FIG.

FIG. 4 is a plan view of a memory cell of a TFT load type SRAM.

FIG. 5 is an equivalent circuit diagram of a memory cell of a TFT load type SRAM.

FIG. 6 is a side sectional view showing a conventional example of the present invention and an enlarged main part in the step of FIG.

[Explanation of symbols]

 11 flip-flop 12 NMOS transistor 13 NMOS transistor 14 PMOS transistor 14a gate electrode 15 PMOS transistor 15a gate electrode 35 contact hole 36 contact hole 37 ion

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 C

Claims (3)

[Claims] 1. A memory cell is formed by using a flip-flop, and a thin film transistor arranged in an upper layer of a driving transistor of the flip-flop is a load element of the flip-flop, and constitutes the thin film transistor. In the method for manufacturing a semiconductor memory device, wherein the semiconductor film and the gate electrode of the driving transistor are connected to each other through a contact hole, the impurity is introduced into the semiconductor film by an oblique ion implantation method. Method of manufacturing semiconductor memory device. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the semiconductor film is a gate electrode of the thin film transistor. 3. The incident angle of the impurities by the oblique ion implantation method is 30 ° or more.
Alternatively, the method of manufacturing the semiconductor memory device according to the item 2.