JPH06252152A - Formation of solder bump on ceramic wiring board - Google Patents

Formation of solder bump on ceramic wiring board

Info

Publication number
JPH06252152A
JPH06252152A JP3213593A JP3213593A JPH06252152A JP H06252152 A JPH06252152 A JP H06252152A JP 3213593 A JP3213593 A JP 3213593A JP 3213593 A JP3213593 A JP 3213593A JP H06252152 A JPH06252152 A JP H06252152A
Authority
JP
Japan
Prior art keywords
mask
wiring board
solder
diameter
solder paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3213593A
Other languages
Japanese (ja)
Inventor
Yoshio Nishikawa
義雄 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP3213593A priority Critical patent/JPH06252152A/en
Publication of JPH06252152A publication Critical patent/JPH06252152A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Abstract

PURPOSE:To easily and accurately control the size of solder bumps to an extent that short circuits between solder bumps or the degradation in packaging reliability will not be caused. CONSTITUTION:Solder paste S1 is placed on the metal round pads 3 on the surface of an AlN wiring board 1 by printing using a mask 5. The mask 5 is removed from the AlN wiring board 1, and the solder paste is subjected to reflow to form solder bumps. At that time the diameter r of the pad 3 should be 50-500mum; the thickness t of the mask 5 10 300mum; the diameter a of the opening 6 of the mask 5 50-1000mum. In this case the diameter a of the opening 6 should be larger than the diameter r of the pad 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、セラミックス配線板の
はんだバンプ形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming solder bumps on a ceramic wiring board.

【0002】[0002]

【従来の技術】従来、導体回路が印刷された配線板の金
属製パッド上に電子部品を表面実装するための方法とし
て、はんだバンプ(Solder bump )法と呼ばれるはんだ
付け法の一種が知られている。この方法は、配線板の製
造工程の一部として、金属製パッド上へのはんだバンプ
の形成を行うことを特徴とするものである。
2. Description of the Related Art Conventionally, as a method for surface-mounting an electronic component on a metal pad of a wiring board on which a conductor circuit is printed, a kind of soldering method called a solder bump method has been known. There is. This method is characterized in that solder bumps are formed on the metal pads as part of the wiring board manufacturing process.

【0003】部品実装前の配線板の金属製パッド上には
んだバンプを形成する方法としては、例えばリフローに
よる方法がある。この方法では、通常、配線板表面の金
属製パッド上にマスクを設けた状態ではんだペーストを
印刷し、次いでマスクを除去した後、はんだペーストを
一旦加熱してから冷却する(リフローする)という手順
が採られている。
As a method of forming solder bumps on a metal pad of a wiring board before component mounting, for example, there is a method by reflow. In this method, usually, a solder paste is printed on a metal pad on the surface of a wiring board with a mask provided, then the mask is removed, and then the solder paste is once heated and then cooled (reflow). Is taken.

【0004】この場合、マスクの形状(厚さ・開口の大
きさ)やパッドの大きさいかんによってはんだペースト
の印刷量が変動し、ひいては形成されるはんだバンプの
大きさも変動することが一般に知られている。
In this case, it is generally known that the printing amount of the solder paste changes depending on the shape of the mask (thickness / opening size) and the size of the pad, and thus the size of the solder bump to be formed also changes. ing.

【0005】[0005]

【発明が解決しようとする課題】ところが、従来のはん
だバンプ形成方法では、パッドの大きさ等の前記諸ファ
クターとはんだペーストの印刷量との相間関係が不明確
であったため、充分にはんだバンプの大きさを制御する
ことができなかった。
However, in the conventional solder bump forming method, the correlation between the above factors such as the size of the pad and the printing amount of the solder paste is unclear. The size could not be controlled.

【0006】このため、はんだペーストの印刷量がパッ
ド11に比べて多過ぎる場合には、大きなはんだバンプ
12が形成され、隣接するはんだバンプ12間でショー
トが生じる場合があった(図5参照)。一方、はんだペ
ーストの印刷量がパッド11に比べて少な過ぎる場合に
は、はんだバンプ13による濡れが不充分になり、実装
信頼性が低下するという問題があった(図6参照)。し
かも、従来方法においては印刷量のばらつきも大きかっ
た。
Therefore, when the printing amount of the solder paste is too large as compared with the pad 11, a large solder bump 12 is formed and a short circuit may occur between the adjacent solder bumps 12 (see FIG. 5). . On the other hand, when the printing amount of the solder paste is too small as compared with the pad 11, there is a problem that the wetting by the solder bumps 13 becomes insufficient and the mounting reliability decreases (see FIG. 6). Moreover, in the conventional method, the variation in the printing amount was large.

【0007】そこで、本発明者らは鋭意研究を行い、マ
スクの厚さ、マスクの開口の大きさ及びパッドの大きさ
とはんだペーストの印刷量との相間関係を求めた実験結
果から、所定範囲内で前記各ファクターを変更すれば良
いという知見を得た。そして、本発明者らはこの知見を
もとに本発明を完成させた。
Therefore, the inventors of the present invention have conducted diligent research and found that the correlation between the thickness of the mask, the size of the opening of the mask and the size of the pad and the printing amount of the solder paste was found to be within a predetermined range Therefore, it was found that the above factors should be changed. The present inventors have completed the present invention based on this finding.

【0008】本発明の目的は、はんだバンプ間のショー
トや実装信頼性の低下等を招かない範囲で、はんだバン
プの大きさ制御を容易にかつ正確に行うことができるセ
ラミックス配線板のはんだバンプ形成方法を提供するこ
とにある。
It is an object of the present invention to form solder bumps on a ceramic wiring board in which the size of the solder bumps can be easily and accurately controlled without causing a short circuit between the solder bumps and a reduction in mounting reliability. To provide a method.

【0009】[0009]

【課題を解決するための手段及び作用】上記の課題を解
決するために、本発明では、セラミックス配線板表面の
金属製円形パッド上にマスクを設けた状態ではんだペー
ストを印刷し、次いでそのマスクをセラミックス配線板
から除去し、更に前記はんだペーストをその融点以上の
温度に一旦加熱してから冷却するセラミックス配線板の
はんだバンプ形成方法において、前記マスクの開口の直
径aを前記金属製円形パッドの直径rよりも大きくする
と共に、該開口の直径aを50μm〜1000μmとし
かつ該金属製円形パッドの直径rを50μm〜500μ
mとし、更に前記マスクの厚さtを10μm〜300μ
mとすることをその要旨としている。
In order to solve the above problems, in the present invention, a solder paste is printed with a mask provided on a circular metal pad on the surface of a ceramic wiring board, and the mask is then printed. Is removed from the ceramic wiring board, and the solder paste is formed by heating the solder paste to a temperature higher than its melting point and then cooling the solder paste. The diameter a of the opening is 50 μm to 1000 μm, and the diameter r of the metal circular pad is 50 μm to 500 μm.
m, and the thickness t of the mask is 10 μm to 300 μm.
The gist is that it is m.

【0010】本発明において、各ファクター(金属製円
形パッドの直径r、マスクの厚さt及びマスクの開口の
直径a)を前記範囲内とする理由は以下の通りである。
即ち、金属製円形パッドの直径rが50μm未満である
と、電子部品のリード等に接する面積が小さくなるた
め、実装信頼性が低下してしまう。一方、金属製円形パ
ッドの直径rが500μmを越える場合、パッドを設け
るピッチを大きくせざるを得なくなり、実装密度が低下
してしまう。
In the present invention, each factor (the diameter r of the metal circular pad, the thickness t of the mask and the diameter a of the opening of the mask) is set within the above range for the following reason.
That is, when the diameter r of the metal circular pad is less than 50 μm, the area in contact with the leads of the electronic component becomes small, and the mounting reliability decreases. On the other hand, when the diameter r of the metal circular pad exceeds 500 μm, the pitch at which the pads are provided is unavoidably increased, and the mounting density is reduced.

【0011】マスクの厚さtが10μm未満であると、
最低限のはんだペーストの印刷量を確保するためにマス
クの開口の直径aを大きくする必要が生じ、結果として
ショートの原因となってしまう。一方、マスクの厚さt
が300μmを越える場合、マスクを除去するときに開
口からペーストが抜け難くなり、印刷量のばらつきが大
きくなる。
If the thickness t of the mask is less than 10 μm,
It is necessary to increase the diameter a of the opening of the mask in order to secure the minimum printing amount of the solder paste, which results in a short circuit. On the other hand, the mask thickness t
When it exceeds 300 μm, it becomes difficult for the paste to come off from the opening when the mask is removed, and the variation in the printing amount increases.

【0012】マスクの開口の直径aが50μm未満であ
ると、マスクを除去するときに開口からペーストが抜け
難くなり、印刷量のばらつきが大きくなる。一方、マス
クの開口の直径aが1000μmを越える場合、通常の
セラミックス配線板のピッチ間隔を越えてしまうため、
結果としてショートが生じ易くなってしまう。
When the diameter a of the opening of the mask is less than 50 μm, it becomes difficult for the paste to come off from the opening when the mask is removed, and the variation of the printing amount increases. On the other hand, when the diameter a of the opening of the mask exceeds 1000 μm, it exceeds the pitch interval of the usual ceramic wiring board.
As a result, a short circuit is likely to occur.

【0013】また、本発明ではマスクの開口の直径a
は、金属製円形パッドの直径rよりも大きく設定され
る。このような大きさ関係にしておくと、はんだペース
トの印刷量の制御がより確実なものとなるからである。
Further, in the present invention, the diameter a of the opening of the mask is
Is set to be larger than the diameter r of the metal circular pad. This is because if the size relationship is set, the printing amount of the solder paste can be controlled more reliably.

【0014】なお、本発明では配線板として、セラミッ
クス基材上に金属製円形パッドが形成されたセラミック
ス配線板が使用される。このような配線板にはんだペー
ストを印刷した場合、セラミックス基材の濡れ性の悪さ
によって、セラミックス基材上のはんだペーストがはじ
かれてしまうからである。よって、印刷領域がパッドの
直径rよりも大きくても、リフロー時にははんだペース
トがパッド上に凝縮し、球欠形のはんだバンプが形成さ
れるからである。
In the present invention, a ceramic wiring board in which a circular metal pad is formed on a ceramic substrate is used as the wiring board. This is because when the solder paste is printed on such a wiring board, the solder paste on the ceramic base material is repelled due to the poor wettability of the ceramic base material. Therefore, even if the printing area is larger than the diameter r of the pad, the solder paste is condensed on the pad during the reflow process, and a ball-shaped solder bump is formed.

【0015】そして、本発明では上述の範囲内にて前記
各ファクターを増減することにより、はんだペーストの
印刷量、ひいてはリフローを経て形成されるはんだバン
プの大きさ(高さ)の調整が行われる。
In the present invention, the printing amount of the solder paste, and consequently the size (height) of the solder bump formed through reflow, is adjusted by increasing or decreasing each of the factors within the above range. .

【0016】次に、はんだペーストの印刷量及びはんだ
バンプの大きさ(高さ)を求めるときの計算方法につい
て詳細に説明する。マスクに設けられる開口の形状は通
常円形状であるため、印刷されるはんだペーストの形状
は略円柱状となる。このため、はんだペーストの印刷量
V0 は、次式1に示すように、 V0 =π・(a/2)2 ・t …〔1〕 となる。なお、上述したように、aはマスクの開口の直
径であり、tはマスクの厚さである。
Next, a calculation method for obtaining the print amount of the solder paste and the size (height) of the solder bump will be described in detail. Since the shape of the opening provided in the mask is usually circular, the shape of the solder paste to be printed is substantially columnar. Therefore, printing the amount V0 of the solder paste, as shown in the following equation 1, V0 = π · (a / 2) becomes 2 · t ... [1]. As described above, a is the diameter of the opening of the mask and t is the thickness of the mask.

【0017】ここで、はんだペースト中に占めるはんだ
粒の体積の逆数をαとし、リフローによって形成される
はんだバンプの体積をV1 とすると、次式2に示すよう
に、 V1 =V0 /α=π・(a/2)2 ・t/α …〔2〕 という関係が成り立つことがわかる。つまり、前式2
は、はんだペースト中のフラックスがリフローによって
除去されると、その分量に応じてはんだバンプの体積が
減少するということを意味している。
Assuming that the reciprocal of the volume of the solder particles in the solder paste is α and the volume of the solder bump formed by the reflow is V1, V1 = V0 / α = π as shown in the following equation 2. It can be seen that the relationship of (a / 2) 2 · t / α ... [2] holds. That is, Equation 2
Means that when the flux in the solder paste is removed by reflow, the volume of the solder bumps decreases according to the amount.

【0018】また、はんだのリフローによって形成され
るはんだバンプの形状が略球欠形となることを考慮する
と、高さをh,パッドの直径をrとしたとき、前記はん
だバンプの体積V1 は、次式3に示すように、 V1 =(1/6)・π・h・{(3/4)・r2 +h2 } …〔3〕 で表されることになる。
Considering that the shape of the solder bump formed by the reflow of the solder is a substantially spherical shape, when the height is h and the diameter of the pad is r, the volume V1 of the solder bump is As shown in the following expression 3, V1 = (1/6) .π.h. {(3/4) .r 2 + h 2 } [3]

【0019】ここで、式2及び式3からV1 を消去し
て、はんだバンプの高さhについての式4に変形する
と、 h=f(r,α,a,t) …〔4〕 となり、hをr,α,a,tの関数としてとらえること
ができる。これを換言すると、はんだバンプの高さhの
値は、変数としてのr,α,a,t値を変更することに
よって、あらかじめ設定可能であるということになる。
Here, when V1 is erased from the equations 2 and 3, and transformed into the equation 4 for the height h of the solder bump, h = f (r, α, a, t) ... [4] We can regard h as a function of r, α, a, and t. In other words, the value of the solder bump height h can be set in advance by changing the r, α, a, and t values as variables.

【0020】以上のように、この発明によると前記諸フ
ァクターの値を所定範囲内において増減することによ
り、はんだバンプの大きさ(高さ)制御を容易にかつ正
確に行うことができる。
As described above, according to the present invention, the size (height) of the solder bump can be easily and accurately controlled by increasing or decreasing the values of the various factors within a predetermined range.

【0021】[0021]

【実施例】以下、本発明を具体化した実施例を図1〜図
5に基づき詳細に説明する。本実施例では、AlN基板
2に導体回路としての金属製円形パッド3、スルーホー
ル内導体パターン4a及び配線パターン4bが形成され
た窒化アルミニウム(AlN)配線板を選択した(図1
参照)。そして、AlN配線板1の表面に、開口6が形
成されたステンレス製のマスク(村上スクリーン製)5
を密着させた。
Embodiments of the present invention will be described in detail below with reference to FIGS. In this embodiment, an aluminum nitride (AlN) wiring board having a metal circular pad 3 as a conductor circuit, a through hole conductor pattern 4a and a wiring pattern 4b formed on an AlN substrate 2 is selected (FIG. 1).
reference). Then, a mask made of stainless steel (made by Murakami Screen) 5 having openings 6 formed on the surface of the AlN wiring board 1
Was in close contact.

【0022】なお、本実施例ではパッド3の直径rを1
50μmに設定し、マスク5の厚さtを100μmに設
定した。また、前記開口6の直径aを220μm〜50
0μmの範囲内で五段階(220 μm,270 μm, 310 μ
m,370 μm,500 μm)に設定することにより、表1
に示すような五種類の試験サンプル〜とした。
In this embodiment, the diameter r of the pad 3 is set to 1
The thickness t of the mask 5 was set to 50 μm, and the thickness t of the mask 5 was set to 100 μm. Further, the diameter a of the opening 6 is 220 μm to 50 μm.
Five steps within the range of 0 μm (220 μm, 270 μm, 310 μm
m, 370 μm, 500 μm)
The following five kinds of test samples are shown.

【0023】次いで、マスク5を設けた状態ではんだペ
ーストS1 の印刷を行い、開口6内にはんだペーストS
1 を充填した(図2参照)。なお、本実施例で使用した
はんだペーストS1 のはんだ粒の粒径は40μmであ
り、粘度は40〜100×10 4 cps に調整されてい
る。また、前記はんだペーストS1 中に占めるはんだ粒
の体積の逆数αの値については、表1に示されるように
試験サンプル〜毎に異なる値となっている。
Next, with the mask 5 provided, the solder paste is
The solder paste S is printed in the opening 6 by printing the solder S1.
1 (see Figure 2). In addition, used in this example
The grain size of the solder particles of the solder paste S1 is 40 μm.
The viscosity is 40-100 × 10 Four adjusted to cps
It Also, the solder particles occupying in the solder paste S1
For the value of the reciprocal α of the volume of, as shown in Table 1,
The test sample has different values.

【0024】次に、はんだペーストS1 を印刷した後に
マスク5をAlN配線板1の表面から除去し、はんだペ
ーストS1 のみをAlN配線板1の表面に残した(図3
参照)、更に、はんだペーストS1 を一旦230℃に加
熱してから室温まで冷却するというリフローを行った
後、はんだペーストS1 中に含まれているフラックスを
除去するために所定の洗浄を行った。以上の工程によ
り、図4に示すような球欠形のはんだバンプS2 をパッ
ド3上に形成した。
Next, after printing the solder paste S1, the mask 5 was removed from the surface of the AlN wiring board 1, leaving only the solder paste S1 on the surface of the AlN wiring board 1 (FIG. 3).
Further, after performing reflow of heating the solder paste S1 once to 230 ° C. and then cooling it to room temperature, predetermined cleaning was performed to remove the flux contained in the solder paste S1. Through the above steps, ball-shaped solder bumps S2 as shown in FIG. 4 were formed on the pads 3.

【0025】このような工程により得られる試験サンプ
ル〜について、それぞれリフローによって形成され
るはんだバンプS2 の高さhs と体積Vs とを測定し、
その平均値(N=80)を求めた。これらの結果を表1
に示す。そして、上述の関係式に基づいて算出される理
論値と前記実測値とを比較するために、hs /ht の値
を求めた。同結果についても表1に示す。
The heights hs and the volumes Vs of the solder bumps S2 formed by reflow are measured for the test samples obtained by the above steps.
The average value (N = 80) was calculated. These results are shown in Table 1.
Shown in. Then, in order to compare the theoretical value calculated based on the above relational expression with the actual measurement value, the value of hs / ht was obtained. The results are also shown in Table 1.

【0026】[0026]

【表1】 [Table 1]

【0027】その結果、表1より明らかなように、いず
れの試験サンプルにおいてもhs /ht の値が1に近い
値となり、理論値と殆ど同じ結果となっていることがわ
かった。このように、本実施例のはんだバンプS2 の形
成方法によると、はんだバンプS2 の高さhs の制御を
容易にかつ極めて正確に行うことができるという結論に
達する。
As a result, as is clear from Table 1, it was found that the hs / ht value was close to 1 in all the test samples, which was almost the same as the theoretical value. As described above, according to the method of forming the solder bump S2 of the present embodiment, it is concluded that the height hs of the solder bump S2 can be controlled easily and extremely accurately.

【0028】また、このはんだバンプ形成方法では、は
んだバンプS2 の高さhs を決定する可変可能なファク
ターとして、四種のもの(α,r,a,t)が存在して
いることになる。本実施例では、前記各ファクターのう
ち任意のものを選択したうえで、上述した関係式に基づ
き、はんだバンプS2 の高さhs を設定することができ
る。
Further, in this solder bump forming method, there are four kinds of variable factors (α, r, a, t) which determine the height hs of the solder bump S2. In this embodiment, the height hs of the solder bump S2 can be set based on the above relational expression after selecting any one of the above factors.

【0029】このことは、例えば配線板上に大きさの異
なるパッドがある場合や、はんだバンプ高さをパッド毎
に変更したい場合などであっても、各々の状況に応じて
細かい設定が可能となることを意味している。
This means that even if there are pads of different sizes on the wiring board, or if it is desired to change the solder bump height for each pad, it is possible to make detailed settings according to each situation. Is meant to be.

【0030】なお、本発明は上記実施例のみに限定され
ることはなく、以下のように変更することが可能であ
る。例えば、 (a)実施例のようなAlN基板2を用いた配線板1以
外にも、例えばアルミナ基板や窒化ホウ素基板等の他の
セラミックス基板を用いた配線板に代えることができ
る。
The present invention is not limited to the above embodiment, but can be modified as follows. For example, (a) In addition to the wiring board 1 using the AlN substrate 2 as in the embodiment, it is possible to replace it with a wiring board using another ceramic substrate such as an alumina substrate or a boron nitride substrate.

【0031】(b)マスク5の開口6は必ずしも円形で
なくても良く、例えば楕円や卵形等であっても良い。開
口6をこれらのような形状にすることは、ファイン化に
よってパッド3が狭ピッチ化した場合などに有利にな
る。
(B) The opening 6 of the mask 5 does not have to be circular, and may be, for example, elliptical or oval. Forming the openings 6 in such a shape is advantageous when the pitch of the pads 3 is narrowed due to the fineness.

【0032】(c)本発明はマザーボードとして使用さ
れるセラミックス配線板へのはんだバンプ形成のみに限
定されることはなく、例えばLCC(リードレス・チッ
プ・キャリア)のパッドへのはんだバンプ形成などにも
勿論応用できる。
(C) The present invention is not limited to the formation of solder bumps on a ceramic wiring board used as a mother board, but may be applied to, for example, formation of solder bumps on pads of an LCC (leadless chip carrier). Of course, it can be applied.

【0033】[0033]

【発明の効果】以上詳述したように、本発明のセラミッ
クス配線板のはんだバンプ形成方法によれば、はんだバ
ンプ間のショートや実装信頼性の低下等を招かない範囲
で、はんだバンプの大きさ制御を容易にかつ正確に行う
ことができるという優れた効果を奏する。
As described in detail above, according to the method for forming solder bumps of a ceramic wiring board of the present invention, the size of the solder bumps is reduced to the extent that a short circuit between solder bumps and deterioration of mounting reliability are not caused. It has an excellent effect that control can be performed easily and accurately.

【図面の簡単な説明】[Brief description of drawings]

【図1】AlN配線板上にマスクを配置した状態を示す
部分拡大平面図である。
FIG. 1 is a partially enlarged plan view showing a state in which a mask is arranged on an AlN wiring board.

【図2】AlN配線板上にはんだペーストを印刷した状
態を示す部分拡大正断面図である。
FIG. 2 is a partially enlarged front sectional view showing a state in which a solder paste is printed on an AlN wiring board.

【図3】AlN配線板からマスクを取り外した状態を示
す部分拡大正断面図である。
FIG. 3 is a partially enlarged front sectional view showing a state in which a mask is removed from an AlN wiring board.

【図4】はんだペーストをリフローさせた状態を示す部
分拡大正断面図である。
FIG. 4 is a partially enlarged front sectional view showing a state where the solder paste is reflowed.

【図5】従来方法において、はんだペーストの印刷量が
パッドに比べて多過ぎる状態を示す部分拡大正断面図で
ある。
FIG. 5 is a partially enlarged front cross-sectional view showing a state in which a printing amount of a solder paste is too large as compared with a pad in a conventional method.

【図6】従来方法において、はんだペーストの印刷量が
パッドに比べて少な過ぎる状態を示す部分拡大正断面図
である。
FIG. 6 is a partially enlarged front cross-sectional view showing a state in which a printing amount of a solder paste is too small as compared with a pad in a conventional method.

【符号の説明】[Explanation of symbols]

1…セラミックス配線板としてのAlN配線板、3…
(金属製円形)パッド、5…マスク、6…開口、S1 …
はんだペースト、S2 …はんだバンプ、r…金属製円形
パッドの直径、t…マスクの厚さ、a…マスクの開口の
直径。
1 ... AlN wiring board as a ceramic wiring board, 3 ...
(Metallic circular) pad, 5 ... Mask, 6 ... Opening, S1 ...
Solder paste, S2 ... Solder bump, r ... Metal circular pad diameter, t ... Mask thickness, a ... Mask opening diameter.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】セラミックス配線板(1)表面の金属製円
形パッド(3)上にマスク(5)を設けた状態ではんだ
ペースト(S1 )を印刷し、次いでそのマスク(5)を
セラミックス配線板(1)から除去し、更に前記はんだ
ペースト(S1 )をその融点以上の温度に一旦加熱して
から冷却するセラミックス配線板(1)のはんだバンプ
(S2 )形成方法において、 前記マスク(5)の開口(6)の直径aを前記金属製円
形パッド(3)の直径rよりも大きくすると共に、該開
口(6)の直径aを50μm〜1000μmとしかつ該
金属製円形パッド(3)の直径rを50μm〜500μ
mとし、更に前記マスク(5)の厚さtを10μm〜3
00μmとすることを特徴としたセラミックス配線板の
はんだバンプ形成方法。
1. A solder paste (S1) is printed with a mask (5) provided on a circular metal pad (3) on the surface of a ceramic wiring board (1), and then the mask (5) is attached to the ceramic wiring board. In the method for forming solder bumps (S2) of a ceramic wiring board (1), the solder paste (S1) is removed from (1), and the solder paste (S1) is once heated to a temperature higher than its melting point and then cooled. The diameter a of the opening (6) is made larger than the diameter r of the metal circular pad (3), the diameter a of the opening (6) is set to 50 μm to 1000 μm, and the diameter r of the metal circular pad (3) is set. 50 μm to 500 μ
m, and the thickness t of the mask (5) is 10 μm to 3
A method for forming solder bumps on a ceramic wiring board, which is characterized in that the thickness is 00 μm.
JP3213593A 1993-02-22 1993-02-22 Formation of solder bump on ceramic wiring board Pending JPH06252152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3213593A JPH06252152A (en) 1993-02-22 1993-02-22 Formation of solder bump on ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3213593A JPH06252152A (en) 1993-02-22 1993-02-22 Formation of solder bump on ceramic wiring board

Publications (1)

Publication Number Publication Date
JPH06252152A true JPH06252152A (en) 1994-09-09

Family

ID=12350458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3213593A Pending JPH06252152A (en) 1993-02-22 1993-02-22 Formation of solder bump on ceramic wiring board

Country Status (1)

Country Link
JP (1) JPH06252152A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104127A (en) * 1996-04-16 1998-01-06 Ngk Spark Plug Co Ltd Manufacture of board having solder bump
JPH10256307A (en) * 1997-03-13 1998-09-25 Ngk Spark Plug Co Ltd Wiring board with semiconductor device, wiring board and manufacture thereof
US6857361B2 (en) * 2001-06-01 2005-02-22 Nec Corporation Method and apparatus for printing solder paste of different thickness on lands on printed circuit board
US8525042B2 (en) 2009-01-21 2013-09-03 Fujitsu Limited Printed circuit board and printed circuit board unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104127A (en) * 1996-04-16 1998-01-06 Ngk Spark Plug Co Ltd Manufacture of board having solder bump
JPH10256307A (en) * 1997-03-13 1998-09-25 Ngk Spark Plug Co Ltd Wiring board with semiconductor device, wiring board and manufacture thereof
US6857361B2 (en) * 2001-06-01 2005-02-22 Nec Corporation Method and apparatus for printing solder paste of different thickness on lands on printed circuit board
US8525042B2 (en) 2009-01-21 2013-09-03 Fujitsu Limited Printed circuit board and printed circuit board unit

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