JPH0625076Y2 - Pace sound generator with pager function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pace sound generator with a pager function that is convenient for emergency contact with a person who is jogging.

[Background of the Invention] Conventionally, a pace sound generating device, that is, a pacemaker for jogging, which generates a sound at a selected pace and runs in accordance with the sound when jogging, has been put to practical use.

On the other hand, a pager (that is, a pager) is widely used as a convenient means for making emergency contact with a person who goes out.

By the way, it is extremely troublesome for a person who uses the pace sound generator to carry a pager in addition to the pace sound generator in order to receive an emergency call, even though both are small devices. In addition, since my nerves are concentrated on the pace sound during jogging, the pager may not notice the reception notification sound.

[Object of the Invention] The present invention has been made in view of the above background.
An object of the present invention is to provide a pace sound generator with a pager function that eliminates the bothersomeness of having both the pace sound generator and the pager when jogging, and that can reliably recognize the reception of the pager even during jogging. And

[Summary of the Invention] In order to achieve the above object, the invention adds a pager function to a pace sound generating device and stops generation of pace sound when the pager function unit receives a signal addressed to itself. However, the point is that the reception is notified by a sound different from the pace sound.

[Embodiment] The present invention will be specifically described below based on an embodiment shown in the drawings.

Configuration FIG. 1 shows the circuit configuration of this embodiment. In the figure, 1 is an antenna, and the receiving circuit 2 is a circuit which demodulates the FM radio wave received by the antenna 1 and sends out a bit string consisting of "1" and "0". The reception control circuit 3 receives a bit string from the reception circuit 2, that is, a reception signal, and outputs a timing signal output circuit 1 described later.
2 and the ID number stored in the ID-ROM 4 are read out, the ID number contained in the received signal is compared, and when a match between the two is detected, the OR gate 13 is turned on. It is a circuit for sending out the call detection signal c to the RS flip-flop 15, the control signal d to the RAM address control unit 5, and the message data (including call type data. The same applies hereinafter) received in the RAM 6 via the RS flip-flop 15. The RAM address control unit 5 receives the control signal d and the one-shot signal from the one-shot circuit 20, and sends a read / write signal e to the RAM 6 to instruct writing or reading and to specify an address related to the writing or reading. It is a circuit that performs. R
The AM 6 is a circuit unit that stores the message data sent from the reception control circuit 3 or reproduces and sends the message data under the control of the RAM address control unit 5, and stores the received message data a plurality of times. it can. The bus control gate 7 is opened by an output Q from an RS flip-flop 15, which will be described later, and sends the message data from the RAM 6 to the display buffer 8.

The display buffer 8 includes a bus control gate 7 or a bus control gate 28, which will be described later, for displaying on the display unit 10.
This is a circuit unit for temporarily setting the message data or time data sent via the. The driver 9 is a circuit unit that takes in the data set in the display buffer 8, converts it into a display drive signal, and sends it to the display unit 10. The display unit 10 uses the display drive signal from the driver 9 to send message data or time. It is a circuit unit that displays data. The oscillator 11 constantly outputs a signal of a constant frequency, and the timing signal output circuit 12 divides the above-mentioned signal from the oscillator 11 into a pace sound signal generating circuit 35 described later, a signal a, and a ringing sound signal generating circuit 36. Signal b (the frequency of which is significantly different from that of signal a) is transmitted, and when the AND gate 26 is opened, a 1 Hz signal is transmitted to the clock measuring circuit 27 via this, and A signal f of a predetermined frequency is also sent to the pace signal generating circuit 33. When the call detection signal c or the one-shot signal from the one-shot circuit 20 is sent, the OR gate 13 sends them to the RS flip-flop 15 as a set signal. When the one-shot signal from the one-shot circuit 21 or the carry signal from the 30-second counter 18 described later is sent, the OR gate 14 sends them to the RS flip-flop 15 as a reset signal. RS
The flip-flop 15 receives the above set signal sent through the OR gate 13, enters the set state, outputs the output Q, receives the reset signal sent through the OR gate 14, enters the reset state, and outputs an inverted output. It is a flip-flop. AND gate 16 is R
It is opened by the output Q of the S flip-flop 15, and the 1 Hz signal from the timing signal output circuit 12 is given to the 30-second counter 18. OR gate 17 is a one-shot circuit 2
The signal from 0 or 21 is given to the 30-second counter 18 as a reset signal. The 30-second counter 18 counts the 1 Hz signal sent through the AND gate 16, sends a carry signal to the RS flip-flop 15 through the OR gate 14 after 30 seconds, and is sent through the OR gate 17. It is a counter that is reset by an incoming signal.

The one-shot circuit 20 is a circuit that sends a one-shot signal each time the read switch S ₁ is operated, and the one-shot circuit 21 is a circuit that sends a one-shot signal each time the return switch S ₂ is operated. . A circuit 23 sends a one-shot signal to the timepiece measuring circuit 27 as a reset signal every time the clear switch S ₃ is operated.
The one-shot circuit 24 is a start / stop switch S
₄ is a circuit that sends out a one-shot signal each time it is operated. The T flip-flop 25 switches the output Q _T from H level to L level or from L level to H level each time there is a one shot signal from the one shot circuit 24. It is a flip-flop that outputs The AND gate 26 is opened by the inverted output and the output Q _T , and the timing signal output circuit 12 gives a 1 Hz signal to the clock measuring circuit 27. The clock measuring circuit 27 is a circuit that counts the 1 Hz signal sent through the AND gate 26 and measures the passage of time. The bus control gate 28 is opened by the inverted output, and sends the time measured by the clock measuring circuit 27, that is, time data, to the display buffer 8.

The one-shot circuits 30 and 31 are switches S, respectively.
Each time ₅ and S ₆ are operated, it is a circuit which sends out a one-shot signal respectively. The up-down counter 32 increases the count value by 1 each time there is a one-shot signal from the one-shot circuit 30, and The count value is incremented by 1 each time there is a one-shot signal from the circuit 31.
It is a counter that only makes it small. The pace signal generation circuit 33 is a circuit that takes in the count value of the up / down counter 32, creates a pulse signal of a predetermined width at a corresponding time interval based on the signal f from the timing signal output circuit 12, and sends it out. is there. The AND gate 34 is a circuit which is opened by the inverted output and the output Q _{T and} supplies the pulse signal from the pace signal generating circuit 33 to the pace sound signal generating circuit 35. Pace sound signal generation circuit 3
Every time the pulse signal is sent through the AND gate 34, the signal 5 drives the speaker 37 with the signal a having a predetermined frequency, and generates a pace sound corresponding to the signal a. On the other hand, the ringing tone signal generation circuit 36 receives the ringing detection signal c, drives the speaker 37 with the signal b of a predetermined frequency for a certain period of time, and generates the ringing tone corresponding to this signal b.

Operation Next, the operation of the present embodiment configured as described above will be described.

First of all, before carrying out jogging while possessing this embodiment,
The switches S ₅ and S ₆ are operated to set the value corresponding to the desired pace in the up / down counter 32. In this case, the set value of the up / down counter 32 is increased or decreased by 1 each time the switch S ₅ or S ₆ is operated. Next, the return switch S ₂ is operated to operate the clock measuring circuit 2
The time data of 7 is displayed on the display unit 10. At this time, the one-shot signal is sent from the one-shot circuit 21 by the operation of the return switch S ₂ , and this is given to the RS flip-flop 15 via the OR gate 14 to reset the RS flip-flop 15 and also via the OR gate 17. It is also given to the 30-second counter 18, and this 30-second counter 18 is reset. R above
When the S flip-flop 15 is reset, it sends out an inverted output, the bus control gate 28 is opened, and if there is time data that is still set in the clock measurement circuit 27, this is the opened bus control. It is given to the display buffer 8 through the gate 28 and displayed on the display unit 10 by the driver 9. Therefore, when the time data is displayed on the display unit 10, the time data at the time of the previous jogging remains in the clock measuring circuit 27 as it is, and the user presses the clear switch S ₃ to clear it. Manipulate. In response to this operation, the one-shot signal is sent from 23, and the timepiece measuring circuit 27 is cleared. As a result, the time data displayed on the display unit 10 also becomes zero.

After the above preparation, jogging is started and the start / stop switch S ₄ is operated. At this time, the one-shot signal is sent from the one-shot circuit 24 by the operation of the start / stop switch S ₄ , and thereby the output Q _T is sent from the T flip-flop 25, but the inverted output already sent and this output The AND gate 26 and the AND gate 34 are opened by Q _T. Then, thereafter, the 1 Hz signal from the timing signal output circuit 12 is passed through the AND gate 26 and the clock measurement circuit 2
7, the clock measuring circuit 27 measures the elapsed time from the operation of the start / stop switch S ₄ , and the signal sent from the pace signal generating circuit 33 at a constant time interval is passed through the AND gate 34. To the pace sound signal generation circuit 35, and the pace sound signal generation circuit 35
Drives the speaker 37 to generate a pace sound at the constant time intervals. The time data measured by the clock measuring circuit 27 is the bus control gate 2 that is open.
It is sequentially sent to the display buffer 8 via 8, and the driver 9 displays it on the display unit 10. In this case the user
By jogging at the pace sound, the user can jog at a constant pace, and the time elapsed from the start of jogging can be easily known.

When there is a radio wave transmitted to call a person who is jogging during jogging as described above, the radio wave is sent to the receiving circuit 2 via the antenna 1.
The reception circuit 2 converts the signal into a reception signal and supplies it to the reception control circuit 3. The reception control circuit 3 synchronizes the reception signal with the signal from the timing signal output circuit 12, and then confirms that the reception signal includes the same ID number as the ID number stored in the ID-ROM 4, and calls the reception signal. The detection signal c is sent to the RS flip-flop 15 via the OR gate 13 and is also given to the call signal generation circuit 36, and the control signal d is set to R
It is given to the AM address control unit 5, and further, the portion related to the message in the received signal is sent to the RAM 6. Then, the RS flip-flop 15 which has received the call detection signal c enters the set state, outputs the output Q, and opens the AND gate 16 and the bus control gate 7. When the AND gate 16 is opened, a 1 Hz signal from the timing signal output circuit 12 is given to the 30-second counter 18, and the 30-second counter 18 starts measuring 30 seconds.

On the other hand, since the inverted output is not sent from the RS flip-flop 15, the bus control gate 28, the AND gate 26, and the AND gate 34 are closed, and the time data of the clock measuring circuit 27 is not sent to the display buffer 8 and the clock measuring is performed. The clock measuring operation of the circuit 27 is stopped, and the operation of the pace sound signal generating circuit 35 is also stopped so that the pace sound is not generated. Further, the ringing tone signal generation circuit 36 to which the ringing detection signal c is given, the speaker 37 with the signal b for a certain period of time.
Drive a ringing tone. Further, the RAM address control unit 5 receiving the control signal d commands the RAM 6 to write by the read / write signal e and also specifies the address to write. As a result, the RAM 6 stores the message sent from the reception control circuit 3 in the portion addressed by the RAM address control unit 5.

Further, after the storage of the RAM 6 is completed, the read / write signal e for instructing the read is issued from the RAM address control unit 5.
Is sent to the display buffer 8 via the bus control gate 7 which has opened the message stored immediately before. The message thus sent is temporarily set in the display buffer 8 and then displayed on the display unit 10 by the driver 9.

At this time, the user of the present embodiment easily recognizes that there is a call to himself, because the pace sound stops, and instead, a ringing sound of a sound different from the pace sound starts to be displayed, You will see Part 10. Thus, the message relating to the call can be easily known.

After the above-mentioned state continues for 30 seconds, a carry signal is sent from the 30-second counter 18 and this is given as a reset signal to the RS flip-flop 15 via the OR gate 14, and the RS flip-flop 15 enters the reset state. , The output Q is stopped and the inverted output is restarted. When the output Q is stopped, the bus control gate 7 and the AND gate 16 are closed, the display of the message on the display unit 10 is stopped, and the operation of the 30-second counter 18 is also stopped. Further, since the transmission of the inverted output is restarted, the bus control gate 28,
The AND gates 26 and 34 are opened to display the time data of the timepiece measurement circuit 27 on the display unit 10, the timekeeping operation of the timepiece measurement circuit 27, the pace sound signal generation circuit 35, and the speaker 37.
Generation of the pace sound is restarted.

It should be noted that the return switch S ₂ can be operated before the lapse of 30 seconds from the ringing tone to forcibly restart the generation of the pace sound or the like. At this time, in response to the operation of the return switch S ₂ , the one-shot signal from the one-shot circuit 21 resets the 30-second counter 18 via the OR gate 17 and also serves as a reset signal to the RS flip-flop 15 via the OR gate 14. Given this RS
The flip-flop 15 is reset. Since the RS flip-flop 15 is in the reset state, the display of the message is stopped, the operation of the 30-second counter 18 is stopped, the time data is displayed on the display unit 10, and the clock measurement circuit 27 is used as in the case described above. The measurement operation of and the generation of pace sound resume.

When the jogging is completed as described above, the start / stop switch S ₄ is operated to stop the measuring operation of the timepiece measuring circuit 27. At this time, in response to the operation of the start / stop switch S ₄ , the one-shot signal is sent from the one-shot circuit 24, and the output of the output Q _T is stopped from the T flip-flop 25 to which the one-shot signal is input. Therefore, the AND gates 26 and 34 are closed, and the clock measuring circuit 2
7, the measurement operation and the generation of pace sound are stopped. Thus, the time required for jogging remains set in the clock measuring circuit 27, and this time is sent to the display buffer 8 and the driver 9 via the open bus control gate 28 and displayed on the display unit 10. To be done. For this reason, the user has to wait for the time required for jogging
When 7 stops, it is easy to recognize that jogging is not performed).

When the message received during jogging is reconfirmed after the jogging ends, the read switch S ₁ is operated. At this time, the one-shot signal sent from the one-shot circuit 20 is given to the RS flip-flop 15 via the OR gate 13 and puts it in the set state. R
When the S flip-flop 15 is set, the bus control gate 7 is opened and the bus control gate 28 is closed. Further, the one-shot signal is also given to the RAM address control unit 5, and the RAM address control unit 5 sends a read / write signal e for instructing the RAM 6 to read, and the address related to the previously stored message is sent. specify. As a result, the RAM 6 reads the message and sends it to the display buffer 8 via the open bus control gate 7. At this time, the time of the clock measuring circuit 27 has not been sent to the display buffer 8 because the bus control gate 28 is closed. As a result, the message received during jogging is displayed on the display unit 10.

The past received messages stored in the RAM 6 are sequentially read out by the operation of the read switch S _{1 and} are displayed on the display unit 1.
Although it is displayed at 0, in this case, the operation is similar to the above.

In addition, after confirming the message as described above, the display unit 1
To return to the state where the time data of the clock measuring circuit 27 is displayed at 0, the return switch S ₂ is operated. As a result, the one-shot signal sent from the one-shot circuit 21 is given to the RS flip-flop 15 via the OR gate 14 to return it to the reset state. As a result, the bus control gate 7 is closed, the bus control gate 28 is opened, and the time data of the clock measuring circuit 27 is again displayed on the display unit 10.

The present invention is not limited to the above-mentioned embodiment, and various modifications can be applied without departing from the invention.

[Effects of the Invention] As described in detail above, the present invention adds a pager function to the pace sound generator, and stops the generation of the pace sound when the pager function unit receives a signal addressed to itself. Since the present invention relates to a pace sound generator with a pager function that notifies the reception by a sound different from the pace sound, it eliminates the trouble of having both the pace sound generator and the pager when jogging. In addition, it is possible to provide a pace sound generator with a pager function that can surely recognize signal reception in the pager function section even during jogging.

[Brief description of drawings]

FIG. 1 shows the circuit configuration of an embodiment of the present invention. 1 ... Antenna, 2 ... Reception circuit, 3 ... Reception control circuit, 4 ... ID-ROM, 5 ... RAM address control unit, 6 ... RAM, 7 ... Bus control gate, 8
…… Display buffer, 9 …… Driver, 10 …… Display section,
11 ... Oscillator, 12 ... Timing signal output circuit, 1
5 ... RS flip-flop, 18 ... 30 second counter, 20-24 ... one-shot circuit, 25 ... T flip-flop, 27 ... clock measuring circuit, 30,31 ...
One shot circuit, 32 ... Up / down counter, 3
3 ...... pacing signal generating circuit, 35 ...... pace sound signal generator circuit, 36 ...... ringing tone signal generating circuit, 37 ...... speaker, _{S 1} ...... read switch, _{S 2} ...... return switch, S
₃ ...... clear switch, _{S 4} ...... start-stop _{switch, S 5,} S ₆ ...... switch.

Claims (2)

[Scope of utility model registration request] 1. A pace setting means, a pace sound generating means for generating a pace sound set by the pace setting means, a receiving means, and a pace sound generation when a signal addressed to itself is received by the receiving means. A pace sound generating apparatus with a pager function, comprising: a reception notification means for stopping the generation of the pace sound by the means and for notifying reception by a sound different from the pace sound. 2. A time measuring means for measuring the time after the pace sound generating means starts generating the pace sound, a display means for displaying the time measured by the time measuring means, and a self-addressed one for the receiving means. 2. A pacer with a pager function according to claim 1, further comprising display switching means for switching the display of said display means from the time measured by said time measuring means to the received data received by said receiving means when a signal is received. Sound generator.